CN101409280A - Well potential triggered ESD protection - Google Patents

Abstract

The present invention provides an integrated circuit for providing ESD protection. The integrated circuit comprises a transistor device having at least one interleaved finger having a substrate region, a source, drain and gate region formed over a channel region disposed between the source and the drain regions. The transistor device further comprises at least one highly doped junction formed adjacent to the source region to measure voltage potential of the substrate region. The integrated circuit further comprises a switching circuit coupled to the at least one highly doped junction such that the voltage potential is transferred to the switching circuit to either draw the full ESD current or trigger to draw the full ESD current.

Description

Well potential triggered ESD protection

The cross reference of related application

The application requires in the U.S. Provisional Patent Application No.60/869 of submission on December 11st, 2006, and 364 priority is incorporated its content into as a reference at this.

Technical field

The present invention relates generally to the field of Electrostatic Discharge protective circuit, and more clearly be used to output protection that improvement is provided.The present invention also helps to protect core transistor under the situation of charging device model (CDM) stress situation or similar stress.

Background technology

Integrated circuit (IC) and other semiconductor device are to extremely responsive by contact producible high voltage with esd event.Therefore, the Electrostatic Discharge protective circuit is essential to integrated circuit.Esd event is usually by the discharge generation of high voltage (being typically several kilovolts), and causes the short time high electric current (several amperes) pulse of (being typically 100ns).Say that intuitively esd event is to contact with the lead-in wire of IC or by the discharge and produce in that IC is inner in other lead-in wire of IC of the equipment that charged by the people.In the process that integrated circuit is installed in the product, these static discharges may destroy or weaken the function of IC, and therefore need carry out expensive repairing to product, and this can provide dissipation mechanism to be avoided by the static discharge that may stand IC.For the ESD phenomenon during the emulation chip ground connection, use three kinds of models at present.Manikin (HBM) and mechanical model (MM) are 2 pins tests (a pin ground connection, and another pin adds plus or minus stress).When IC self is recharged, can discharge by a pin.Such stress is modeled in charging device model (CDM).

In order to protect IC to avoid ESD, on chip, add the special protection circuit.All circuit that are directly connected to bonding welding pad (bond pad) all must be able to bear limited amount ESD stress.Therefore, these pads have coupled esd protection circuit.But also the ESD fault may take place in IC core inside.Particularly the input and output pin needs extra protection, because these circuit are connected to pad.Notice that identical bonding welding pad can be used for being connected with input, make can use identical protection protect input and output both.

In the prior art, propose protection and exported the different modes that avoids ESD.Under first kind of situation, output is self-shield.This follows the serious shortcoming that increases of driver area usually, handles all ESD electric currents because need to add illusory interdigital (dummy finger).In addition, in most of technologies, need increase required area once more, also increase conducting resistance leaking and/or the measure of source adding ballast.In some technologies, this method is infeasible, because driver lacks the ability of reply ESD electric current inherently.

Under second kind of situation, use the double diode method, combine with circuit sometimes, so that driver is off-state during ESD.The ESD electric current is changed direction by a diode and power supply clamper, makes driver keep safety.In this case, driver can keep complete silication (promptly not using the ballast measure) and minimum dimension (being the required size of operate as normal).The major advantage of this solution is its minimized in size, but the triggering of power supply clamper is required very strictness, and this is because trigger voltage must be hanged down with the protection driver very much.

In the third solution, first and second kinds of situations are made up.In this case, placed isolation resistance, and driver is made stalwartness with processing section ESD electric current, in most of the cases means to have added the ballast measure, and has also increased illusory interdigital sometimes.Isolation resistance is calculated as by allowing to make the power supply clamper trigger in the time of can be at high voltage setting up some voltages on the resistance during the ESD.

As the 4th kind of solution, added localised protection.This localised protection (as the situation for the power supply clamper) can be voltage, RC or current trigger.Difficulty in this case is to make clamper with enough low voltage triggered again.

Therefore, exist in the art the shortcoming that overcomes prior art the ESD circuit is provided the needs of improved output protection.

Summary of the invention

In one embodiment of the invention, provide a kind of Electrostatic Discharge protective circuit.This circuit comprises the area of the lightly doped region with first conduction type, and on area, form at least one is staggered interdigital.This at least one the staggered interdigital source region of at least one second conduction type, the drain region of at least one second conduction type and at least one grid region that forms on channel region of comprising, this channel region is between source region and drain region.This circuit further comprises the highly doped knot of at least one first conduction type that is adjacent to form with at least one interdigital source region that interlocks.This at least one highly doped knot is used to measure the voltage of area.

In another embodiment of the present invention, provide a kind of integrated circuit that is used to provide esd protection.This circuit comprises the MOS transistor with the area that comprises the first conduction type lightly doped region, and at least one that forms on described area is staggered interdigital.This at least one the staggered interdigital source region of at least one second conduction type, the drain region of at least one second conduction type and at least one grid region that forms on channel region of comprising, this channel region is between source region and drain region.This circuit also comprises the highly doped knot of at least one first conduction type that is adjacent to form with at least one interdigital source region that interlocks.This at least one highly doped knot is used to measure the voltage of area.This circuit further comprises the voltage that the switching circuit that is connected at least one highly doped knot is used to trigger with reception.

Description of drawings

Figure 1A illustrates the profile of esd protection circuit according to an embodiment of the invention.

Figure 1B illustrates the transistorized schematic circuit of Figure 1A.

Fig. 2 A illustrates the different execution modes of the esd protection circuit that is used for how interdigital device of the trap potential measurement knot that uses Figure 1A and Figure 1B to Fig. 2 C.

Fig. 3 A illustrates and uses the esd protection circuit of Figure 1A and 1B to add the structure chart of switching circuit according to another embodiment of the present invention.

Fig. 3 B and 3C illustrate the figure that schematically shows according to the circuit diagram of Fig. 3 A structure chart of alternate embodiment of the present invention.

Fig. 4 A illustrates the structure chart that the esd protection circuit that uses Fig. 3 A adds the voltage transmission circuit of the additional embodiments according to the present invention.

Fig. 4 B illustrates the figure that schematically shows according to the circuit diagram of Fig. 4 A structure chart of alternate embodiment of the present invention.

Fig. 5 A illustrates the structure chart that the esd protection circuit that uses Fig. 4 A adds the voltage shifter of root a tree name another embodiment of the present invention.

Fig. 5 B illustrates the figure that schematically shows according to the circuit diagram of Fig. 5 A structure chart of alternate embodiment of the present invention.

Fig. 6 illustrates the figure that schematically shows according to the circuit diagram of Fig. 5 A structure chart with add ons of alternate embodiment of the present invention.

Embodiment

The present invention relates to the protection of output node.More specifically, the present invention proposes to use the trap electromotive force to trigger the method for esd protection.Notice that this " trap " can be N trap, P trap, body (bulk), matrix (body), substrate, thereby or for enough low-doped can in this layer, set up transistorized any other layer.Simultaneously, introduce the invention of the NMOS of the CMOS piece technology that is used for using the P substrate although notice most of embodiment of the present invention and Tu, yet this invention is not limited to this situation.Any technical staff of this area can easily be converted to explanation the PMOS situation, and may use the present invention equally in other technology (SOI, many traps technology, high voltage etc.).In addition,, suppose that transistor to be protected is in the periphery of chip although in the present invention, can also use here open in disclosed method protect core transistor.

With reference to Figure 1A, wherein show the profile of the esd protection circuit 100 that is used to provide esd protection according to one embodiment of present invention.This circuit 100 comprises lightly doped region, is preferably the P substrate 102 of first conduction type.This circuit 100 further comprises for example transistorized semiconductor device 104, as shown the exemplary MOSFET in the P substrate 102.Transistor 104 preferably includes the first heavily doped region N+104a (leakage) of second conduction type, second heavily doped region N+104b (source) and the grid 104c of second conduction type.Typically, body region 106 preferably is connected to source 104b (Figure 1B) or ground (not shown), and this body region 106 preferably has the heavily doped region of the first conduction type P+.This circuit 100 further comprises the knot (also be called additional knot) 108 of the heavily doped region that preferably has the first conduction type P+, join in the P substrate 102 with can measure shown in Figure 1A and Figure 1B as described in electromotive force in the P substrate.

Notice that the also preferred heavily doped region 108 that adds is to avoid producing Schottky diode when placing contact.Typically, technological design rule forbids directly placing contact (promptly not adding heavily doped region) in substrate 102.Yet if be not this situation for special process, contact can directly be placed in the trap and not have a heavily doped region.

Notice that must isolate 110 incoming calls by placement between transistorized source 104b and the additional knot 108 isolates.Preferably can by between source 104b and additional knot 108, allow to form shallow trench isolation from (STI) or deep trench isolation (DTI) or even part trench isolations (PTI) form and isolate 110.Alternatively, under the situation of silicide process, can form by silicide agglomeration (SB) and isolate 110, or form isolation 110 by between source 104b and additional knot 108, placing polycrystalline grid (Poly gate).Similarly, can isolate 110 with control volume resistance by using STI, DTI, PTI, SB or polycrystalline between additional knot 108 and body region 106, to form.

Except that other parameter, the most important parameter of some of invention is that snowslide is leaked 104a, source 104b (being ambipolar collector electrode), additional knot 108 and is connected distance between 106 with body.By controlling these distances, for given drain source voltage, the voltage on the additional knot 108 is controlled.Usually, for given drain source voltage, additional knot 108 distances that are connected between 106 with body are big more, and the voltage on the additional knot 108 is high more.Similarly, for given drain source voltage, source 104a is more little with the distance of additional knot 108, and the additional voltage of tying is high more.Voltage range usually 0 and 0.7V between, 0.7V is the voltage that triggers in ambipolar pattern on the required body-source of driver.Owing to should avoid this triggering, all voltages in the trap should preferably be lower than 0.7V.Yet, in some cases, can add the restriction that electromotive force transmission circuit and/or voltage shifter circuit remove this 0.7V.Even in this case, exemplary voltages should not surpass several volts.The distance that adopts is subjected to the restriction of technological design rule.Each technology has minimum design rule for the distance between knot.For the present invention, typical range is within 1 to 5 times scope of minimum design rule.For example, in 65nm CMOS technology, this minimum design rule is the magnitude at 0.1um.Notice and the invention is not restricted to this distance range.

With reference now to Fig. 2 A, to 2C, wherein illustrates and have the generalized section that comprises according to several different execution mode of the esd protection circuit 200 of the how interdigital transistor device 104 of additional knot 108 of the present invention.In Fig. 2 A, illustrate only at additional 108 the how interdigital nmos device 104 that finishes of device one side.In Fig. 2 B, finish 108 in that the next door of each source 104b of transistor 104 knot is additional.In Fig. 2 C, only add and finish 108 at the 104b place, middle source region of transistor 104.Although notice the execution mode that the invention discloses the additional knot 108 as shown in Fig. 2 A, 2B and 2C, it will be appreciated by those skilled in the art that also to have many other the possible implementation methods that add knot.

The voltage of being measured by additional knot 108 preferably is transferred to switching circuit (following introduction), and this switching circuit can be drawn all ESD electric currents, or then triggers another switching circuit to draw all ESD electric currents.In order to explain the operation principle of this embodiment, must consider from bipolar behavior when the trap electromotive force is local when surpassing diode drop of source electromotive force (about 0.7V) MOS device.Typically, this flows through trap resistance so that the rising of trap voltage obtains by making the avalanche current that is produced by high electric field at drain terminal.Too big if desired avalanche current, if perhaps required high avalanche current flows through the quite long duration, then the heat that is produced by snowslide will damage device.Therefore, it is very important limiting required snowslide amount.By the trap electromotive force being transferred to trigger, can come the switch clamper with the low-voltage place via additional knot 108 of the present invention.Reduce this voltage and also mean the electric field that reduces drain electrode place, consequent heat still less.

Fig. 3 A illustrates and uses the esd protection scheme 100 shown in Figure 1A of the present invention and the 1B to add the schematically showing of structure chart 300 of the switching circuit 302 in parallel with transistor 104 as shown in the figure.As mentioned above, the voltage of being measured by additional knot 108 preferably is transferred to switching circuit 302, and this switching circuit 302 can be drawn all ESD electric currents or then trigger another switching circuit to draw all ESD electric currents.Using under the situation of two switching circuits, first is called " trigger ", and second be called " clamper ".Under the situation of only using a switching circuit, this device is called as " clamper ".Trigger and/or clamper both can be made up of one or more devices.These devices can be the combination in any of one or more diode, SCR, transistor (MOS, ambipolar or any other type), electric capacity, resistance, inductance or these elements.

Notice that in Fig. 3 A node A and E can be that separate or shared.Similarly, Node B and F can be that separate or shared.In most cases, node E is output, and Node B and F are ground, and node A and E are output or Vdd.At transistor 104 is in the another kind of execution mode of PMOS, and node A and E are Vdd, and node F is output, and Node B and F are output or ground.

With reference to figure 3B, wherein show the illustrative circuitry of structure chart 300 according to an alternative embodiment of the invention.In this embodiment, switching circuit 302 preferably comprises only SCR clamper 304, and it draws the ESD electric current fully by additional knot 108 transmission voltages the time.The voltage that triggers SCR304 in required being used to of G1 node is～0.7V, and this is with roughly the same for triggering the required voltage of driver 104 in double pole mode.Introduce the other execution mode of switching circuit 302 below.

With reference to figure 3C, shown in it according to the present invention the illustrative circuitry of the structure chart 300 of another alternate embodiment.As mentioned above, switching circuit 302 preferably includes SCR clamper 304 and trigger device 306, is NMOS 306 in this example, and both all are parallel-connected to driver 104.Particularly, as shown in Fig. 3 C, the base stage of trigger NMOS 306 is connected to the additional knot 108 of transistor 104.Notice that because transistorized behavior can be used for other element of drive circuit, transistor 104 also is called driver in the present invention.The voltage that is important to note that additional knot 108 is assumed to the electromotive force of the source 104c of driver NMOS 104 and equates.For preferred embodiment, this is to be suffered as the so near fact that is allowed in the technology with source 104c by additional knot 108 proving.

Introduce the operation principle of the circuit of Fig. 3 C here.Originally, when o pads (node E) when running into esd event, the drain voltage of driver 104 raises, and causes the generation snowslide of knot place, leakages-source.This avalanche current increases the trap electromotive force of transistor driver 104.In case this voltage reaches the threshold voltage vt h of trigger NMOS 306, then this trigger NMOS 306 is converted to " conducting " state, draws the ESD electric current thus.This ESD electric current will trigger SCR clamper 304.This threshold voltage is transistor (NMOS or PMOS) minimum voltage between grid and the source when being converted to conducting state.Because this clamper 304 is triggered, so this ESD electric current is shunted.Notice that if the threshold voltage of trigger NMOS 306 is lower than 0.7V, then this conversion still took place before driver 104 enters ambipolar pattern.Drop to the threshold voltage less than trigger NMOS 306 even be also noted that electromotive force, SCR 304 also remains on " conducting " state and continues to draw the ESD electric current.If the threshold voltage vt h of trigger NMOS 306 is greater than 0.7V, then driver 104 will enter ambipolar pattern.In this case, the known technology of ballast of must use for example draining makes driver healthy and strong and avoid triggering.Therefore, threshold voltage must be enough low, makes this protection trigger before can taking place in the fault of driver 104.

Fig. 4 A illustrates and uses the esd protection scheme 300 shown in Fig. 3 A of the present invention to add as shown in the figure the structure chart 400 that is connected in parallel on the electromotive force transmission circuit 402 between driver 104 and the switching circuit 302 that is preferably placed at.This electromotive force transmission circuit 402 preferably arrives switching circuit 302 with the voltage transmission of driver 104.Electromotive force transmission circuit 402 can provide many different functions.One of them function is to reduce in operate as normal because the noise in the substrate 102 of driver 104 triggers the possibility of esd protection.Execution mode for this situation comprises adding resistance (as what introduced with reference to following Fig. 4 B), adds electric capacity between additional knot and power line, perhaps adds one or more inverter stage.Another function of electromotive force transmission circuit 402 is that the voltage of amplification driver 104 triggers to help circuits for triggering 306.In this case, electromotive force transmission circuit 402 preferably includes amplifier circuit, but it can be designed as and makes the voltage Be Controlled be transferred to circuits for triggering 306 (increase or reduce electromotive force).The execution mode of this situation comprises the adding inverter stage, as Fig. 6 introduced with reference to following.Notice that the voltage of electromotive force transmission circuit 402 outputs can be different from the voltage of its input.

Notice that in Fig. 4 A, node A, C and E can be that separate or shared.Similarly, Node B, D and F can be that separate or shared.In most cases, node E is output, and Node B, D and F are ground, and node A, C and E are output or Vdd.At transistor 104 is in the another kind of execution mode of PMOS, and node A, C and E are Vdd, and node F is output, and Node B and D are output or ground.

With reference to Fig. 4 B of the present invention, shown in it according to the present invention the illustrative circuitry of the structure chart 400 of an alternate embodiment.In this embodiment, electromotive force transmission circuit 402 preferably includes resistance 404.Particularly, the grid of trigger 306 is connected to resistance 404, this resistance then be connected to the additional knot 108 of driver 104.The resistance substrate parallel connection that this resistance 404 is connected with the ground connection of driver 104, and allow to calculate thus in driver 104, trigger trigger NMOS 306 required the avalanche current amount.Notice that electromotive force transmission circuit 402 as shown in Figure 4 preferably includes resistance 404, but invention is not limited to the impedance component of any particular type, can be active or passive, for example diode, MOS device, trap resistance, electric capacity, SCR, inductance, short circuit etc.

Fig. 5 A illustrates and uses the esd protection scheme 300 shown in Fig. 4 A of the present invention to add the structure chart 500 of the voltage shifter 502 of the preferred placement of connecting with transistor driver 104 as shown in the figure.Voltage shifter 502 means that preferably any circuit or Butut change, and it is used to control and triggers transistor driver 104 and enter voltage between required trap/substrate of ambipolar pattern 102 and the source 104b.As discussed above, node A, C and E can be that separate or shared.Equally, Node B, D and F can separate or shared.In most cases, node E is output, and Node B, D and F are ground, and node A, C and E are output or Vdd.At transistor 104 is in the another kind of execution mode of PMOS, and node A, C and E are Vdd, and node F is output, and Node B and D are output or ground.

With reference to figure 5B, shown in it according to the present invention the illustrative circuitry of the structure chart 500 of an alternate embodiment.In this embodiment, the illustrative embodiments of voltage shifter 502 is a diode 504, and the anode of diode 504 is connected to the source 104b of driver 104, and the negative electrode of diode 504 is connected to body 106 and ground.In another embodiment, this diode 504 can substitute with transistor, and transistor can also provide special-purpose function equally in operate as normal, as following will introduce in detail with reference to figure 6.

With reference to figure 6, shown in it according to the illustrative circuitry 600 of the structure chart with add ons 500 of another alternate embodiment of the present invention.In this embodiment, the illustrative embodiments of voltage shifter 502 is transistor MN4506; And as shown in the figure, electromotive force transmission circuit 402 is an inverter stage circuit 406, and it has the combination that resistance R 1408 is connected with the capacitor C 1410 that is connected to voltage Vdd2 610.Circuit 600 also comprises the PMOS transistor 602MP1 of the drain electrode of the nmos pass transistor MN1 that is connected to driver 104.Circuit 600 further comprises the 602 last diodes 604 that also further are connected to voltage Vdd1 606 in parallel with MP1, as shown in Figure 6.Notice that Vdd1 606 and Vdd2 610 are for having any node of constant potential in normal work period.Vss 607 in the circuit 600 is preferably ground as shown in the figure.In addition, the output 608 of circuit 600 comprises PMOS transistor MP1602 and nmos pass transistor MN1 104.Circuit 600 illustrates more complicated connection, but is not meant to limit the present invention in any manner.As discussed above, the purpose of circuit 600 is the voltage of amplification driver 104, thereby can control transmission helps circuits for triggering 306 to the voltage of circuits for triggering 306 (increase or reduce electromotive force) and trigger by electromotive force transmission circuit 402 being designed to comprise inverter stage.This provides surplus for circuits for triggering 306, therefore allows the threshold voltage of trigger NMOS 306 higher.Introduce the operation principle of this embodiment herein, below.

Originally, when the voltage of output 608 raise owing to ESD, the voltage of Vdd1 606 also raise～0.7V or still less, this is the built-in voltage that goes up diode 608.Along with the voltage on the MN1104 raises, the electromotive force in trap/substrate 102 of MN1 104 also raises.Sometime, reach the threshold voltage of the MN2 of inverter stage circuit 604.Because be used as the voltage of the MN4 506 of voltage shifter, the threshold voltage of MN2 can reach and be higher than 0.7V.Notice that MN4 506 can have special function, promptly can switch under the normal condition of work of circuit.This is called as cascaded design well known to those skilled in the art.When MN2 was converted to " conducting ", MP2 was converted to " disconnection ", and this is because the trap electromotive force of MN1 104 is higher than the threshold voltage of MP2.This conversion of MP2 and MN2 causes MP3 to be converted to " conducting ".Therefore, electric current injects from Vdd2 line 610 by MP2 and by R1 408, sets up voltage on the grid of the MN5 of trigger 306.Notice that this moment, MN3 was in " disconnection " state.When MN5 306 conductings, it triggers SCR clamper 304.The ESD electric current can be shunted by safety by last diode 604 and SCR clamper 304 now.Notice that if add special-purpose triggering scheme, this clamper 304 also is preferably used as power supply clamper (being the Vdd-Vss protection).Equally, clamper 304 and trigger 306 can be easy to by a plurality of o pads (not shown) shared now.In addition, part or whole electromotive force transmission circuit 604 also can be shared by a plurality of o pads.Capacitor C 1 410 is preferred for stablizing the grid of MN5 304 in operate as normal, with the false triggering of avoiding causing owing to the substrate current in the trap of MN1 104.

Although be shown specifically and introduced the different embodiment in conjunction with the present invention instruction here, the embodiment that those skilled in the art can be easy to design in conjunction with these instructions many other variations does not deviate from the spirit and scope of invention.

Claims (25)

1, a kind of ESD protection circuit, be esd protection circuit, described circuit comprises:

Area with lightly doped region of first conduction type;

Basic at least one that forms on area is staggered interdigital; Described at least one the staggered interdigital source region of at least one second conduction type, the drain region of at least one second conduction type and at least one grid region that on the channel region between described source and the drain region, is forming of comprising; And

The highly doped knot of at least one first conduction type that is adjacent to substantially form with at least one described staggered interdigital source region, wherein said at least one highly doped knot is operationally measured the electromotive force of area.

2, esd protection circuit according to claim 1, wherein the described highly doped knot of first conduction type and described at least one source region electricity are isolated.

3, esd protection circuit according to claim 1 comprises that also the body that is placed in the described interdigital source region that interlocks connects, and described therein body connects the highly doped knot electricity isolation with described first conduction type.

4, esd protection circuit according to claim 3, it is a kind of formation in salicide piece or the silicide agglomeration that trench isolations, field oxide, polycrystalline grid, self-aligned silicide piece are used in wherein said electricity isolation.

5, require 1 described esd protection circuit according to power, wherein said first conduction type comprises a kind of in n or the p conduction type.

6, require 4 described esd protection circuits according to power, wherein said second conduction type comprises the another kind in n or the p conduction type.

7, a kind of integrated circuit that is used to provide esd protection, described circuit comprises:

MOS transistor comprises: the area with lightly doped region of first conduction type; Basic at least one that forms on described area is staggered interdigital, described at least one the staggered interdigital source region of at least one second conduction type, the drain region of at least one second conduction type and at least one grid region that is forming on the channel region between described source and the drain region of comprising; And the highly doped knot of at least one first conduction type that is used to measure the voltage of area, wherein said at least one highly doped knot and described at least one described staggered interdigital being adjacent to substantially form, and described at least one highly doped knot is used to measure the voltage of area; And

Be connected to the switching circuit of described at least one highly doped knot, be used to receive the described voltage that is used to trigger.

8, integrated circuit according to claim 7, wherein the described highly doped knot of first conduction type and described at least one source region electricity are isolated.

9, integrated circuit according to claim 8, it is a kind of formation in salicide piece or the silicide agglomeration that trench isolations, field oxide, polycrystalline grid, self-aligned silicide piece are used in wherein said electricity isolation.

10, integrated circuit according to claim 7 comprises that also the body that is placed in the described interdigital source region that interlocks connects, and wherein said body connects the highly doped knot electricity isolation with described first conduction type.

11, integrated circuit according to claim 10, it is a kind of formation in salicide piece or the silicide agglomeration that trench isolations, field oxide, polycrystalline grid, self-aligned silicide piece are used in wherein said electricity isolation.

12, integrated circuit according to claim 10, wherein said at least one highly doped knot and the distance between body is connected are controlled to control the voltage of area.

13, integrated circuit according to claim 7, wherein described switching circuit is triggered when described voltage is higher than the threshold voltage of described switching circuit.

14, integrated circuit according to claim 7, wherein said switching circuit comprises the SCR clamper.

15, integrated circuit according to claim 7, wherein said switching circuit comprise the SCR clamper and trigger combining of element that wherein said triggering element is connected to described at least one highly doped knot.

16, integrated circuit according to claim 15, wherein said triggering element comprises at least one transistor, wherein said transistorized grid are connected to described at least one highly doped knot.

17, integrated circuit according to claim 15, wherein said triggering element comprises at least one in SCR and the diode.

18, integrated circuit according to claim 7 also comprises the electromotive force transmission circuit that is connected between highly doped zone and the switching circuit.

19, integrated circuit according to claim 18, wherein said electromotive force transmission circuit comprises at least one in resistance, inductance, transistor, SCR or the electric capacity.

20, integrated circuit according to claim 18, wherein said electromotive force transmission circuit comprises at least one inverter circuit.

21, integrated circuit according to claim 10 also comprises the voltage shifter that is connected to body connection and source.

22, integrated circuit according to claim 21, wherein said voltage shifter comprises diode.

23, integrated circuit according to claim 21, wherein said voltage shifter comprises transistor.

24, integrated circuit according to claim 7, wherein said first conduction type comprise a kind of in n or the p conduction type.

25, integrated circuit according to claim 7, wherein said second conduction type comprises the another kind in n or the p conduction type.

Images