CN101404561B - Bit error rate estimation method, apparatus and receiver - Google Patents
Bit error rate estimation method, apparatus and receiver Download PDFInfo
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- CN101404561B CN101404561B CN2008102270090A CN200810227009A CN101404561B CN 101404561 B CN101404561 B CN 101404561B CN 2008102270090 A CN2008102270090 A CN 2008102270090A CN 200810227009 A CN200810227009 A CN 200810227009A CN 101404561 B CN101404561 B CN 101404561B
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Abstract
The invention discloses a bit error rate (BER) estimation method. In the method, the number of false check formulas is obtained during LDPC decoding, and the number of the bit errors is obtained by the number of false check formulas to estimate the BER. The method obtains information for estimating the BER during decoding, therefore, the relativity of the information with the BER is high, thus increasing the accuracy of the BER estimation. The invention also provides a device and a receiver for estimating the BER. By using the method, the device and the receiver also realize accurate estimation on the BER.
Description
Technical field
The present invention relates to the error-control technique in the wireless communication system, refer to a kind of bit error rate estimation method, device and receiver especially.
Background technology
Utilize chnnel coding (error correcting code) to realize that error control is one of key technology in the radio digital communication.Traditional channel error correction coding mode mainly contains convolution code, RS block code etc.Low-density checksum (LDPC, Low-Density Parity Check) sign indicating number is an application focus in recent years.
The LDPC sign indicating number is that a class has sparse parity check matrix, has the superperformance of approaching the Shannon limit.Decipher complexity than traditional convolution code and RS block code height though utilize the LDPC sign indicating number, but along with the improvement of decoding algorithm and the development of large scale integrated circuit level, the superperformance of LDPC sign indicating number has obtained paying attention to also having begun to be widely used in fields such as satellite communication, audio-video-frequency broadcast.At present, use the LDPC sign indicating number to comprise the system that meets mobile multimedia industry standard (CMMB), national standard of digital terrestrial broadcasting (DTTB), WiMAX802.16e, DVB-S2 etc. as the communication/broadcast system of channel decoding.
Bit error rate (BER, Bit-Error Rate) is to weigh one of receiver performance and the most important index of working condition in the wireless communication system.
BER method of estimation commonly used is to utilize the transmission pseudo random sequence to measure.Simply be exactly, send known pseudo random sequence to receiver, construct identical pseudo random sequence at the receiver opposite side, after reception data after handling by the pseudo random sequence that constructs with through demodulate/decode are carried out related operation, the bit number that locates errors and decipher, and carry out statistical average, to obtain receiver bit error rate information.This utilization sends the method that pseudo random sequence is tested, and only is suitable for the laboratory debug phase at present, in real work, because the audio/video information that sends can not comprise pseudo random sequence, thereby can't use.
Since the LDPC sign indicating number in different system may with other block code cascade as chnnel coding, for example in CMMB, the LDPC sign indicating number can with the cascade of RS sign indicating number, the LDPC sign indicating number as ISN and the RS sign indicating number as outer sign indicating number.For such system, at present, another kind of BER method of estimation commonly used is, in the decode procedure of RS decoder, detect byte (byte) number of the mistake in each RS packet (packet), if wrong byte number is then finished decoding within the error correcting capability scope of RS sign indicating number, otherwise abandon decoding.The mistake byte rate information of utilizing the RS decoder to provide is estimated BER.There is following shortcoming in this method: at first, RS decoder statistics be the number of mistake byte, but wrong several positions (bit) and uncertain in mistake byte; Secondly, if the mistake byte number surpasses the RS error correcting capability, because the RS decoder can be abandoned decoding, so the RS decoder is to can not get wrong byte number, also just can't determine bit error rate information, and BER also has no idea to obtain; At last, the LDPC sign indicating number may with the cascade of different outer sign indicating number, perhaps use alone, at this moment can only rely on the estimation that ldpc decoder self is finished BER.
In addition, at application number is CN200710196638, denomination of invention for " being used for estimating the device and the correlation technique of the bit error rate of the data that send in communication system " in first to file, provide a kind of after separating constellation mapping, the value and the predetermined threshold value of the soft-decision of the sign confidence level that obtains are compared, utilize comparative result promptly to estimate BER with the degree of closeness of predetermined threshold value.Thisly estimate the method for BER based on soft decision information, judging process was realized before channel decoding.Because the correlation of soft decision information and BER dies down after channel decoding, LDPC sign indicating number particularly, BER sharply descends when signal power to noise power ratio (SNR) increases, and therefore, the accuracy of the BER that the method that being somebody's turn to do in actual applications provide in first to file estimates is not enough.
Summary of the invention
In view of this, main purpose of the present invention is to provide a kind of bit error rate estimation method, can accurately estimate bit error rate.
Another object of the present invention is to provide a kind of bit error rate estimation unit, can accurately estimate bit error rate.
Another purpose of the present invention is to provide a kind of receiver, can accurately estimate bit error rate.
For achieving the above object, technical scheme of the present invention specifically is achieved in that
A kind of bit error rate BER method of estimation, this method may further comprise the steps:
A, in LDPC decoding, obtain the number of invalid verification formula;
B, utilize the number of invalid verification formula to obtain wrong bit number;
C, estimate BER according to the wrong bit number that obtains;
Wherein, the specific implementation of described step B is: obtain described wrong bit number with function y=f (x), wherein, function argument x is invalid verification formula number, the wrong bit number that dependent variable y representative is estimated;
F (x) is a sectional parabola, and its value multiply by different zoom factors for different power powers in different intervals; In the less interval of described x, use less power; In the bigger interval of described x, use bigger power.
The method of obtaining the number of invalid verification formula in the steps A is: when judging the verification formula and be false, design variables is added the number of adding up invalid verification formula.
Described f (x) is:
Dependent variable y represents the error bit number that estimates;
Wherein, x
0Value make
a
0, a
1Be zoom factor.
Described step C specific implementation is: the wrong bit number of Different L DPC piece is done average computation obtain BER.
A kind of bit error rate BER estimation unit, this device comprises: ldpc decoder, wrong bit number acquisition module and BER estimation module, wherein,
Ldpc decoder is used to realize LDPC decoding, also is used for invalid verification formula is added up to obtain the number of invalid verification formula;
Wrong bit number acquisition module is used for the number of basis from the invalid verification formula of ldpc decoder, calculates wrong bit number;
The BER estimation module is used for estimating BER according to the wrong bit number from wrong bit number acquisition module;
Wherein, described wrong bit number acquisition module comprises receiver module, processing module and output module;
Receiver module is used to receive the number from the invalid verification formula of ldpc decoder;
Processing module, the number that is used for the invalid verification formula that receives is independent variable x, obtains described wrong bit number y according to sectional parabola function y=f (x); Described f (x) its value in different intervals multiply by different zoom factors for different power powers; In the less interval of described x, use less power; In the bigger interval of described x, use bigger power;
Described output module is used for the wrong bit number that processing module obtains is exported to described BER estimation module.
Described f (x) is:
Wherein, x
0Value make
a
0, a
1Be zoom factor.
At least comprise calculator in the described ldpc decoder, be used to add up the number of invalid verification formula.
A kind of receiver comprises ldpc decoder, wrong bit number acquisition module and BER estimation module at least, wherein,
Ldpc decoder is used to realize LDPC decoding, also is used for invalid verification formula is added up to obtain the number of invalid verification formula;
Wrong bit number acquisition module is used for the number of basis from the invalid verification formula of ldpc decoder, calculates wrong bit number;
The BER estimation module is used for estimating BER according to the wrong bit number from wrong bit number acquisition module;
Wherein, described wrong bit number acquisition module comprises receiver module, processing module and output module;
Receiver module is used to receive the number from the invalid verification formula of ldpc decoder;
Processing module, the number that is used for the invalid verification formula that receives is independent variable x, obtains described wrong bit number y according to sectional parabola function y=f (x); Described f (x) its value in different intervals multiply by different zoom factors for different power powers; In the less interval of described x, use less power; In the bigger interval of described x, use bigger power;
Described output module is used for the wrong bit number that processing module obtains is exported to described BER estimation module.
Described f (x) is:
Wherein, x
0Value make
a
0, a
1Be zoom factor.
At least comprise calculator in the described ldpc decoder, be used to add up the number of invalid verification formula.
As seen from the above technical solution, this number of in LDPC decoding, obtaining invalid verification formula of the present invention, the wrong bit number that utilizes the number of invalid verification formula to obtain is estimated BER.Because the inventive method is to obtain the information that is used to estimate BER in decode procedure, the correlation height of this information and BER, thus improved accuracy to the BER estimation.The present invention also provides device and the receiver of a kind of BER of estimation, utilizes method of the present invention, and apparatus of the present invention and receiver have also been realized the accurate estimation to BER.
Description of drawings
Fig. 1 is the flow chart that the present invention estimates BER;
Fig. 2 is the flow chart that the present invention estimates the embodiment of BER;
Fig. 3 is the schematic diagram that utilizes BER that the inventive method estimates and simulation curve comparison first embodiment of actual BER;
Fig. 4 is the schematic diagram that utilizes BER that the inventive method estimates and simulation curve comparison second embodiment of actual BER;
Fig. 5 is the composition structural representation of the present invention's device of estimating BER.
Embodiment
For making purpose of the present invention, technical scheme and advantage clearer, below with reference to the accompanying drawing embodiment that develops simultaneously, the present invention is described in more detail.
Fig. 1 is the flow chart that the present invention estimates BER, and as shown in Figure 1, the inventive method may further comprise the steps:
Step 100: the number of in LDCP decoding, obtaining invalid verification formula.
We know, the LDPC sign indicating number is a kind of block code based on sparse check matrix, the decoding of LDPC is the process of an iteration, in each iteration check-node and information bit node computing information is transmitted, and the lastest imformation bit node also extracts its hard decision information with trial and error decoding.If all verification formulas are all set up, and are then successfully decoded, stop iteration and export decoding information; If have at least one verification formula to be false on the contrary, then think and this trial and error decoding failure continue iterative process.Because the code delay of system throughput paginal translation has requirement, iteration can not unrestrictedly be carried out.When iterations reaches preset upper limit and when still having the verification formula to be false, the LDCP decode procedure is thought and is stopped current LDPC block decoding failure iteration and export last hard decision information, provides the decoding failure indication simultaneously.Whether when the LDCP decode procedure finishes in decoding, can only indicate current LDPC block decoding successful, if success, then all bits of current block are correctly transmitted and are received; If the indication decoding failure then exists the verification formula to be false, but can't determine the concrete number of error bit.
Therefore, in this step, when in each iteration, checking whether the verification formula is set up, invalid verification formula is added up to obtain the number of invalid verification formula.Like this, when current LDPC block decoding finishes, when exporting whether successfully decoded the indication, export the number (when successfully decoded, the invalid number of verification formula of output is 0) of invalid verification formula.
Step 101: utilize the number of invalid verification formula to obtain wrong bit number.
Can obtain the error bit number with function y=f (x), wherein function argument x is invalid verification formula number, the error bit number that dependent variable y representative is estimated, f (x) can represent that its value multiply by different zoom factors for different power powers in different intervals with sectional parabola.In the less interval of x, use less power; In the bigger interval of x, then use bigger power.
A kind of implementation method of simple misjudgment bit number can utilize formula (1) to realize:
Wherein, function argument x represents the number of invalid verification formula, and dependent variable y represents the error bit number that estimates.
In the formula (1), its value multiply by different zoom factor a for different power powers in different intervals
0, a
1, x wherein
0Value obtain according to formula (2):
X according to formula (2) acquisition
0, two sections parabolas of f (x) curve are linked to each other; Zoom factor a
0, a
1Can determine that its selection is relevant with the check matrix of LDPC sign indicating number by emulation or experiment.
Such as, to the pattern of CMMB1/2 code check, the LDPC check matrix is one 4608 * 9216 a matrix, supposes to select a
0=88, a
1=240, determine x according to formula (2)
0=1785.For another kind 3/4 bit rate mode of CMMB, the LDPC check matrix is one 6912 * 9216 a matrix, supposes to select a
0=48, a
1=120, determine x according to formula (2)
0=750.
At the LDPC sign indicating number of different system, sectional parabola y=f (x) can be divided into more interval, with more power power curve, such as 4 powers, 2.5 powers wait and connect, thereby can obtain estimation effect more accurately.The selection of concrete parameter can be determined in emulation or laboratory debug phase.
Step 102: estimate BER according to the wrong bit number that obtains.
After in step 101, obtaining wrong bit number, can utilize existing method to estimate BER, obtain BER as the wrong bit number of Different L DPC piece is done average computation.
Fig. 2 is the flow chart that the present invention estimates the embodiment of BER, as shown in Figure 2, specifically describes the method that the present invention estimates BER in conjunction with the LDPC decode procedure, specifically comprises the steps:
Step 200～step 201: initialization information bit node prior probability; Realization information is transmitted and renewal check-node and information bit node.
The realization of this step belongs to prior art, also is those skilled in the art's conventional techniques means, repeats no more here.
Step 202: the number of adding up invalid verification formula.
In existing LDPC decode procedure, can whether set up the verification formula and judge, specific implementation belongs to prior art and how it realizes haveing nothing to do with the inventive method, therefore, repeats no more here.What this step was emphasized is, when judging the verification formula and be false, design variables is added the number of adding up invalid verification formula.
Step 203: judge whether that all verification formulas all set up, if enter step 206; Otherwise continue execution in step 204.
Step 204: judge whether iterations arrives the upper limit, if enter step 206; Otherwise continue execution in step 205.
Step 205: return step 201 after iterations adds one.
Step 206: export decode results, export the number of invalid verification formula simultaneously.
After finishing decode procedure, the decode results whether output decoding is successful, the number of the invalid verification formula that obtains is added up in output simultaneously.
Step 207: utilize the number of invalid verification formula to obtain wrong bit number.
The specific implementation of this step can no longer repeat here referring to step 101.
Step 208: estimate BER according to the wrong bit number that obtains.The specific implementation of this step can be referring to step 102.
Line face simulation example describes method of the present invention.Fig. 3 is the schematic diagram that utilizes BER that the inventive method estimates and simulation curve comparison first embodiment of actual BER, Fig. 3 is at emulation CMMB, 16QAM, under the simulated conditions of 1/2 bit rate mode, BER that estimates and the comparative result of actual BER, wherein curve 31 is actual BER curve, the BER curve of curve 32 for estimating.Fig. 4 is the schematic diagram that utilizes BER that the inventive method estimates and simulation curve comparison second embodiment of actual BER, Fig. 4 is the BER of the estimation that obtains under the multipath channel under awgn channel, the 200Hz Doppler frequency shift and the comparative result of actual BER, wherein curve 41 is actual BER curve, the BER curve of curve 42 for estimating.Clearly, utilize the inventive method to estimate that the BER curve that obtains is very approaching with actual BER curve, show to come the present invention to estimate that the accuracy of the method for BER is very high.
Fig. 5 is the composition structural representation of the present invention's device of estimating BER, as shown in Figure 5, comprises ldpc decoder, wrong bit number acquisition module and BER estimation module, wherein,
Ldpc decoder is used to realize LDPC decoding, also is used for invalid verification formula is added up to obtain the number of invalid verification formula.Wherein statistics can realize that specific implementation belongs to those skilled in the art's conventional techniques means, repeats no more here by the counter that is provided with.
Wrong bit number acquisition module is used for the number of basis from the invalid verification formula of ldpc decoder, calculates wrong bit number.The specific implementation method sees also step 101, repeats no more here.
The BER estimation module is used for estimating BER according to the wrong bit number from wrong bit number acquisition module.The specific implementation method sees also step 102, repeats no more here.
Described wrong bit number acquisition module comprises receiver module, processing module and output module, wherein,
Receiver module is used to receive the number from the invalid verification formula of ldpc decoder;
Processing module, the number that is used for the invalid verification formula that receives is independent variable x, obtains described wrong bit number y according to sectional parabola function y=f (x); Described f (x) its value in different intervals multiply by different zoom factors for different power powers;
Described output module is used for the wrong bit number that processing module obtains is exported to described BER estimation module.
In the less interval of described x, use less power; In the bigger interval of described x, use bigger power.
Described f (x) is:
Wherein, function argument x represents the number of invalid verification formula, and dependent variable y represents the error bit number that estimates;
Wherein, x
0Value make
a
0, a
1Be zoom factor.
The described apparatus of the present invention of Fig. 5 are arranged in the receiver, make receiver realize accurate estimation to BER.
The above is preferred embodiment of the present invention only, is not to be used to limit protection scope of the present invention.Within the spirit and principles in the present invention all, any modification of being done, be equal to and replace and improvement etc., all should be included within protection scope of the present invention.
Claims (10)
1. bit error rate BER method of estimation is characterized in that this method may further comprise the steps:
A. in LDPC decoding, obtain the number of invalid verification formula;
B. utilize the number of invalid verification formula to obtain wrong bit number;
C. estimate BER according to the wrong bit number that obtains;
Wherein, the specific implementation of described step B is: obtain described wrong bit number with function y=f (x), wherein, function argument x is invalid verification formula number, the wrong bit number that dependent variable y representative is estimated;
F (x) is a sectional parabola, and its value multiply by different zoom factors for different power powers in different intervals; In the less interval of described x, use less power; In the bigger interval of described x, use bigger power.
2. BER method of estimation according to claim 1 is characterized in that, the method for obtaining the number of invalid verification formula in the steps A is: when judging the verification formula and be false, design variables is added the number of adding up invalid verification formula.
3. BER method of estimation according to claim 1 is characterized in that, described f (x) is:
Wherein, function argument x represents the number of invalid verification formula, and dependent variable y represents the error bit number that estimates;
Wherein, x
0Value make
a
0, a
1Be zoom factor.
4. BER method of estimation according to claim 1 is characterized in that, described step C specific implementation is: the wrong bit number of Different L DPC piece is done average computation obtain BER.
5. bit error rate BER estimation unit is characterized in that this device comprises: ldpc decoder, wrong bit number acquisition module and BER estimation module, wherein,
Ldpc decoder is used to realize LDPC decoding, also is used for invalid verification formula is added up to obtain the number of invalid verification formula;
Wrong bit number acquisition module is used for the number of basis from the invalid verification formula of ldpc decoder, calculates wrong bit number;
The BER estimation module is used for estimating BER according to the wrong bit number from wrong bit number acquisition module;
Wherein, described wrong bit number acquisition module comprises receiver module, processing module and output module;
Receiver module is used to receive the number from the invalid verification formula of ldpc decoder;
Processing module, the number that is used for the invalid verification formula that receives is independent variable x, obtains described wrong bit number y according to sectional parabola function y=f (x); Described f (x) its value in different intervals multiply by different zoom factors for different power powers; In the less interval of described x, use less power; In the bigger interval of described x, use bigger power;
Described output module is used for the wrong bit number that processing module obtains is exported to described BER estimation module.
6. BER estimation unit according to claim 5 is characterized in that, described f (x) is:
Wherein, function argument x represents the number of invalid verification formula, and dependent variable y represents the error bit number that estimates;
Wherein, x
0Value make
a
0, a
1Be zoom factor.
7. BER estimation unit according to claim 5 is characterized in that, comprises calculator in the described ldpc decoder at least, is used to add up the number of invalid verification formula.
8. a receiver is characterized in that, comprises ldpc decoder, wrong bit number acquisition module and BER estimation module at least, wherein,
Ldpc decoder is used to realize LDPC decoding, also is used for invalid verification formula is added up to obtain the number of invalid verification formula;
Wrong bit number acquisition module is used for the number of basis from the invalid verification formula of ldpc decoder, calculates wrong bit number;
The BER estimation module is used for estimating BER according to the wrong bit number from wrong bit number acquisition module;
Wherein, described wrong bit number acquisition module comprises receiver module, processing module and output module;
Receiver module is used to receive the number from the invalid verification formula of ldpc decoder;
Processing module, the number that is used for the invalid verification formula that receives is independent variable x, obtains described wrong bit number y according to sectional parabola function y=f (x); Described f (x) its value in different intervals multiply by different zoom factors for different power powers; In the less interval of described x, use less power; In the bigger interval of described x, use bigger power;
Described output module is used for the wrong bit number that processing module obtains is exported to described BER estimation module.
9. receiver according to claim 8 is characterized in that, described f (x) is:
Wherein, function argument x represents the number of invalid verification formula, and dependent variable y represents the error bit number that estimates;
Wherein, x
0Value make
a
0, a
1Be zoom factor.
10. receiver according to claim 8 is characterized in that, comprises calculator in the described ldpc decoder at least, is used to add up the number of invalid verification formula.
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| EP2654209A1 (en) * | 2012-04-19 | 2013-10-23 | Rohde & Schwarz GmbH & Co. KG | Method and device for determining of a bit and/or packet error rate |
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| CN101345601A (en) * | 2007-07-13 | 2009-01-14 | 华为技术有限公司 | Interpretation method and decoder |
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| CN101026436A (en) * | 2006-02-22 | 2007-08-29 | 华为技术有限公司 | Low density parity check code decoding method |
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| EP2654209A1 (en) * | 2012-04-19 | 2013-10-23 | Rohde & Schwarz GmbH & Co. KG | Method and device for determining of a bit and/or packet error rate |
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