CN109408260B - Method and device for estimating number of error bits, computer device and storage medium - Google Patents
Method and device for estimating number of error bits, computer device and storage medium Download PDFInfo
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Abstract
The invention relates to a method, a device, computer equipment and a storage medium for estimating the number of error bits, wherein the method comprises the steps of counting the number of test error bits in a set interval and the number of corresponding test unsatisfied syndromes; establishing an initial model according to the statistical result; fitting the initial model to form a target model; when in use, the number of actually unsatisfied syndromes is calculated for the code words input into the decoder; and estimating the actual number of error bits by using the target model and the actual number of unsatisfied syndromes. According to the invention, the number of the test error bits in the set interval and the corresponding test unsatisfied syndrome number are counted to obtain the target models in different intervals, in the actual use process, the actual number of the error bits is estimated according to the target model of the interval in which the actual number of the unsatisfied syndrome falls, the selection of a decoding mode is effectively carried out or the next read retry is directly carried out, the times of unnecessary decoding iteration and retry are reduced, and the integral decoding efficiency can be improved.
Description
Technical Field
The invention relates to a solid state disk, in particular to a method and a device for estimating the number of error bits, a computer device and a storage medium.
Background
The solid state disk has the disadvantage of easily generating data read-write errors, and the probability of data errors is obviously increased after the number of times of erasing is more, so that an error correction algorithm is very needed to ensure, for example, the solid state disk adopts an ECC algorithm to check and change data errors, judge whether a block is bad or not, and accurately estimate the number of error bits, which has important significance for estimating the quality of a channel environment, but the error correction capability of the error correction algorithm is basically fixed, but no suitable algorithm is available at present to accurately estimate the number of error bits of a code word before entering an LDPC decoder, so that the number of retries cannot be reduced, and the decoding efficiency is low,
therefore, it is necessary to design a method for reducing the number of retries and improving the decoding efficiency.
Disclosure of Invention
The invention aims to overcome the defects of the prior art and provides a method and a device for estimating the number of error bits, computer equipment and a storage medium.
In order to achieve the purpose, the invention adopts the following technical scheme: the method for estimating the number of error bits comprises the following steps:
counting the number of test error bits in a set interval and the number of corresponding test unsatisfied syndromes;
establishing an initial model according to the statistical result;
fitting the initial model to form a target model;
when in use, the number of actually unsatisfied syndromes is calculated for the code words input into the decoder;
and estimating the actual number of error bits by using the target model and the actual number of unsatisfied syndromes.
The further technical scheme is as follows: the counting of the number of test error bits in the set interval and the number of test unsatisfied syndromes in the corresponding test includes:
acquiring original data;
encoding original data to obtain a test code word;
setting the interval, step length and maximum statistical times of the number of randomly injected test error bits;
generating the number of corresponding test error bits by using a random number;
adding the number of the test error bits into the test code word;
calculating the number of the syndromes which do not meet the test according to the test code words;
recording the number of unsatisfied syndromes corresponding to the number of the test error bits;
judging whether the recording times reach the maximum statistical times or not;
if not, returning to the step of generating the corresponding test error bit by using the random number;
if yes, resetting the number of the injected test error bits according to the step length;
judging whether the number of the injected test error bits reaches the maximum value of the interval or not;
if yes, entering the step of establishing an initial model according to the number of the test error bits and the number of the corresponding test unsatisfied syndromes;
if not, returning to the step of generating the corresponding test error bit by using the random number.
The further technical scheme is as follows: the establishing of the initial model according to the statistical result comprises the following steps:
averaging the number of test syndromes corresponding to the same number of test error bits to form the number of target syndromes;
and acquiring a relation curve according to the interval of the number of the test error bits and the number of the corresponding target syndromes so as to obtain an initial model.
The further technical scheme is as follows: the fitting the initial model to form the target model includes:
dividing threshold intervals of the number of the target syndromes according to the relation curve;
performing piecewise fitting by adopting a minimum variance according to the division result and the fitting formula, and determining an influence factor and an offset value;
and determining a target model according to the influence factors and the offset values.
The further technical scheme is as follows: the fitting formula includes: sμ(x) A · x + b; wherein a is more than 0, and b is more than 0; a is the scale factor and b is the offset value.
The further technical scheme is as follows: the estimating the actual number of error bits by using the target model and the actual number of unsatisfied syndromes comprises:
acquiring an actual interval in which the number of actually unsatisfied syndromes is located;
and estimating the actual number of error bits according to the number of actually unsatisfied syndromes by using an object model of the actual interval.
The present invention also provides an apparatus for estimating the number of error bits, comprising:
the statistical unit is used for counting the number of the test error bits in the set interval and the number of the corresponding test unsatisfied syndromes;
the initial model establishing unit is used for establishing an initial model according to the statistical result;
the fitting unit is used for fitting the initial model to form a target model;
the actual number calculating unit is used for calculating the number of actually unsatisfied syndromes of the code words input into the decoder when in use;
and the bit number estimation unit is used for estimating the actual number of error bits by using the target model and the actual number of unsatisfied syndromes.
The further technical scheme is as follows: the statistical unit includes:
the data acquisition module is used for acquiring original data;
the encoding module is used for encoding the original data to obtain a test code word;
the setting module is used for setting the interval, the step length and the maximum statistical frequency of the number of the randomly injected test error bits;
the random generating module is used for generating the number of corresponding test error bits by using a random number;
the adding module is used for adding the number of the test error bits into the test code word;
the calculation module is used for calculating the number of the syndromes which do not meet the test according to the test code words;
the recording module is used for recording the number of test syndromes corresponding to the number of test error bits;
the frequency judging module is used for judging whether the recording frequency reaches the maximum statistical frequency or not;
the step length setting module is used for resetting the number of the injected test error bits according to the step length if the step length is up;
and the interval judgment module is used for judging whether the number of the injected test error bits reaches the maximum value of the interval.
The invention also provides computer equipment which comprises a memory and a processor, wherein the memory is stored with a computer program, and the processor realizes the method when executing the computer program.
The invention also provides a storage medium storing a computer program which, when executed by a processor, is operable to carry out the method as described above.
Compared with the prior art, the invention has the beneficial effects that: in the invention, the number of the test error bits in the set interval and the number of the corresponding test unsatisfied syndromes are counted, the initial model is established according to the counting result, and the initial model is fitted to obtain the target models in different intervals.
The invention is further described below with reference to the accompanying drawings and specific embodiments.
Drawings
In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings needed to be used in the description of the embodiments are briefly introduced below, and it is obvious that the drawings in the following description are some embodiments of the present invention, and it is obvious for those skilled in the art to obtain other drawings based on these drawings without creative efforts.
Fig. 1 is a schematic flow chart of a method for estimating the number of error bits according to an embodiment of the present invention;
FIG. 2 is a schematic sub-flow chart of a method for estimating the number of erroneous bits according to an embodiment of the present invention;
FIG. 3 is a schematic sub-flow chart of a method for estimating the number of erroneous bits according to an embodiment of the present invention;
FIG. 4 is a schematic sub-flow chart of a method for estimating the number of erroneous bits according to an embodiment of the present invention;
FIG. 5 is a schematic sub-flow chart of a method for estimating the number of erroneous bits according to an embodiment of the present invention;
FIG. 6 is a diagram illustrating the result of all 4-bit errors falling into 8 rings according to an embodiment of the present invention;
FIG. 7 is a diagram illustrating the result of all 4-bit errors falling into 10 rings according to an embodiment of the present invention;
FIG. 8 is a diagram illustrating the results of all 4-bit errors falling into 12-and 14-rings according to an embodiment of the present invention;
FIG. 9 is a diagram illustrating the result of all 4-bit errors having no edge connection with each other according to an embodiment of the present invention;
fig. 10 is a schematic diagram illustrating a fitting relationship between the number of error bits in a codeword and the number of unsatisfied syndromes according to an embodiment of the present invention;
fig. 11 is a schematic block diagram of an apparatus for estimating the number of error bits according to an embodiment of the present invention;
FIG. 12 is a schematic block diagram of a computer device provided by an embodiment of the present invention.
Detailed Description
The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are some, not all, embodiments of the present invention. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
It will be understood that the terms "comprises" and/or "comprising," when used in this specification and the appended claims, specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof.
It is also to be understood that the terminology used in the description of the invention herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention. As used in the specification of the present invention and the appended claims, the singular forms "a," "an," and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise.
It should be further understood that the term "and/or" as used in this specification and the appended claims refers to and includes any and all possible combinations of one or more of the associated listed items.
Referring to fig. 1, fig. 1 is a schematic flow chart illustrating a method for estimating a number of erroneous bits according to an embodiment of the present invention. The error bit number estimation method can be applied to the solid state disk containing the LDPC ECC algorithm to correct data before the decoder of the solid state disk works, so that the retry times are reduced, and the decoding efficiency is improved.
As shown in fig. 1, the method includes the following steps S110 to S150.
And S110, counting the number of the test error bits in the set interval and the number of the corresponding test unsatisfied syndromes.
In this embodiment, the number of test error bits refers to the number of test error bits generated by the test data employed in the test to model; the number of unsatisfied syndromes is the number of unsatisfied syndromes generated in the process of testing to establish a model.
Because the number of the test error bits and the number of the corresponding test unsatisfied syndromes have a certain linear relationship, the two values are counted, and then modeling is carried out according to the statistical result, so that the number of the error bits of the code word before entering the LDPC decoder is favorably estimated, the selection of a decoding mode can be effectively carried out or the next read retry operation can be directly carried out, thus, unnecessary decoding iteration can be greatly reduced, and the whole decoding efficiency can be improved. The number of error bits is also an important parameter, and taking reading data by the solid state disk memory as an example, under the condition of a large error, the optimal read offset voltage can be adjusted in advance so as to obtain more accurate read data.
In one embodiment, as shown in FIG. 2, the step S110 may include steps S110 a-S110 j.
S110a, acquiring original data;
in this embodiment, the original data refers to test data written in the solid state disk.
S110, 110b, encoding the original data to obtain a test code word.
The test code words refer to code words formed after encoding is performed to correct errors of original data before writing in the solid state disk. In this embodiment, specifically, an LDPC encoder is used to encode original data, and an LDPC (Low Density Parity Check Code) has a linear block Code of a sparse Check matrix, and has a good performance approaching Shannon limit, a Low decoding complexity, a flexible structure, and an excellent error correction performance.
S110c, setting the interval, step size and maximum statistic times of the number of randomly injected test error bits.
When the number of unsatisfied syndromes is obtained, and in different intervals of the number of testing error bits, the relation parameters between the number of testing error bits and the number of unsatisfied syndromes are changed, so that a plurality of intervals of the number of randomly injected testing error bits need to be set, when the number of unsatisfied syndromes is obtained, the number of unsatisfied syndromes needs to be obtained according to all the numbers of testing error bits in the intervals, most preferably, the obtaining needs to be repeated for multiple times so as to improve the accuracy, and therefore, the maximum statistical frequency needs to be set.
When the number of the unsatisfied syndromes is obtained, the number of the testing error bits is increased according to the set step length so as to complete the process of obtaining the number of the unsatisfied syndromes by the testing error bits in the whole interval.
S110d, generating the number of the corresponding test error bits by using the random number.
The number of test error bits generated by the random number method can improve the acquisition accuracy.
And S110e, adding the number of the test error bits into the test code word.
And S110f, calculating the number of syndromes which do not meet the test according to the test code words.
In this embodiment, S ═ H · m is usedTAnd carrying out syndrome calculation, wherein m represents a test code word, and H represents a check matrix adopted by the LDPC error correcting code, and the check matrix is a linear block code matrix and is used for calculating the syndrome.
S110g, recording the number of test unsatisfied syndrome corresponding to the number of test error bits;
and recording the number of the test unsatisfied syndromes so as to facilitate subsequent processing.
S110h, judging whether the recording frequency reaches the maximum statistical frequency.
The number of the error bits of the same test is repeatedly obtained and tested to obtain the number of unsatisfied syndromes, so that the accuracy is improved, and the errors are reduced
If not, returning to the step S110 d;
if yes, S110i resets the number of injected test error bits according to the step size.
After the maximum number of times of statistics is performed on the same number of test error bits to obtain the number of unsatisfied syndromes, the above-mentioned procedure needs to be performed for the next number of test error bits, so the number of test error bits needs to be increased according to the set step length, and the same procedure is used for statistics until the number of currently injected test error bits reaches the maximum value of the interval.
S110j, judging whether the number of the injected test error bits reaches the maximum value of the interval;
and taking the recorded content as a statistical result to obtain the number of the unsatisfied syndromes tested corresponding to the number of the test error bits in the set interval.
If yes, go to step S120;
if not, the process returns to step S110 d.
And S120, establishing an initial model according to the statistical result.
In this embodiment, the statistical result refers to the number of test error bits and the number of unsatisfied syndrome tests within the statistical setting interval; the initial model refers to a graph formed by a plurality of testing error bit numbers and the number of the corresponding testing unsatisfied syndromes.
In one embodiment, as shown in fig. 3, the step S120 may include steps S121 to S122.
S121, averaging the number of the test syndromes corresponding to the same number of the test error bits to form the number of the target syndromes;
and obtaining a test syndrome number corresponding to the test error bit number from the plurality of test syndrome numbers in an averaging mode, so that the accuracy of the initial model can be improved.
And S122, obtaining a relation curve according to the interval of the number of the test error bits and the number of the corresponding target syndromes so as to obtain an initial model.
In this embodiment, a relation curve between the interval of the number of test error bits and the corresponding number of target syndromes may be drawn by using tools such as matlab.
And S130, fitting the initial model to form a target model.
In the present embodiment, the target model refers to a curve formed by curve fitting with respect to the initial model.
In one embodiment, as shown in fig. 4, the step S130 may include steps S131 to S133.
And S131, dividing threshold intervals of the number of the target syndromes according to the relation curve.
Because the relationship between the number of error bits and the number of target syndromes may be different in different intervals, the number of target syndromes needs to be divided into threshold intervals to obtain the relationship between the number of error bits and the number of target syndromes in each interval, thereby improving the accuracy of estimating the number of error bits.
And S132, performing piecewise fitting by adopting a minimum variance according to the division result and the fitting formula, and determining an influence factor and an offset value.
In this embodiment, the fitting formula includes: sμ(x) A · x + b, wherein a > 0, b > 0; a is the scale factor and b is the offset value.
And setting different segmentation threshold values for unsatisfied syndromes according to the curve, fitting points in each interval by using a minimum variance algorithm, and determining the influence factor and the deviation value of each segmentation interval.
And S133, determining a target model according to the influence factors and the offset values.
When determining the impact factors and offset values for each segment interval, s may be usedμ(x) The formula of a · x + b determines the relationship between the number of error bits and the unsatisfied syndrome, and thus determines the target model.
And S140, calculating the number of actually unsatisfied syndromes of the codes input into the decoder when in use.
Firstly, the number of actually unsatisfied syndromes is calculated for the code word input into the decoder, and S is specifically adopted to be H.mTAnd (4) calculating.
And S150, estimating the actual number of error bits by using the target model and the actual number of unsatisfied syndromes.
In one embodiment, the step S150 may include steps S151 to S152.
S151, acquiring an actual interval where the actual number of the unsatisfied syndromes is located;
and S152, estimating the actual number of error bits according to the number of actually unsatisfied syndromes by using the target model of the actual interval.
Determining the number of actually unsatisfied syndromes to determine which interval the actually unsatisfied syndromes fall into, and determining a target model s corresponding to the falling interval according to the number of actually unsatisfied syndromesμ(x) Inputting the number s which does not actually satisfy the syndromeμ(x) The actual number of the error bits is estimated, the bandwidth waste caused by the fact that the error bits cannot be corrected when entering a decoder under the condition of a large number of error bits can be effectively avoided, the decoding efficiency is improved, and the process is also suitable for error estimation of the code word error of the irregular QC-LDPC.
Taking an example: taking a regular QC-LDPC check array constructed by a PEG algorithm as an example, such check arrays have the same column weight, and since the LDPC code is a relatively sparse grouped linear code, it can be generally represented by a bipartite graph, for example, G ═ V ═ L ═ R, E), L represents a set of all variable nodes, R represents a set of all check nodes, and E represents a connection line between a variable node and a check node. Assuming that the column weight of the LDPC check array is 4, an example is taken to analyze one error mode in the check array, that is, 8 loops, as shown in fig. 6, a black square represents a check node that is not satisfied by check calculation of the check array, a white square represents a satisfied check node, a black circle represents a variable node where an error occurs, each variable node is connected to 4 check nodes, and the middle 4 check nodes are connected to even number of variable nodes where an error occurs, so that a syndrome is satisfied, and the number of unsatisfied syndromes is 8, which is a special case.
Of course, there is more than 8 rings of one error pattern in the LDPC check array, and as shown in fig. 7, assuming that all 4-bit errors fall into 10 rings of error patterns, there are two more syndromes not satisfied. Also shown in FIG. 8, the error patterns that fall into 12-and 14-rings, respectively, add two and four unsatisfied syndromes, respectively. In the case of an LDPC codeword with only 4 bits in error, there is no borderline connection for a high probability of random error of 4 erroneous bits, and the result is shown in fig. 9. Therefore, the situation that random errors occur to the LDPC code words can be obtained, the random errors fall into different error modes, the calculated syndromes are different, but in a certain interval range, the number of all rings is theoretically counted, the probability of falling into the rings is calculated, the number of error bits can be estimated according to the syndromes, and the relation between the syndromes and the number of the error bits is simulated through a statistical method. Since it is determined from one time of randomly injecting n error positions that the relation between the number of unsatisfied syndromes and the number of error bits does not have generality, and is different under different error modes, it is necessary to analyze statistically, and according to the characteristics of the LDPC check matrix, if 1-bit error is added in terms of statistical analysis, that is, one step is added, unsatisfied check nodes should also be added. Assume that the number of randomly injected error bits is represented by x and the number of unsatisfied syndromes can be represented by sμ(x) Represents, can be for sμ(x) Fitting is carried out, namely: sμ(x) A · x + b; wherein a is more than 0, and b is more than 0; a is the scale factor and b is the offset value.
When the number of error bits is small, a is not more than l because of the sparsity of the codeword itself as shown in fig. 10, and when a is l, b is 0; as the number of error bits increases, more bits of errors may occur in the same check node, and therefore the influence factor a becomes smaller. And setting a threshold value for the number of syndromes which are not satisfied in different intervals, so as to perform piecewise fitting and obtain higher accuracy. Approximate function fitting thereofAs shown in fig. 11, for a specific LDPC check matrix, the influence factor a and the offset value b of each segment in the curve can be obtained through statistics. The number of unsatisfied syndromes respectively matched with three threshold values T through actual calculationu1，Tu2，Tu3And comparing, determining which interval falls into, thereby determining a and b, and estimating the error bit number of the code word: x ═ sμ(x)-b)/a。
When the QC-LDPC check array with fixed column weight is constructed by PEG, the estimation method is also suitable for the irregular LDPC check array, if the distribution of column weight is approximately uniform, the corresponding influence factor and offset value can be obtained by a statistical mode, and the result can not generate too large fluctuation. If the column weight distribution is completely irregular, the fitting precision can be improved by dividing a plurality of intervals, so that the more accurate error bit number can be estimated. So as to estimate the number of error bits of the code word through the interval in which the number of unsatisfied syndromes falls.
The method comprises the steps of estimating the number of error bits of a code word before the code word enters a decoder based on the LDPC linear block code, estimating the number of error bits of the code word by setting different thresholds for the number of unsatisfied syndromes according to the characteristics of the LDPC check matrix by utilizing the number of unsatisfied syndromes according to the syndrome information calculated by the code word and the check matrix, having important significance for estimating the quality of a channel environment and providing an important reference factor for the LDPC decoder, thereby selecting a more appropriate decoding mode and improving the decoding efficiency. By carrying out corresponding modeling analysis on the characteristics of the LDPC check array, the influence of the number of error bits on the syndrome under different error conditions is determined to determine the influence factors of different error intervals, so that the error number of the code word is estimated, the condition that under different error modes, the number of unsatisfied syndromes and the actual number of error bits have a reasonable proportional relation can be obtained, different thresholds are set for the number of unsatisfied syndromes to obtain the influence factors and the offset values of different intervals, the number of error bits of the code word can be estimated, and the like, different other check arrays can also estimate the error bit number of the code word.
The error correction capability of the error correction algorithm is basically fixed, so that the number of approximately erroneous bits can be estimated by a certain method before decoding and error correction, and a proper mode is selected for decoding, so that the retry times can be greatly reduced, and the decoding efficiency is improved.
According to the error bit number estimation method, the number of the test error bits in the set interval and the number of the corresponding test unsatisfied syndromes are counted, the initial model is established according to the counting result, the initial model is fitted to obtain the target models in different intervals, in the actual use process, the actual number of the unsatisfied syndromes of the code words before decoding is calculated, the actual number of the error bits is estimated according to the target model of the interval in which the actual number of the unsatisfied syndromes of the codes fall, the selection of the decoding mode is effectively carried out or the next read retry is directly carried out, the number of unnecessary decoding iteration and retry is reduced, and the integral decoding efficiency can be improved.
Fig. 11 is a schematic block diagram of an apparatus 300 for estimating the number of error bits according to an embodiment of the present invention. As shown in fig. 11, the present invention also provides an apparatus 300 for estimating the number of error bits corresponding to the above method for estimating the number of error bits. The error bit number estimation apparatus 300 includes a unit for performing the above error bit number estimation method, and may be configured in a solid state disk including an ECC algorithm of LDPC.
Specifically, referring to fig. 11, the apparatus 300 for estimating the number of error bits includes:
a counting unit 301, configured to count the number of test error bits in a set interval and the number of unsatisfied syndrome checks corresponding to the test error bits;
an initial model establishing unit 302, configured to establish an initial model according to the statistical result;
a fitting unit 303, configured to fit the initial model to form a target model;
an actual number calculation unit 304, configured to calculate, for a codeword input to the decoder, an actual number of unsatisfied syndromes;
a bit number estimation unit 305 for estimating an actual number of erroneous bits using the target model and the actual number of unsatisfied syndromes.
In one embodiment, the statistical unit 301 comprises:
the data acquisition module is used for acquiring original data;
the encoding module is used for encoding the original data to obtain a test code word;
the setting module is used for setting the interval, the step length and the maximum statistical frequency of the number of the randomly injected test error bits;
the random generating module is used for generating the number of corresponding test error bits by using a random number;
the adding module is used for adding the number of the test error bits into the test code word;
the calculation module is used for calculating the number of the syndromes which do not meet the test according to the test code words;
the recording module is used for recording the number of test syndromes corresponding to the number of test error bits;
the frequency judging module is used for judging whether the recording frequency reaches the maximum statistical frequency or not;
the step length setting module is used for resetting the number of the injected test error bits according to the step length if the step length is up;
and the interval judgment module is used for judging whether the number of the injected test error bits reaches the maximum value of the interval.
In an embodiment, the initial model establishing unit 302 includes:
the average value obtaining module is used for averaging the test syndrome numbers corresponding to the same test error bit number to form a target syndrome number;
and the relation curve module is used for acquiring a relation curve according to the interval of the number of the test error bits and the number of the corresponding target syndromes so as to obtain an initial model.
In one embodiment, the fitting unit 303 includes:
the dividing module is used for dividing the threshold interval of the number of the target syndromes according to the relation curve;
the parameter determining module is used for performing piecewise fitting by adopting a minimum variance according to the dividing result and the fitting formula to determine an influence factor and an offset value;
and the target model determining module is used for determining a target model according to the influence factor and the deviation value.
In one embodiment, the bit number estimation unit 305 includes:
the actual interval obtaining module is used for obtaining an actual interval where the actual number of the unsatisfied syndromes does not meet the requirements;
and the number estimation module is used for estimating the actual number of the error bits according to the actual number of unsatisfied syndromes by using the target model of the actual interval.
It should be noted that, as can be clearly understood by those skilled in the art, the specific implementation process of the above-mentioned error bit number estimation apparatus 300 and each unit may refer to the corresponding description in the foregoing method embodiment, and for convenience and brevity of description, no further description is provided herein.
The above-mentioned error bit number estimation apparatus 300 may be implemented in the form of a computer program, which can be run on a computer device as shown in fig. 12.
Referring to fig. 12, fig. 12 is a schematic block diagram of a computer device according to an embodiment of the present application. The computer device 500 is a server within a solid state disk with an ECC algorithm including LDPC.
Referring to fig. 12, the computer device 500 includes a processor 502, memory, and a network interface 505 connected by a system bus 501, where the memory may include a non-volatile storage medium 503 and an internal memory 504.
The non-volatile storage medium 503 may store an operating system 5031 and a computer program 5032. The computer program 5032 comprises program instructions that, when executed, cause the processor 502 to perform a method of error bit number estimation.
The processor 502 is used to provide computing and control capabilities to support the operation of the overall computer device 500.
The internal memory 504 provides an environment for the operation of the computer program 5032 in the non-volatile storage medium 503, and when the computer program 5032 is executed by the processor 502, the processor 502 can execute a method for estimating the number of error bits.
The network interface 505 is used for network communication with other devices. Those skilled in the art will appreciate that the configuration shown in fig. 12 is a block diagram of only a portion of the configuration associated with the present application and does not constitute a limitation of the computer device 500 to which the present application may be applied, and that a particular computer device 500 may include more or less components than those shown, or may combine certain components, or have a different arrangement of components.
Wherein the processor 502 is configured to run the computer program 5032 stored in the memory to implement the following steps:
counting the number of test error bits in a set interval and the number of corresponding test unsatisfied syndromes;
establishing an initial model according to the statistical result;
fitting the initial model to form a target model;
when in use, the number of actually unsatisfied syndromes is calculated for the code words input into the decoder;
and estimating the actual number of error bits by using the target model and the actual number of unsatisfied syndromes.
In an embodiment, when the step of counting the number of bits with test errors in the set interval and the step of testing the number of unsatisfied syndromes with the corresponding test are implemented by the processor 502, the following steps are specifically implemented:
acquiring original data;
encoding original data to obtain a test code word;
setting the interval, step length and maximum statistical times of the number of randomly injected test error bits;
generating the number of corresponding test error bits by using a random number;
adding the number of the test error bits into the test code word;
calculating the number of the syndromes which do not meet the test according to the test code words;
recording the number of unsatisfied syndromes corresponding to the number of the test error bits;
judging whether the recording times reach the maximum statistical times or not;
if not, returning to the step of generating the corresponding test error bit by using the random number;
if yes, resetting the number of the injected test error bits according to the step length;
judging whether the number of the injected test error bits reaches the maximum value of the interval or not;
if yes, entering the step of establishing an initial model according to the number of the test error bits and the number of the corresponding test unsatisfied syndromes;
if not, returning to the step of generating the corresponding test error bit by using the random number.
In an embodiment, when the step of establishing the initial model according to the statistical result is implemented by the processor 502, the following steps are specifically implemented:
averaging the number of test syndromes corresponding to the same number of test error bits to form the number of target syndromes;
and acquiring a relation curve according to the interval of the number of the test error bits and the number of the corresponding target syndromes so as to obtain an initial model.
In an embodiment, when the processor 502 implements the step of fitting the initial model to form the target model, the following steps are specifically implemented:
dividing threshold intervals of the number of the target syndromes according to the relation curve;
performing piecewise fitting by adopting a minimum variance according to the division result and the fitting formula, and determining an influence factor and an offset value;
and determining a target model according to the influence factors and the offset values.
Wherein the fitting formula comprises: sμ(x) A · x + b; wherein a is more than 0, and b is more than 0; a is the scale factor and b is the offset value.
In an embodiment, when the step of estimating the actual number of error bits by using the target model and the actual number of unsatisfied syndromes is implemented, the processor 502 specifically implements the following steps:
acquiring an actual interval in which the number of actually unsatisfied syndromes is located;
and estimating the actual number of error bits according to the number of actually unsatisfied syndromes by using an object model of the actual interval.
It should be understood that in the embodiment of the present Application, the Processor 502 may be a Central Processing Unit (CPU), and the Processor 502 may also be other general-purpose processors, Digital Signal Processors (DSPs), Application Specific Integrated Circuits (ASICs), Field Programmable Gate Arrays (FPGAs) or other Programmable logic devices, discrete Gate or transistor logic devices, discrete hardware components, and the like. Wherein a general purpose processor may be a microprocessor or the processor may be any conventional processor or the like.
It will be understood by those skilled in the art that all or part of the flow of the method implementing the above embodiments may be implemented by a computer program instructing associated hardware. The computer program includes program instructions, and the computer program may be stored in a storage medium, which is a computer-readable storage medium. The program instructions are executed by at least one processor in the computer system to implement the flow steps of the embodiments of the method described above.
Accordingly, the present invention also provides a storage medium. The storage medium may be a computer-readable storage medium. The storage medium stores a computer program, wherein the computer program, when executed by a processor, causes the processor to perform the steps of:
counting the number of test error bits in a set interval and the number of corresponding test unsatisfied syndromes;
establishing an initial model according to the statistical result;
fitting the initial model to form a target model;
when in use, the number of actually unsatisfied syndromes is calculated for the code words input into the decoder;
and estimating the actual number of error bits by using the target model and the actual number of unsatisfied syndromes.
In an embodiment, when the processor executes the computer program to implement the step of counting the number of test error bits in the set interval and the corresponding test unsatisfied with the number of syndromes, the following steps are specifically implemented:
acquiring original data;
encoding original data to obtain a test code word;
setting the interval, step length and maximum statistical times of the number of randomly injected test error bits;
generating the number of corresponding test error bits by using a random number;
adding the number of the test error bits into the test code word;
calculating the number of the syndromes which do not meet the test according to the test code words;
recording the number of unsatisfied syndromes corresponding to the number of the test error bits;
judging whether the recording times reach the maximum statistical times or not;
if not, returning to the step of generating the corresponding test error bit by using the random number;
if yes, resetting the number of the injected test error bits according to the step length;
judging whether the number of the injected test error bits reaches the maximum value of the interval or not;
if yes, entering the step of establishing an initial model according to the number of the test error bits and the number of the corresponding test unsatisfied syndromes;
if not, returning to the step of generating the corresponding test error bit by using the random number.
In an embodiment, when the processor executes the computer program to implement the step of building an initial model according to the statistical result, the following steps are specifically implemented:
averaging the number of test syndromes corresponding to the same number of test error bits to form the number of target syndromes;
and acquiring a relation curve according to the interval of the number of the test error bits and the number of the corresponding target syndromes so as to obtain an initial model.
In an embodiment, when the processor executes the computer program to implement the step of fitting the initial model to form the target model, the following steps are specifically implemented:
dividing threshold intervals of the number of the target syndromes according to the relation curve;
performing piecewise fitting by adopting a minimum variance according to the division result and the fitting formula, and determining an influence factor and an offset value;
determining a target model from the impact factors and the offset values
Wherein the fitting formula comprises: sμ(x) A · x + b; wherein a is more than 0, and b is more than 0; a is a scale factor and b is an offset value
In an embodiment, when the step of estimating the actual number of error bits by using the target model and the actual unsatisfied syndrome number is implemented by the processor executing the computer program, the following steps are specifically implemented:
acquiring an actual interval in which the number of actually unsatisfied syndromes is located;
and estimating the actual number of error bits according to the number of actually unsatisfied syndromes by using an object model of the actual interval.
The storage medium may be a usb disk, a removable hard disk, a Read-Only Memory (ROM), a magnetic disk, or an optical disk, which can store various computer readable storage media.
Those of ordinary skill in the art will appreciate that the elements and algorithm steps of the examples described in connection with the embodiments disclosed herein may be embodied in electronic hardware, computer software, or combinations of both, and that the components and steps of the examples have been described in a functional general in the foregoing description for the purpose of illustrating clearly the interchangeability of hardware and software. Whether such functionality is implemented as hardware or software depends upon the particular application and design constraints imposed on the implementation. Skilled artisans may implement the described functionality in varying ways for each particular application, but such implementation decisions should not be interpreted as causing a departure from the scope of the present invention.
In the embodiments provided in the present invention, it should be understood that the disclosed apparatus and method may be implemented in other ways. For example, the above-described apparatus embodiments are merely illustrative. For example, the division of each unit is only one logic function division, and there may be another division manner in actual implementation. For example, various elements or components may be combined or may be integrated into another system, or some features may be omitted, or not implemented.
The steps in the method of the embodiment of the invention can be sequentially adjusted, combined and deleted according to actual needs. The units in the device of the embodiment of the invention can be merged, divided and deleted according to actual needs. In addition, functional units in the embodiments of the present invention may be integrated into one processing unit, or each unit may exist alone physically, or two or more units are integrated into one unit.
The integrated unit, if implemented in the form of a software functional unit and sold or used as a stand-alone product, may be stored in a storage medium. Based on such understanding, the technical solution of the present invention essentially or partially contributes to the prior art, or all or part of the technical solution can be embodied in the form of a software product, which is stored in a storage medium and includes instructions for causing a computer device (which may be a personal computer, a terminal, or a network device) to execute all or part of the steps of the method according to the embodiments of the present invention.
While the invention has been described with reference to specific embodiments, the invention is not limited thereto, and various equivalent modifications and substitutions can be easily made by those skilled in the art within the technical scope of the invention. Therefore, the protection scope of the present invention shall be subject to the protection scope of the claims.
Claims (8)
1. The method for estimating the number of error bits, comprising:
counting the number of test error bits in a set interval and the number of corresponding test unsatisfied syndromes;
establishing an initial model according to the statistical result;
fitting the initial model to form a target model;
when in use, the number of actually unsatisfied syndromes is calculated for the code words input into the decoder;
estimating the number of actual error bits by using the target model and the number of actually unsatisfied syndromes;
the counting of the number of test error bits in the set interval and the number of test unsatisfied syndromes in the corresponding test includes:
acquiring original data;
encoding original data to obtain a test code word;
setting the interval, step length and maximum statistical times of the number of randomly injected test error bits;
generating the number of corresponding test error bits by using a random number;
adding the number of the test error bits into the test code word;
calculating the number of the syndromes which do not meet the test according to the test code words;
recording the number of unsatisfied syndromes corresponding to the number of the test error bits;
judging whether the recording times reach the maximum statistical times or not;
if not, returning to the step of generating the corresponding test error bit by using the random number;
if yes, resetting the number of the injected test error bits according to the step length;
judging whether the number of the injected test error bits reaches the maximum value of the interval or not;
if yes, entering the step of establishing an initial model according to the number of the test error bits and the number of the corresponding test unsatisfied syndromes;
if not, returning to the step of generating the corresponding test error bit by using the random number.
2. The method of claim 1, wherein the establishing an initial model according to the statistical result comprises:
averaging the number of test syndromes corresponding to the same number of test error bits to form the number of target syndromes;
and acquiring a relation curve according to the interval of the number of the test error bits and the number of the corresponding target syndromes so as to obtain an initial model.
3. The method of claim 2, wherein the fitting the initial model to form the target model comprises:
dividing threshold intervals of the number of the target syndromes according to the relation curve;
performing piecewise fitting by adopting a minimum variance according to the division result and the fitting formula, and determining an influence factor and an offset value;
and determining a target model according to the influence factors and the offset values.
4. The method of claim 3, wherein the fitting formula comprises:
wherein, the water-soluble polymer is a polymer,
，
；
is a proportional influence factor, and is,
is an offset value.
5. The method of claim 3, wherein estimating the actual number of erroneous bits using the target model and the actual unsatisfied syndrome number comprises:
acquiring an actual interval in which the number of actually unsatisfied syndromes is located;
and estimating the actual number of error bits according to the number of actually unsatisfied syndromes by using an object model of the actual interval.
6. An apparatus for estimating the number of error bits, comprising:
the statistical unit is used for counting the number of the test error bits in the set interval and the number of the corresponding test unsatisfied syndromes;
the initial model establishing unit is used for establishing an initial model according to the statistical result;
the fitting unit is used for fitting the initial model to form a target model;
the actual number calculating unit is used for calculating the number of actually unsatisfied syndromes of the code words input into the decoder when in use;
the bit number estimation unit is used for estimating the actual error bit number by utilizing the target model and the actual number of unsatisfied syndromes;
the statistical unit includes:
the data acquisition module is used for acquiring original data;
the encoding module is used for encoding the original data to obtain a test code word;
the setting module is used for setting the interval, the step length and the maximum statistical frequency of the number of the randomly injected test error bits;
the random generating module is used for generating the number of corresponding test error bits by using a random number;
the adding module is used for adding the number of the test error bits into the test code word;
the calculation module is used for calculating the number of the syndromes which do not meet the test according to the test code words;
the recording module is used for recording the number of test syndromes corresponding to the number of test error bits;
the frequency judging module is used for judging whether the recording frequency reaches the maximum statistical frequency or not; if not, returning to the step of generating the corresponding test error bit by using the random number;
the step length setting module is used for resetting the number of the injected test error bits according to the step length if the step length is up;
the interval judging module is used for judging whether the number of the injected test error bits reaches the maximum value of the interval or not; if yes, entering the step of establishing an initial model according to the number of the test error bits and the number of the corresponding test unsatisfied syndromes; if not, returning to the step of generating the corresponding test error bit by using the random number.
7. A computer arrangement, characterized in that the computer arrangement comprises a memory having stored thereon a computer program and a processor implementing the method according to any of claims 1-5 when executing the computer program.
8. A storage medium, characterized in that the storage medium stores a computer program which, when executed by a processor, implements the method according to any one of claims 1 to 5.
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| CN113343630B (en) * | 2021-06-25 | 2023-09-05 | 海光信息技术股份有限公司 | Modeling method and modeling device, electronic equipment and storage medium |
| CN114356218B (en) * | 2021-12-07 | 2024-01-16 | 广州致存科技有限责任公司 | Data error correction method, device and medium of Flash memory |
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