CN101395795B - A MEMS resonator, a method of manufacturing thereof, and a MEMS oscillator - Google Patents

Abstract

The invention relates to a MEMS resonator comprising a first electrode, a movable element (48) comprising a second electrode, the movable element (48) at least being movable towards the first electrode, the first electrode and the movable element (48) being separated by a gap (46, 47) having sidewalls. According to the invention, the MEMS resonator is characterized in that the gap (46, 47) has been provided with a dielectric layer (60) on at least one of the sidewalls.

Description

MEMS resonator and manufacture method thereof, and MEMS oscillator

Technical field

The present invention relates to a kind of MEMS resonator, the displaceable element that it comprises first electrode and comprises second electrode, displaceable element is movably towards first electrode at least, the interval that first electrode and displaceable element are had sidewall separates.

The invention still further relates to a kind of method of making this MEMS resonator.

The invention still further relates to a kind of MEMS oscillator of the MEMS of comprising resonator, and relate to a kind of integrated circuit that comprises this MEMS oscillator.

Background technology

From the known a kind of MEMS resonator of WO 2004/027796A2.The document discloses a kind of plane two fixed ends beam resonator.This two fixed ends beam resonator comprises monocrystalline silicon (SCS) beam, and it is disposed in two and props up between the zone admittedly.The SCS beam has the width and the height of definition, and is used as the resonant element of two fixed ends beam resonator 200.Drive electrode and sensing answer electrode toward each other, separate with the SCS beam at interval by sub-micron.Electrode preferably includes polysilicon.Therefore, the two fixed ends beam resonator is made up of silicon basically or fully.

The shortcoming of known MEMS resonator is to be difficult to make.

Summary of the invention

The interchangeable MEMS resonator that the purpose of this invention is to provide a kind of MEMS resonator kind that proposes in first section, this resonator relatively are easy to make.Independent claims limit the present invention.Appended claims define advantageous embodiment.

According to the present invention, by at least one sidewall, providing dielectric layer to achieve this end to the interval.Adopt the electric capacity conversion that silicon MEMS resonator is encouraged and sensing.The efficient of this conversion depends on the distance (interval width) between resonator and its excitation and/or the sensing electrode to a great extent.Usually, in the great majority such as oscillator and accelerometer are used, require this distance less than 1 μ m.Adopt traditional photoetching technique can not make these narrow intervals.For the device among the WO 2004/027796A2, need a lot of treatment steps, comprising adopting sacrifice layer and additional etch step.Yet the present invention can reduce interval width in simple mode, promptly by only adopting an additional treatment step.

The present invention is also based on following understanding: the dielectric constant of the dielectric substance that provides on sidewall is greater than 1, and should the fact can be utilized.Because dielectric constant is greater than 1, thus the significant interval width less than distance between electrodes, this has become inventor's understanding.In the accompanying drawing of this specification is described, further explanation done in term " significant interval width ".

In the advantageous embodiment of MEMS resonator according to the present invention, at least two sidewalls, provide dielectric layer.The advantage of this measure is further to reduce physical gap width and significant interval width.

In another embodiment of MEMS resonator according to the present invention, the MEMS resonator also comprises another electrode, moving meter is movably towards another electrode, another electrode and displaceable element had an other sidewall another separate at interval, described another be provided another dielectric layer at interval at least one other sidewall.Supplemantary electrode makes the designer for example first electrode (for example can be embodied as exciting electrode, be used for electric capacity excitation displaceable element), and second electrode is embodied as sensing electrode (for example, being used to measure the electric capacity modulation that produces owing to another varying width at interval).

Advantageously, at least two other sidewalls, provide another dielectric layer.

Preferably, dielectric or in addition dielectric comprise at least a in the following material: silicon dioxide, silicon nitride or the ferroelectric material such as PZT or PLZT.Dielectric dielectric constant is big more, and it is many more that the significant interval width is reduced.

The invention still further relates to a kind of method of the MEMS of manufacturing resonator.The method according to this invention may further comprise the steps:

Semiconductor body is provided, and it comprises substrate layer, at sacrifice layer that is provided on the substrate layer and the top layer that provided on sacrifice layer;

Form top layer pattern, be used for forming at interval, this interval exposes sacrifice layer partly, and this is further used for limiting displaceable element at interval;

Optionally remove sacrifice layer, be used for displaceable element is partly discharged from substrate layer; And

On at least one sidewall at the interval relevant, provide dielectric layer with displaceable element top layer on every side.

WO 2004/027796A2 discloses a kind of method at interval that forms, and this interval width is less than the width that can obtain with photoetching technique.In the method, the additional sacrificial oxide layer of deposition is immediately partly removed this sacrifice layer in the interval of next-door neighbour's resonator, so that keep nano level oxide layer on resonator.Fill residue at interval with polysilicon then, to form electrode.The release resonator structure is used as last step of this method and finishes, and wherein optionally etches away thin sacrificial oxide layer and oxide layer.Therefore, the document discloses a kind of quite complicated formation method at interval, and this interval width is less than the width that can obtain with photoetching technique.

The method according to this invention is different from said method significantly.In the method according to the invention, before providing dielectric layer at least one sidewall, discharge displaceable element.And, do not remove this dielectric, this described understanding early with the inventor is consistent.Therefore, need less processing step in the method according to the invention.

US 2005/0124135 A1 discloses three kinds of replaceable methods that form width less than the interval of the width that can obtain with photoetching technique.In by the disclosed first method of US 2005/0124135 A1, heat is grown or is deposited an oxide layer on silicon substrate, and forms this oxide pattern to form groove at this.Then, deposition one thin polysilicon layer on this oxide layer.Recharge groove with oxide then, and it is carried out back-etching, so that be exposed to the sacrificial oxide layer on the trenched side-wall.At last, carry out etching to sacrificing sidewall polycrystalline silicon, thereby produce nanometer channel.

In by the disclosed second method of US 2005/0124135 A1, on substrate, form nitration case.The mask that deposit spathic silicon layer, and employing then has opening forms this polysilicon layer pattern, and wherein the size with opening is reduced to submicron-scale.Adopt this mask to form submicron-scale then by etching.

In by disclosed the third method of US 2005/0124135 A1, SOI is provided wafer, this wafer comprises first silicon layer, oxide layer and second silicon layer.Then, the nitration case of deposition of thin on the SOI wafer, it prevents the oxidation of second silicon layer in the processing step of back.The deposit film polysilicon layer, and form this membrane polysilicon layer pattern to produce opening.The polysilicon layer that forms pattern is carried out oxidation, to form oxide mask.Opening has been reduced size in oxidizing process.Carry out the anisotropic dry etch of thin nitration case then, carry out the ion etching step subsequently, so that second polysilicon layer is etched into oxide layer downwards.At last, remove oxide layer partly, so that partly discharge the part of the micro-structural that produces.

The common ground of all three kinds of methods is all to have adopted the mask that has reduced size to come etching to have the groove of submicron-scale.This is different from the method according to this invention in itself, and the method according to this invention does not comprise that etching has the step of the groove of sub-micron width.On the contrary, the groove that be formed can have by the obtainable stock size of conventional lithographic techniques.In the method according to the invention, after forming groove, reduce the size of groove, this has simplified manufacturing process significantly.

Note that the sequence of steps that can change in the method according to this invention.For example, before optionally removing sacrifice layer, second material can be offered displaceable element.For this reason, can adopt conventional procedures as etching, deposition and CMP.

The advantageous embodiment of the method according to this invention is characterised in that provides the top layer that comprises silicon on sacrifice layer in the step of semiconductor body is provided.Employing silicon has the following advantages: its can with most of technology compatibilities, therefore can carry out simply integrated with integrated circuit.

Improved being characterised in that of another of embodiment provides the step of dielectric layer to comprise oxidation step before, and the silicon at least of at least one sidewall at the interval relevant with top layer is converted into silica thus.The oxidation of silicon be a kind of fine control and also in most of MEMS manufacturing environments also obtainable technology.Silicon dioxide is that to have dielectric constant be 3.9 dielectric substance, and this is favourable for reducing the significant interval width significantly.

Alternative embodiment is characterised in that provides the step of dielectric layer to comprise dielectric layer deposition, provides this dielectric layer at least one sidewall at the interval relevant with top layer.Deposition technique also provides the high controllability to the dielectric layer of deposition.

Preferably, the step of dielectric layer deposition comprises the deposition of at least a following material: silicon dioxide and silicon nitride.

And, adopt a kind of step of preferably carrying out dielectric layer deposition of following technology: ald (ALD) and low-pressure chemical vapor deposition (LPCVD).

The invention still further relates to the MEMS oscillator that comprises the MEMS resonator.Less interval helps to reduce the motional impedance of MEMS resonator.Need low motional impedance (for example,＜10kOhm) to obtain low oscillator phase during resonance.

The invention still further relates to a kind of integrated circuit that comprises this MEMS oscillator.The technological process that forms silicon oxide layer and integrated circuit on resonistor is compatible.Therefore, allow relatively directly to carry out integrated according to MEMS resonator of the present invention to the Monolithic integrated MEMS oscillator.

Any bells and whistles can be combined, and combines with any aspect.Other advantages are tangible for the those skilled in the art.Under the prerequisite that does not break away from claim of the present invention, variations and modifications are feasible.Therefore, should be understood that clearly that this specification is illustrative, rather than be used to limit the scope of the invention.

Description of drawings

With reference to the accompanying drawings, will describe the present invention in the mode of example and how to implement, wherein:

Fig. 1 a to Fig. 1 e illustrates the method for manufacturing MEMS resonator according to one embodiment of the method for the invention;

Fig. 2 illustrates and is forming the principle that reduces interval width under dielectric situation at interval on the sidewall by oxidation; And

Fig. 3 illustrates and is forming the principle that reduces interval width under dielectric situation at interval on the sidewall by being deposited on.

Embodiment

With reference to some accompanying drawing, will the present invention be described with regard to specific embodiment, be not limited thereto but this law is bright, its scope is only limited by claims.Any reference marker in the claims should not be understood that to limit its scope.Described accompanying drawing is schematically and is nonrestrictive.In the accompanying drawings, in order to illustrate purpose, some size of component are exaggerated, and do not draw in proportion.In current explanation and claim, use term " to comprise " or the place of " comprising ", do not get rid of other elements or step.When mentioning singular noun (for example " " or " a kind of ", " being somebody's turn to do "), adopt the place of indefinite article or definite article, this comprises the plural number of this noun, unless clearly statement.

And in specification and claim, the term first, second, third, etc. are used to distinguish similar element, are not to be used for describing sequencing and time sequencing.Should be appreciated that the term of Shi Yonging is interchangeable like this, and embodiments of the invention described herein can be with other operations in tandem except said or illustrated order under suitable situation.

Fig. 1 a to Fig. 1 e illustrates the MEMS resonator in each stage of according to one embodiment of the method for the invention MEMS manufacturing process.

Fig. 1 a refers to a stage of manufacturing process, and semiconductor body 100 wherein is provided.Substrate layer 20, the sacrifice layer 30 that is provided on substrate layer 20 and the top layer 40 that is provided on sacrifice layer 30 are provided semiconductor body 100.In one embodiment of the invention, top layer 40 can comprise silicon, but other materials also is feasible, for example, and germanium (Ge), as the III-V semiconducting compound of GaAs (GaAs), as the II-VI semiconducting compound and the other materials of indium phosphide.For sacrifice layer 30 materials, can adopt silicon dioxide (SiO ₂), but other materials also is feasible.Be used as at silicon under the situation of the material of top layer 40 and the material that silica (or other insulating material) is used as sacrifice layer 30, can adopt term silicon-on-insulator (SOI).On market, can obtain silicon-on-insulator substrate/wafer widely, and it can be made in the simple mode that is easy to.In the example shown in Fig. 1 a to Fig. 1 e, adopted the SOI substrate, wherein top layer 40 comprises silicon, and wherein insulation (sacrifice) layer 30 comprises silicon dioxide.

Fig. 1 b and Fig. 1 c illustrate other stages of manufacturing process.In Fig. 1 b, figuratum mask layer 55 is provided, it has opening 50.For example, can adopt traditional optical flat printing technology to finish mask layer 50 is formed pattern, but also can adopt other lithographic printing, for example e-beam lithography art, ion beam imprint lithography and x ray imprint lithography.In these technology, pattern is directly write on the mask layer 50.In this specific example, adopted photoetching technique.So, mask layer 50 can comprise photoresist layer, but also can be the hard mask of for example being made by silica or silicon nitride.In Fig. 1 c, by 55 pairs of top layers of opening, the 40 formation patterns of mask layer 50.Therefore, formed opening 45 in top layer 40, it is corresponding to the opening in the mask layer 55.This can finish by for example adopting dry etch step (for example DRIE etching).Lithographic technique is known by the those skilled in the art.Form opening 45, so that the sacrifice layer 30 below the exposed top layer 40.Also form interval 46,47, it defines the displaceable element 48 of the MEMS resonator that will make.

In Fig. 1 d, show other stages of manufacturing process, remove sacrifice layer 30 (sacrifice layer below the displaceable element at least) partly, partly to discharge displaceable element 48.Can finish this process by for example adopting the selectivity wet etching step.The selective etch technology is also for known to the those skilled in the art.Displaceable element is placed in (not shown in FIG.) between the clamped areas.In this specific example, displaceable element 48 (at least) with direction that at interval 46,47 sidewall is vertical on be movably.

Adopt electric capacity to change and encourage resonator with sensing silicon MEMS.The efficient of this conversion depends on the distance (interval width) between resonator and its exciting electrode and/or the sensing electrode to a great extent.Usually, in the great majority such as oscillator and accelerometer are used, require this distance less than 1 μ m.Adopt traditional photoetching technique can not make these narrow intervals.Fig. 1 e illustrates other stages of the manufacturing process of MEMS resonator according to one embodiment of the method for the invention.In this embodiment, reduce the width at the interval 46,47 in the top layer 40 with step of thermal oxidation.Thermal oxidation is known technology for the those skilled in the art.Under the situation of silicon thermal oxidation, the same with situation in the illustrated example, comprising O usually ₂Or H ₂Under about 1000 ℃ temperature, carry out oxidation step in the environment of O.Can be at S.Wolf, " Silicon processing ", Vol.1 finds the more information about thermal oxidation among the pp.198-241.

In Fig. 1 e, in all places that silicon is not capped, growthing silica SiO on 46,47 sidewall at interval especially ₂(dielectric).Yet,, can prevent the growth of silicon dioxide by partly or cover layer is provided in groove.Alternatively, next-door neighbour's silicon can adopt different materials, so that have only silicon oxidized in top layer 40.A kind of isolation technology of known this principle of employing is called as LOCOS (local oxidation of silicon).In LOCOS, adopt silicon nitride (Si ₃N ₄) avoid oxidation.Therefore, this technology makes only provides dielectric on a sidewall at interval 46,47.

Alternatively, except oxidation, can on the sidewall at interval 46,47, deposit dielectric (for example silica, and silicon nitride).There are several technology that are used to deposit, for example ald (ALD) and low pressure gas phase deposition (LPCVD).In order to guarantee on sidewall at interval, to deposit dielectric, can adopt inclination/shade deposition technique.At S.Wolf, " Siliconprocessing ", Vol.1 can find more information about the shade deposition among the pp.374.

Before or after the stage shown in Fig. 1 e, can carry out various other steps and finish this product, such as:

Part is removed the oxide of growth/deposition;

Form electrode;

Form bonding welding pad;

Form other circuit; Or the like.

Step above-mentioned is that the crowd knows to the those skilled in the art.

As shown in Figures 2 and 3, by to providing before the dielectric and afterwards significant interval width compares, can determine validity of the present invention.In Fig. 2, the interval width that illustrates under the situation that adopts silicon oxidation reduces, and in Fig. 3, the interval width that illustrates under the situation that adopts the silica deposition reduces.

With reference to Fig. 2, physical width is from g ₀Be reduced to g ₁.This is the result of spaced-apart sidewalls oxidation, and it is the oxide layer 60 of d that the oxidation of spaced-apart sidewalls has formed thickness.Parameter g ₀Represent the primary leading width, from the original sidewall S1 at interval 46,47, S2 measures before oxidation.Parameter g ₁Represent the physical gap width after the oxidation.

At two silicon main body (ε _rEquivalent interval width (the g of the capacitor that forms=3.9) _Eff) provide by following formula:

$g_{\mathrm{eff}}=g_1+\frac{2d}{{\mathrm{\ϵ}}_r}=g_1+\frac{2d}{3.9}$

Known silica at the oxide thickness 44% of having grown is lower than under the situation of initial surface physical gap width g ₁Can be following by primary leading width g ₀Expression:

$g_0=g_1+2d(1-0.44)$

$\⇒g_1=g_0-2d(1-0.44)$

With g ₁Formula substitution g _EffFormula after, obtain following relation:

$\⇒g_{\mathrm{eff}}=g_0-2d(1-0.44-\frac{1}{3.9})=g_0-0.61d\≥0.46g_0$

From described formula significant interval width g as can be seen _EffLess than primary leading width g ₀Minimum significant interval width after the oxidation is 0.46 g ₀, this thickness appears when following oxide thickness:

$0.56d_{\max }=0.5g_0$

$\⇒d_{\max }=\frac{0.5}{0.56}{g}_0=0.893g_0$

For the MEMS resonator that adopts the electric capacity conversion, this has caused the factor that reduces of its impedance when resonance be 0.46 ^-4=22.3.

With reference to Fig. 3, situation is different, and this is because under the dielectric situation of deposition, do not consume the silicon (or other materials) on the sidewall.At two silicon main body (ε _rEquivalent interval width (the g of the capacitor that forms=3.9) _Eff) be given by the following formula (being similar to Fig. 2):

$g_{\mathrm{eff}}=g_1+\frac{2d}{{\mathrm{\ϵ}}_r}=g_1+\frac{2d}{3.9}$

Yet, physical gap width g ₁Can be following by primary leading width g ₀Expression:

$g_0=g_1+2d$

$\⇒g_1=g_0-2d$

With g ₁Formula substitution g _EffFormula after, obtain following relation:

$\⇒g_{\mathrm{eff}}=g_0-2d(1-\frac{1}{3.9})=g_0-1.487d\≥0.256g_0$

As can be seen, from described formula, significant interval width g _EffOnce more less than primary leading width g ₀, under the situation of oxidation even littler.The minimum significant interval width is 0.256g after the oxidation ₀, this appears at oxide thickness d when being following situation:

d _max＝0.5g ₀

For the MEMS resonator, when resonance this to have caused the factor that reduces of its resistance be 0.256 ^-4=231.3.

Therefore the invention provides a kind of attractive MEMS resonator, it has good performance, and the MEMS resonator more known than prior art is easy to make more.The present invention also provides a kind of method of making this MEMS resonator, and its method more known than prior art is simpler.

Claims (8)

1. MEMS resonator, it comprises second electrode of first electrode and displaceable element (48) form, displaceable element (48) is movably towards first electrode at least, first electrode and displaceable element (48) are had the interval (46 of sidewall, 47) separately, wherein, first electrode and second electrode are as the part of the top layer (40) of semiconductor body (10) and form, wherein semiconductor body comprises substrate layer (20), sacrifice layer (30) and top layer (40), wherein under first electrode, there is sacrifice layer, and under second electrode (48), do not have sacrifice layer, and wherein at least one sidewall at interval (46,47), provide dielectric layer (60).

2. MEMS resonator as claimed in claim 1 is characterized in that providing dielectric layer (60) at least two sidewalls.

3. method of making the MEMS resonator, it may further comprise the steps:

Semiconductor body (10) is provided, and substrate layer (20), the sacrifice layer (30) that is provided on substrate layer (20) and the top layer (40) that is provided on sacrifice layer (30) are provided for it;

Form top layer (40) pattern, to form (46,47) at interval, (46,47) expose sacrifice layer (30) partly at interval, and (46,47) also are used to limit displaceable element (48) at interval;

Optionally remove sacrifice layer (30), so that moving meter (48) is partly discharged from substrate layer (20); And

On at least one sidewall at the interval (46,47) relevant, provide dielectric layer (60) with displaceable element (48) top layer (40) on every side.

4. method as claimed in claim 3 is characterized in that in the step that semiconductor body (10) are provided, and the top layer (40) that comprises silicon is provided on sacrifice layer (30).

5. method as claimed in claim 4 is characterized in that providing the step of dielectric layer (60) to comprise oxidation step, and thus, the silicon at least at least one sidewall at the interval (46,47) relevant with top layer (40) is converted into silica.

6. as claim 3 or 4 described methods, it is characterized in that providing the step of dielectric layer (60) to comprise dielectric layer deposition, at least one sidewall at the interval (46,47) relevant, provide this dielectric layer (60) with top layer (40).

7. MEMS oscillator, it comprises MEMS resonator as claimed in claim 1 or 2.

8. integrated circuit, it comprises MEMS oscillator as claimed in claim 7.

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