CN101393241B - TD-SCDMA far-end radio frequency unit antenna port standing wave ratio measurement method and apparatus - Google Patents

TD-SCDMA far-end radio frequency unit antenna port standing wave ratio measurement method and apparatus Download PDF

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CN101393241B
CN101393241B CN2008101975484A CN200810197548A CN101393241B CN 101393241 B CN101393241 B CN 101393241B CN 2008101975484 A CN2008101975484 A CN 2008101975484A CN 200810197548 A CN200810197548 A CN 200810197548A CN 101393241 B CN101393241 B CN 101393241B
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江浩洋
王峰
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Wuhan Feng and Zhida information technology limited liability company
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Wuhan Hongxin Telecommunication Technologies Co Ltd
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Abstract

The invention relates to a method for measuring standing wave ratio at an antenna port of a TD-SCDMA remote end radio frequency unit and a device carrying out the same. The device comprises a central processing unit CPU, a programmable gate array FPGA, a digital-to-analog converter, a frequency converter, a multi-path selecting switch and three to ten amplifiers with antennas, wherein the programmable gate array FPGA is connected with a base station, the digital-to-analog converter, the central processing unit CPU, the multi-path selecting switch and all the amplifiers with the antennas respectively, and the multi-path selecting switch is connected with the amplifiers with the antennas respectively, and the frequency converter is connected with the digital-to-analog converter and the multi-path selecting switch respectively. The invention centers on measuring the power of downlink pilot frequency accurately and positions the downlink pilot frequency slot accurately by using the FPGA; at the same time, the timeliness of the calculation is ensured by the framework of pure hardware, the CPU is in charge of the calculation with low timeliness requirements and less operand. The method can better measure the standing wave ratio at the antenna port and can also contribute to reducing the cost of the system, in particular a multi-antenna system, and improving the timeliness and miniaturization.

Description

TD-SCDMA far-end radio frequency unit antenna port standing wave ratio measurement method and device
Technical field
The present invention relates to a kind of in TD-SCDMA remote radio unit (RRU) system the method and apparatus of employed measurement antenna opening standing-wave ratio (SWR).
Background technology
Remote radio unit (RRU) (RRU) is an ingredient important in the 3G communication system, for being attached to a communication module of base station (NODE B).The remote radio unit (RRU) major function is to finish the blind area to cover, and reduces base station number, and this module can be delivered to the upper-level BTS that is depended on data by optical fiber.
TD-SCDMA is the framework of many antennas for what improve the covering power employing, common have 6 antennas and 8 antennas, therefore extremely important to the real-time detection of every antenna condition, and this parameter of standing-wave ratio (SWR) is with regard to the quality of fine embodiment antenna work, and therefore measuring standing-wave ratio (SWR) real-time and accurately has extremely important ground meaning to system diagnostics.Traditional method is that each radio-frequency module is comprising power detection mechanism, adopt chip that the root mean square of signal is measured and report the upper strata control system then, therefore can increase much for the multiaerial system cost, nor be beneficial to system's miniaturization, and then add to the difficulties for system stability.
Summary of the invention
The objective of the invention is in order to overcome the defective that classic method exists, provide that a kind of cost is low, real-time is high, control is accurate, help the TD-SCDMA far-end radio frequency unit antenna port standing wave ratio measurement method and the device of system's miniaturization.The present invention is to be core with field programmable gate array (FPGA), with respect to central processor CPU and these software control means of digital signal processor DSP, FPGA is parallel fully hardware structure, control very precisely for the signal measurement of certain time period, our measuring method can measure the power of descending pilot frequency in the TD-SCDMA agreement very accurately based on this, with respect to other time slot of TD-SCDMA, the power of descending pilot frequency the most stably exists.By measuring the power (P of forward direction descending pilot frequency respectively +) and back to descending pilot power (P -), pass through formula then
Figure DEST_PATH_GSB00000038480500011
Calculate standing-wave ratio (SWR).
Device of the present invention is made of following components as shown in Figure 2: the power amplifier of central processor CPU, programmable gate array FPGA, digital to analog converter, frequency changer, multidiameter option switch, a 3-10 band antenna, programmable gate array FPGA links to each other with the power amplifier of base station, digital to analog converter, central processor CPU, multidiameter option switch, each band antenna respectively, multidiameter option switch links to each other with the power amplifier of each band antenna respectively, and frequency changer links to each other with digital to analog converter, multidiameter option switch respectively.This function of installing each module is as follows: CPU is responsible for calculating the formula of VSWR, simultaneously the descending pilot frequency power detection is provided with basic parameter, FPGA is a power of being responsible for detecting in real time signal in the descending pilot frequency time slot, and note and report CPU, also to carry out in addition before and after the power amplifier of the control of multidiameter option switch and each band antenna to control; Analog to digital converter is to be responsible for allowing the analog if signal digitizing follow-up FPGA handle; Frequency changer is that radiofrequency signal is transformed to intermediate-freuqncy signal; Multidiameter option switch is that the multi-channel rf input signal is carried out routing, and a certain as required moment can only have the signal of the power amplifier of one road band antenna to deliver to subsequent treatment; Power amplifier can be sent front and back respectively to signal to control according to the front and back of FPGA.
TD-SCDMA far-end radio frequency unit antenna port standing wave ratio measurement method of the present invention may further comprise the steps:
A, forward power P +Test: (1) central processor CPU is configured the register of programmable gate array FPGA; (2) FPGA control multidiameter option switch gating road power amplifier, and the control power amplifier transmits forward signal according to the configuration of CPU; (3) power amplifier transmits forward signal according to the control of FPGA, and chosen certain road power amplifier forward signal changes intermediate-freuqncy signal through frequency changer into from radiofrequency signal again by multidiameter option switch, and intermediate-freuqncy signal becomes digital signal and sends into FPGA by analog to digital converter; (4) the signal link time-delay set of the frame synchronizing signal brought according to the base station of FPGA and CPU is carried out power detection at descending pilot frequency place time slot exactly; (5) CPU waits for the time of two frames, guarantees that the collection computing of FPGA is finished, and the power register of CPU visit FPGA is finished forward power P then +Test;
B, back are to power P -Test: the register of (1) CPU configuration FPGA, select power amplifier to transmit backward signal, (2) FPGA is according to the configuration of CPU, control multidiameter option switch gating road power amplifier, and the control power amplifier transmits backward signal; (3) power amplifier transmits backward signal according to the control of FPGA, and chosen certain road power amplifier backward signal changes intermediate-freuqncy signal through frequency changer into from radiofrequency signal again by multidiameter option switch, and intermediate-freuqncy signal becomes digital signal and sends into FPGA by analog to digital converter; (4) the signal link time-delay set of the frame synchronizing signal brought according to the base station of FPGA and CPU is carried out power detection at descending pilot frequency place time slot exactly; (5) CPU waits for the time of two frames, guarantees that the collection computing of FPGA is finished, the power register of CPU visit FPGA then, after finishing to power P-test;
C, obtain standing-wave ratio (SWR): CPU obtains P +And P -After, utilize formula VSWR = P + + P - P + - P - Can calculate standing-wave ratio (SWR).
Described central processor CPU is configured the register of programmable gate array FPGA and comprises: front and back to the link time-delay of signal, down-bound pilot frequency signal with respect to the time slot at synchronizing signal place, select certain road power amplifier to test and select power amplifier to transmit forward signal.
P above-mentioned +And P -Do not need reality to be worth accurately, because the signal of coming from power amplifier is through overdamping, as long as guarantee that their decay is a unanimity.
The present invention is a core with accurate measurement descending pilot frequency power, utilizes FPGA that descending pilot frequency time slot is accurately located, and the framework of pure hardware has been guaranteed the real-time of computing simultaneously.The little calculating of the CPU less demanding operand of complementary responsible real-time.The present invention can measure the antenna opening standing-wave ratio (SWR) well, also helps system, especially multiaerial system to reduce cost, improve real-time and miniaturization simultaneously.
Description of drawings
Fig. 1 uses block diagram for TD-SCDMA RRU.
Fig. 2 is a TD-SCDMA RRU antenna opening SWR measurement device block diagram.
Fig. 3 concerns block diagram for the TD-SCDMA time slot.
Embodiment
Device of the present invention is made of following components as shown in Figure 2: the power amplifier of central processor CPU, programmable gate array FPGA, digital to analog converter, frequency changer, multidiameter option switch, 8 band antennas, programmable gate array FPGA links to each other with the power amplifier of base station, digital to analog converter, central processor CPU, multidiameter option switch, each band antenna respectively, the multidiameter option switch power amplifier of each band antenna respectively links to each other, and frequency changer links to each other with digital to analog converter, multidiameter option switch respectively.This function of installing each module is as follows: CPU is responsible for calculating the formula of VSWR, simultaneously the descending pilot frequency power detection is provided with basic parameter, FPGA is a power of being responsible for detecting in real time signal in the descending pilot frequency time slot, and note and report CPU, also to carry out in addition before and after the power amplifier of the control of multidiameter option switch and each band antenna to control; Analog to digital converter is to be responsible for allowing the analog if signal digitizing follow-up FPGA handle; Frequency changer is that radiofrequency signal is transformed to intermediate-freuqncy signal; Multidiameter option switch is that the multi-channel rf input signal is carried out routing, and a certain as required moment can only have the signal of the power amplifier of one road band antenna to deliver to subsequent treatment; Power amplifier can be sent front and back respectively to signal to control according to the front and back of FPGA.
According to TD-SCDMA time slot relation among Fig. 3, the power that we will test is descending pilot frequency (DwPTS), each chip is represented 0.78125us among the figure, frame synchronizing signal is initial synchronously with the TS0 time slot, just we are 675us at initial moment of sampling that FPGA is set, the time period of sampling is 75us, and the realization of these time-delays is that the high frequency clock by FPGA inside obtains by counting.In addition according to the time-delay of each module of system's reality, front and back also have the time-delay of 42us to signal, that is to say that our initial sampled point (being referred to synchronizing signal) is 717us in our device.Above parameter has been arranged, and we just can begin following step and carry out the SWR measurement of TD-SCDMA far-end radio frequency unit antenna port, and measuring method may further comprise the steps:
(1) CPU is configured the register of FPGA, and to the link time-delay of signal, down-bound pilot frequency signal selects certain road power amplifier to test with respect to the time slot at synchronizing signal place before and after comprising, selects power amplifier to transmit forward signal;
(2) FPGA controls multidiameter option switch gating road power amplifier according to the configuration of CPU;
(3) FPGA is according to the configuration of CPU, and the control power amplifier transmits forward signal;
(4) power amplifier transmits forward signal according to the control of FPGA;
(5) chosen certain road power amplifier forward signal has passed through multidiameter option switch;
(6) forward signal by multidiameter option switch is changed into intermediate-freuqncy signal by frequency changer from radiofrequency signal, and the TD-SCDMA signal of 2010MHz-2025MHz can be by the unified intermediate-freuqncy signal that is transformed into 96MHz in our device;
(7) intermediate-freuqncy signal becomes digital signal by analog to digital converter;
(8) for digitized signal, the signal link time-delay that frame synchronizing signal that FPGA brings according to the base station and CPU set is carried out power detection at descending pilot frequency place time slot exactly;
(9) CPU waits for 10ms, and the frame of TD-SCDMA is 5ms, guarantees that the collection computing of FPGA is finished, and the power register of CPU visit FPGA has so just been finished the test of forward power P+ then;
(10) register of CPU configuration FPGA selects power amplifier to transmit backward signal, and repeating step (2) is to (9), and forward signal wherein becomes backward signal, has so just finished back to power P -Test;
(11) CPU obtains P +And P -After, utilize formula VSWR = P + + P - P + - P - Can calculate standing-wave ratio (SWR).
P above-mentioned +And P -Do not need reality to be worth accurately, because the signal of coming from power amplifier is through overdamping, as long as guarantee that their decay is a unanimity.

Claims (3)

1.TD-SCDMA far-end radio frequency unit antenna port SWR measurement device, comprise: the power amplifier of central processor CPU, programmable gate array FPGA, digital to analog converter, frequency changer, multidiameter option switch, a 3-10 band antenna, it is characterized in that: programmable gate array FPGA links to each other with the power amplifier of base station, digital to analog converter, central processor CPU, multidiameter option switch, each band antenna respectively, multidiameter option switch links to each other with the power amplifier of each band antenna respectively, and frequency changer links to each other with digital to analog converter, multidiameter option switch respectively.
2.TD-SCDMA far-end radio frequency unit antenna port standing wave ratio measurement method may further comprise the steps:
A, forward power P +Test: (1) central processor CPU is configured the register of programmable gate array FPGA; (2) FPGA control multidiameter option switch gating road power amplifier, and the control power amplifier transmits forward signal according to the configuration of CPU; (3) power amplifier transmits forward signal according to the control of FPGA, and chosen certain road power amplifier forward signal changes intermediate-freuqncy signal through frequency changer into from radiofrequency signal again by multidiameter option switch, and intermediate-freuqncy signal becomes digital signal and sends into FPGA by analog to digital converter; (4) the signal link time-delay set of the frame synchronizing signal brought according to the base station of FPGA and CPU is carried out power detection at descending pilot frequency place time slot exactly; (5) CPU waits for the time of two frames, guarantees that the collection computing of FPGA is finished, and the power register of CPU visit FPGA is finished forward power P then +Test;
B, back to power P-test: the register of (1) CPU configuration FPGA, select power amplifier to transmit backward signal, (2) FPGA is according to the configuration of CPU, control multidiameter option switch gating road power amplifier, and the control power amplifier transmits backward signal; (3) power amplifier transmits backward signal according to the control of FPGA, and chosen certain road power amplifier backward signal changes intermediate-freuqncy signal through frequency changer into from radiofrequency signal again by multidiameter option switch, and intermediate-freuqncy signal becomes digital signal and sends into FPGA by analog to digital converter; (4) the signal link time-delay set of the frame synchronizing signal brought according to the base station of FPGA and CPU is carried out power detection at descending pilot frequency place time slot exactly; (5) CPU waits for the time of two frames, guarantees that the collection computing of FPGA is finished, the power register of CPU visit FPGA then, after finishing to power P-test;
C, obtain standing-wave ratio (SWR): CPU obtains P +And P -After, utilize formula
Figure FSB00000038480400011
Can calculate standing-wave ratio (SWR).
3. standing wave ratio measurement method according to claim 2 is characterized in that: described central processor CPU is configured the register of programmable gate array FPGA and comprises: front and back to the link time-delay of signal, down-bound pilot frequency signal with respect to the time slot at synchronizing signal place, select certain road power amplifier to test and select power amplifier to transmit forward signal.
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CN103063908B (en) * 2009-08-27 2015-06-10 珠海银邮光电技术发展股份有限公司 Method of detecting mobile communication system antenna standing wave ratio by radio frequency identification devices (RFID)
CN101834677B (en) * 2010-03-11 2013-12-04 京信通信系统(中国)有限公司 Base band power statistic-based standing wave detecting system and method for radio frequency remote system
CN102215074B (en) * 2011-06-03 2014-01-01 京信通信系统(中国)有限公司 Power and standing-wave radio detection device and method
CN102215075A (en) * 2011-06-03 2011-10-12 大唐移动通信设备有限公司 Method and device for carrying out standing wave detection on antenna
CN106324352B (en) * 2015-06-18 2019-01-22 国家新闻出版广电总局无线电台管理局 The standing-wave ratio detection circuit of multifrequency medium wave transmitter
CN107449981A (en) * 2017-07-24 2017-12-08 武汉虹信通信技术有限责任公司 The simple multiple signals coupling detection means and method of power of mobile communication amplifier
CN114039622B (en) * 2021-11-06 2023-07-28 四川恒湾科技有限公司 Method for realizing switching of synchronous surface between network ports on radio frequency unit

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