CN1013913B - Analogue /digital converter of current model - Google Patents

Abstract

The present invention relates to a current-mode analog-to-digital converter, which belongs to the design of an integrated circuit. The present invention adopts the parallel technology of parallel input and parallel output and a bit-by-bit comparison technology that the bit-by-bit comparison is carried out from a high bit to a low bit to determine a reference signal of the next bit. the current-mode analog-to-digital converter is composed of a weighted PMOS constant-current source, a group of current switches and an NMOS current mirror. The present invention has the advantages of high integration, high speed, simple circuit, easy realization, etc.

Description

Analogue /digital converter of current model

The invention belongs to integrated circuit (IC) design.

A/D converter (A/D) has a very important role in Analog signals'digital is handled, and along with the development of microprocessor, development low-cost, high-speed and the A/D converter that microprocessor is compatible has been subjected to more and more many attention.

Extensively can be divided into two classes usually in the mould/number conversion technology of usefulness at present:

1. parallel A/D converter technology.Reaching the decoding network [3] that is made of basic gate circuit by resistance pressure-dividing network [1], one group of comparator [2] as shown in Figure 1 forms.It is a kind of fastest transducer, and its course of work is actually the quantizing process of analog quantity, that is to say that for N parallel-by-bit A/D converter, its analog references amount at first is divided into 2 with electric resistance partial pressure ^NIndividual quantization unit, they are corresponding to (2 ^N-1) individual equal quantized interval, when analog quantity is imported, the pairing quantification number output of reference quantity that will be approaching after just comparing with it with all quantization unit, and through the corresponding N bit digital quantity of decoding network output.Fig. 1 represents the schematic diagram of one three parallel-by-bit A/D converter.This shows, this A/D converter is parallel the comparison, so speed is higher, yet because too much figure place requires numerous comparators, for example need 7 comparators, then need 256 comparators and huge decoding circuit for 8 A/D converters for 3 A/D converters.Because divider resistance and the discreteness of each comparator input offset voltage and the existence of bias current also can produce certain nonlinearity erron, this just brings the difficulty on the integrated technique, thereby has limited the raising of precision in addition.And in this technology ambipolar still in the highest flight;

2. gradual approaching/number converter.It is by one group of binary weighted capacitance network [4], and a switch and a high-speed high-performance comparator [2] and controller network [5], trigger network [6], clock signal [7] are formed, and be as shown in Figure 2, simple in structure.But it is under the control of CP timeticks, compare to low level successively by a high position, therefore its speed is subjected to certain limitation, promptly finish one-off pattern/number conversion and need the repeatedly time interval usually, for example need N clock pulse at least, and its change-over time is with figure place N linear growth for the conversion of N position.

The former speed is fast in above-mentioned two kinds of A/D converter technical schemes, but the circuit structure complexity is difficult to realize that the latter is simple in structure but speed is slow.The objective of the invention is to overcome the deficiency of these two kinds of technical schemes, make it the advantage of the two, propose a kind ofly have high integratedly, high-speed, circuit is simple, the electric current pattern/number conversion technology that is easy to realize.

The present invention proposes a kind of analogue/digital converter of current model technical scheme, utilize the current multi-way inverter to realize parallel input, constant-current source reference signal and current switch are realized current ratio, and can be in a pulse interval from a high position to the low technology of relatively determining the next reference current signal by turn.The analogue/digital converter of current model that this technology constitutes as shown in Figure 3, it is by a current multi-way inverter circuit [8], the constant-current source of a plurality of weightings [9], corresponding current switch array, with the current ratio that realizes input signal and reference signal, its operation principle is described below:

The input of analog quantity electric current reaches the parallel purpose of importing through the current multi-way inverter circuit, makes input signal be input to an end of each comparator concurrently, is I for first reference current _REF/ 2 electric current and analog quantity input current compare, and its comparative result determines the reference current value of several of backs simultaneously; Removing one's own department or unit reference quantity for second reference current is I _REF/ 2 ²Outward, primary result determines I simultaneously _REFWhether/2 reference current amounts add deputy comparator; And the like for the N position, remove one's own department or unit reference quantity I _REF/ 2 ^NOutward, first, second ... the comparative result of N-1 position determines reference quantity I respectively _REF/ 2, I _REF/ 2 ², I _REF/ 2 ^N-1The comparator that whether adds the N position, its control procedure is respectively by switch S ₁..., Sn-1 realizes.

Said current multi-way inverter circuit can utilize it to amplify reduction capability in design among the present invention, required reference constant-current source scope is dwindled, this circuit can be made of a plurality of nmos pass transistors in parallel, the weighting constant-current source can use PMOS transistor or other devices and circuit to constitute, current switch can be used nmos pass transistor, the PMOS transistor, cmos transmission gate or other devices and circuit constitute.

Several main feature of the present invention:

1. adopt parallel input neatly, parallel export technique and approximation technique one by one, make entire method have the advantage of the high-speed and high integration of approaching A/D converter at a high speed and one by one of parallel A/D converter simultaneously, be in particular in and utilize NMOS current mirror multichannel inverting function, input signal is input to each comparator concurrently, and compares with corresponding reference current; For output, adopt parallel interface, whole mould/number conversion is finished with interior at a time beat;

2. adopt weighting constant-current source and current switch to come to control the size of low level reference current according to the result of high bit comparison;

3. the output of current comparator is through the shaping of standard CMOS inverter, and the series connection that can utilize CMOS inverter [10] simultaneously is to reach the synchronous needs of multichannel output;

4. consider that reference current is from 2 ^-1To 2 ^-7Can produce certain error, therefore in design, can make full use of the amplification reduction capability of the current multi-way inverter circuit of NMOS current mirror composition, required reference constant-current source scope is dwindled.For example, select ten sixths, promptly with the wide length of breadth length ratio input pipe of efferent ducts such as each NMOS current mirror of low level for a full MOS8 position A/D converter

(W/L) _5～8=(1/16) (W/L) _1NBecause

_REF＝I _REF（ (D1)/2 ＋ (D2)/22 ＋ (D3)/23 ＋ (D4)/24 ＋ (D5)/25 ＋ (D6)/26 ＋ (D7)/27 ＋ (D8)/28

Can be write as

_REF=I _REF((D ₁)/(2 ¹)+(D ₂)/(2 ²)+(D ₃)/(2 ³)+1/16 ((D ₅)/(2 ¹)+(D ₆)/(2 ²)+(D ₇)/(2 ³)+(D ₈)/(2 ⁴)))

Make absolute error with reference to constant-current source from 2 like this ^-1To 2 ^-4, help further improving the precision of A/D converter.

Brief Description Of Drawings:

Fig. 1 is the A/D converter of concurrent technique

Fig. 2 is one by one the A/D converter of approximation technique

Fig. 3 is that parallel input of the present invention and line output reach the A/D converter of comparison techniques by turn

Fig. 4 is 4 A/D converters of one embodiment of the invention

A kind of embodiment of the present invention be 4 digit current pattern/number converters as shown in Figure 4, it is by the PMOS constant-current source of 11 weightings, the current mirror that the current switch that 6 nmos pass transistors are formed and 5 NMOS constitute is formed.

D wherein ₁Expression highest order (MSB), D ₄Expression lowest order (LSB), reference current I _REFFull shelves (Full-Scale) current value that equals to change.When the input analog current signal is Ia.Like this for highest order (MSB), if Ia is greater than I _REF/ 2, then the voltage located of node (a) is low level, and MSB=0 is through one-level inverter MSB=1; If Ia is less than I _REF/ 2, it is high level that node (a) is located voltage, MSB=1, then MSB=0.Bit D ₁State changing nmos switch S simultaneously ₁Open and closed.For the second bit D ₂If, last time comparative result MSB=1, nmos switch S ₁Conducting, then I _REF/ 2 act on the second bit D ₂Comparator, otherwise nmos switch disconnects I in the above two kinds of cases _REF/ 2 ²+ D ₁I _REF/ 2 with Ia relatively to determine the second bit D ₂State " 1 " or " 0 ", can determine the 3rd bit D equally ₃With the 4th bit D ₄State " 1 " or " 0 ", and the like can get 8 even more high-order situation, for example can be write as for the state of 8 every bits of A/D converter:

$D_i\mathrm{=S}{}_{\mathrm{ign}}\mathrm{［I}{}_a\mathrm{-(}$ (I _RET)/(2 ³) + $\underset{\mathrm{j=1}}{\overset{\mathrm{i-1}}{\mathrm{\Σ}}}$ (D ³)/(2 ³) I _REF)](i=1,2,……8）

Wherein:

We adopt the standard CMOS process design and have made 4 MOS analogue/digital converter of current model, the wherein transistorized pinch-off voltage V of PMOS in view of the above _P=-1.5V, the cut-in voltage V of nmos pass transistor _T=1.0V, the breadth length ratio of NMOS current mirror (W/L) _N=(100 μ m/10 μ m), the breadth length ratio of NMOS current switch (W/L) _N=(100 μ m/10 μ m), the breadth length ratio of the input pipe of PMOS current mirror (W/L)=(160 μ m/10 μ m), efferent duct is respectively 80 μ m/10 μ m, 40 μ m/10 μ m, 20 μ m/10 μ m, 10 μ m/10 μ m, V _DD=5V.

Claims (2)

1, a kind of full MOS analogue/digital converter of current model, it is characterized in that forming the current multi-way inverter circuit of realizing parallel input by a plurality of nmos pass transistors in parallel, the constant-current source of a plurality of weightings, and corresponding current switch array a plurality of current comparator that constitute, that analog signal and each reference signal of input compared concurrently constitutes.

2, a kind of analogue/digital converter of current model of full MOS according to claim 1 is characterized in that said current mirror is the NMOS current mirror, and said constant-current source is the PMOS transistor, and said current switch is a nmos pass transistor.

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