CN101383186B - Programming method and device of NAND type flash memory and reading method - Google Patents
Programming method and device of NAND type flash memory and reading method Download PDFInfo
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- CN101383186B CN101383186B CN2007101497685A CN200710149768A CN101383186B CN 101383186 B CN101383186 B CN 101383186B CN 2007101497685 A CN2007101497685 A CN 2007101497685A CN 200710149768 A CN200710149768 A CN 200710149768A CN 101383186 B CN101383186 B CN 101383186B
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Abstract
The invention relates to a programming method, a device and a reading method of a flash memory of an NAND gate type. Under the condition that data quantity in once programming does not occupy the storage capacity of all data storage areas in a page, the programming method and the device which are provided by the invention can shorten the data programming time of the page so as to further increase the whole data programming speed of the flash memory of an NAND gate type. In addition, under the condition that data quantity in once reading does not occupy the storage capacity of all the data storage areas in the page, the reading method of the flash memory of an NAND gate type, which is provided by the invention, can decrease the data reading number of the page so as to further decrease the whole reading number of the flash memory of an NAND gate type.
Description
Technical field
The present invention relates to a kind of programming and read method of Sheffer stroke gate type flash memory, and particularly relate to a kind of programmed method and the device that can accelerate Sheffer stroke gate type flash memory overall data program speed, and the read method that can reduce Sheffer stroke gate type flash memory overall data reading times.
Background technology
Generally speaking, Sheffer stroke gate type flash memory (NAND flash memory) mainly is made up of a plurality of blocks (Block), and each block inside is divided into the identical paging of a plurality of memory capacity (Page), and each paging inside has a plurality of data storage area (data storage area) and difference pairing clear area (spare area) thereof again.With the paging size specification is that 2Kbytes+64bytes/page is an example, its inside has the data storage area and the clear area of the memory capacity of pairing 4 16bytes respectively thereof of the memory capacity of 4 512byte s, and be that 4Kbytes+128bytes/page is an example with the paging size specification again, its inside has the data storage area and the clear area of the memory capacity of pairing 8 16bytes respectively thereof of the memory capacity of 8 512bytes.
What deserves to be mentioned is earlier at this, can deposit some auxiliary data in above-mentioned each clear area, for example: the error correction sign indicating number (error correction code, ECC), bad block information (bad block information) ... Deng.Wherein, error correcting code is the fiduciary level that is used for promoting the stored data of data storage area that read each paging; And bad block information (bad block information) is used for judging whether block is damage, for instance, when first byte of the pairing clear area of first paging of block or second paging when first paging damages (if) be not the 0xFF digital value, promptly represent the block of this block for damage.
Know as industry, when Sheffer stroke gate type flash memory carries out data programing (program) or reads (read), must be unit with a paging, till last clear area be programmed/be read to the mode of operation of and data programing/read must in regular turn from first data storage area in the paging again.Also because of like this, known when carrying out the operation of data programing/read at a paging, must programme/read after the data of all data storage area in the full paging, then could carry out the programming of data/read the pairing clear area of described data storage area.
Yet, with the paging size specification is that 2Kbytes+64bytes/page or 4Kbytes+256bytes/page are example, in the operation of data programing/read, the data volume of once programming/reading might not just be the memory capacity of all data storage area in the paging, so with this understanding, just can't be in data programing/read operation once, the data of the clear area that the data storage area in this paging of programming simultaneously/read is corresponding with it.
Also because of like this, known in the operation of data programing/read, when the data volume of once programming/reading is not equal under the condition of the memory capacity of all data storage area in the paging, again data programing/when reading is carried out in the data storage area in this paging and corresponding clear area thereof, traditionally, must carry out data programing/read operation one time to this paging earlier at data storage area, this data storage area is carried out data programing/read.Then, when data storage area is finished data programing/after reading, must be again at its corresponding clear area, data programing/read operation that another time carried out in this paging is to carry out data programing/read to this clear area.
So according to as can be known above-mentioned, because traditional Sheffer stroke gate type flash memory is in the operation of data programing/read, can't be not equal under the condition of the memory capacity of all data storage area in the paging in the data volume of one-time programming/read, simultaneously the programming of data is carried out in data storage area and corresponding clear area thereof or read.Therefore, in the face of this situation, the mode of known solution is that repeatedly data programing/read operation is carried out in this paging mostly, just can reach by this simultaneously data storage area and corresponding clear area thereof carrying out the programming of data or read.
Yet, the time that Sheffer stroke gate type flash memory carries out a data programing is equivalent to want 300us, so follow under the state of this type of settling mode, just must spend 600us at least for data programing time of data storage area in the paging and corresponding clear area thereof.Moreover if will carry out discontinuous again words in address between the data storage area of data programing in this paging, then longer that time of data programing will be drawn finished in this paging.So, not only can make the speed of Sheffer stroke gate type flash memory overall data programming become quite slow, and also can increase the number of times that Sheffer stroke gate type flash memory overall data reads.
Summary of the invention
In view of this, purpose of the present invention just provides a kind of programmed method and device of Sheffer stroke gate type flash memory, under the condition of its memory capacity of all data storage area in the discontented paging of institute's data programmed amount once, can reduce the data programing time of paging, and then accelerate Sheffer stroke gate type flash memory overall data program speed.
Another object of the present invention just provides a kind of read method of Sheffer stroke gate type flash memory, under the condition of its memory capacity of all data storage area in the discontented paging of the data volume that is once read, can reduce the data read number of times of paging, and then reduce Sheffer stroke gate type flash memory overall data reading times.
Based on purpose above-mentioned and that will reach, the present invention proposes a kind of programmed method of Sheffer stroke gate type flash memory.This Sheffer stroke gate type flash memory includes the identical paging of a plurality of memory capacity, and each paging inside has a n data storage area and the pairing n of a difference clear area thereof.Wherein, the start address of (i+1) individual data storage area continues in the end address of i data storage area, and the continue start address of (i+1) individual clear area of the end address of i clear area, n is that positive integer, the i more than or equal to 2 is the positive integer less than n.In addition, the start address of the 1st clear area in the described n clear area end address of n data storage area of continuing.
The programmed method of Sheffer stroke gate type flash memory proposed by the invention comprises the following steps: at first, when first paging in the described paging will be carried out data programing, determine will carry out k data storage area of data programing in this first paging and distinguish a pairing k clear area, wherein k is the positive integer that is not more than n.
Then, the 1st data storage area in first paging begins to carry out data loading operations thus in regular turn, till n clear area, wherein said data loading operations flow process comprises: load tentation data to described k data storage area, and load corresponding to the auxiliary data of a tentation data described k clear area extremely; And load in obliterated data to the first paging remaining (n-k) individual data storage area and (n-k) individual clear area.
At last, described k data storage area and a described k tentation data that the clear area is loaded respectively and auxiliary data are programmed, and programmed in described (n-k) individual data storage area and described (n-k) obliterated data that individual clear area loaded.
From another viewpoint, the present invention proposes a kind of read method of Sheffer stroke gate type flash memory, it comprises the following steps: at first, when described first paging will be carried out data read, determine that this first paging Chinese medicine carries out k data storage area of data read and distinguishes a pairing k clear area, wherein k is the positive integer that is not more than n.Then, the 1st data storage area in first paging begins to carry out data read operation thus in regular turn, till n clear area, wherein said data read operation flow process comprises: read stored tentation data in described k the data storage area, and read corresponding to stored auxiliary data in described k the clear area of tentation data; And do not read remaining (n-k) individual data storage area in this first paging and (n-k) distinguish stored tentation data and auxiliary data in the individual clear area.
From another viewpoint, the present invention proposes a kind of programmer of Sheffer stroke gate type flash memory again, and it comprises decision signal generation unit, decision package, and control module.Wherein, the decision signal generation unit is used for producing decision signal, uses definite described first paging and will carry out k data storage area of data programing and distinguish a pairing k clear area, and wherein k is the positive integer that is not more than n.
Decision package couples the decision signal generation unit, in order to described decision signal of foundation and control signal, and begin to carry out data loading operations by the 1st data storage area in described first paging in regular turn, till n clear area, wherein said data loading operations is to load tentation data described k data storage area, load the auxiliary data corresponding to tentation data described k clear area, and in described first paging remaining (n-k) individual data storage area and (n-k) individual clear area loading obliterated data.
Control module couples Sheffer stroke gate type flash memory, decision signal generation unit and decision package, in order to described control signal to be provided and to assign the order register of program command to Sheffer stroke gate type flash memory inside, use described k data storage area and a described k tentation data that the clear area is loaded respectively and auxiliary data are programmed, and programmed in described (n-k) individual data storage area and described (n-k) obliterated data that individual clear area loaded.
In one embodiment of this invention, decision package comprises designating unit, arithmetic element, data supply unit, and selected cell.Wherein, designating unit couples control module, in order to produce specification signal accordingly according to described control signal.Arithmetic element couples decision signal generation unit and designating unit, in order to according to described decision signal and described specification signal, selects signal and produce.The data supply unit couples control module, in order to the described control signal of foundation, and corresponding generation tentation data, auxiliary data and obliterated data.Selected cell couples arithmetic element and data supply unit, in order to the described selection signal of foundation, and provide tentation data to load, provide auxiliary data to load, and provide obliterated data to load to described (n-k) individual data storage area and described (n-k) individual clear area to described k clear area corresponding to tentation data to described k data storage area.
Because under the condition of the programmed method of Sheffer stroke gate type flash memory provided by the present invention and the device memory capacity of all data storage area in the discontented paging of institute's data programmed amount once, data storage area and the pairing clear area thereof that will carry out data programing in the paging are loaded tentation data and auxiliary data respectively, and the data storage area and the pairing clear area thereof of not carrying out data programing in the paging all loaded obliterated data (that is digital value of 0xFFH).
Therefore, the programmed method of Sheffer stroke gate type flash memory provided by the present invention can carry out in the time of a data programing at Sheffer stroke gate type flash memory with device, data storage area and the pairing clear area thereof that will carry out data programing in the paging are loaded tentation data and auxiliary data respectively, and be different from the settling mode that prior art proposes, so can reduce the data programing time of each paging, and then accelerate Sheffer stroke gate type flash memory overall data program speed.
In addition, because under the condition of the read method of Sheffer stroke gate type flash memory provided by the present invention memory capacity of all data storage area in the discontented paging of the data volume that is once read, only read in the data storage area that will carry out data read in the paging and the pairing clear area thereof the tentation data and the auxiliary data that store respectively, and do not read in the data storage area of not carrying out data read in the paging and the pairing clear area thereof the tentation data and the auxiliary data of storage respectively.
Therefore, the read method of Sheffer stroke gate type flash memory provided by the present invention can carry out in the time of a data read at Sheffer stroke gate type flash memory, read out in the data storage area that will carry out data read in the paging and the pairing clear area thereof the tentation data and the auxiliary data that store respectively, can rise so read the fiduciary level of the stored data of each data storage area in the paging, and can also judge the block of Sheffer stroke gate type flash memory internal damage.Moreover, because the data read number of times of each paging only is 1 time, so can reduce Sheffer stroke gate type flash memory overall data reading times.
And be that above-mentioned and its purpose that is reached, feature and advantage of the present invention can be become apparent, one embodiment of the invention cited below particularly, and be described with reference to the accompanying drawings as follows.
Description of drawings
Fig. 1 shows the synoptic diagram that the paging size specification is 2Kbytes+64bytes/page and 4Kbytes+128bytes/page.
Fig. 2 shows the programmed method process flow diagram of the Sheffer stroke gate type flash memory of one embodiment of the invention.
Fig. 3 shows the circuit system calcspar of programmer of the Sheffer stroke gate type flash memory of one embodiment of the invention.
Fig. 4 shows the read method process flow diagram of the Sheffer stroke gate type flash memory of one embodiment of the invention.
The reference numeral explanation
101: specification is the paging of 2Kbytes+64bytes/page
SDA1-SDA8: data storage area
SA1-SA8: clear area
S201-S205: each step of programmed method process flow diagram of the Sheffer stroke gate type flash memory of one embodiment of the invention
300: the device of Sheffer stroke gate type flash memory
301: Sheffer stroke gate type flash memory
303: the decision signal generation unit
305: decision package
307: control module
309: designating unit
311: arithmetic element
313: the data supply unit
315: selected cell
DS[4:1]: decision signal
P[8:1]: specification signal
CS: control signal
S401-S403: each step of read method process flow diagram of the Sheffer stroke gate type flash memory of one embodiment of the invention
Embodiment
The spirit that the present invention will set forth is carried out the time of data programing for shortening interior each paging of Sheffer stroke gate type flash memory on the one hand, and then reaches the speed of accelerating the programming of Sheffer stroke gate type flash memory overall data; Then carry out the number of times of data read on the other hand, can promote the fiduciary level that reads stored data in interior each paging of Sheffer stroke gate type flash memory simultaneously for reducing interior each paging of Sheffer stroke gate type flash memory.And following content will be done a detailed description with the effect that will reach at the technical characterictic of this case, to offer this invention those skilled in the relevant art reference.
Generally speaking, Sheffer stroke gate type flash memory mainly is made up of a plurality of block, and each block inside is divided into the identical paging of a plurality of memory capacity, and each paging inside has a n data storage area and the pairing n of a difference clear area thereof.Wherein, the start address of (i+1) individual data storage area continues in the end address of i data storage area, and the continue start address of (i+1) individual clear area of the end address of i clear area, n is that positive integer, the i more than or equal to 2 is the positive integer less than n.In addition, the start address of the 1st clear area in the described n clear area end address of n data storage area of continuing.
Fig. 1 shows the synoptic diagram that the paging size specification is 2Kbytes+64bytes/page and 4Kbytes+128bytes/page.Please refer to Fig. 1, with paging 101 size specifications is that 2Kbytes+64bytes/page is an example, and its inside has data storage area (the data storage area) DSA1-DSA4 of the memory capacity of 4 512bytes and distinguishes clear area (spare area) SA1-SA4 of the memory capacity of pairing 4 16bytes.Wherein, data storage area DSA1-DSA4 is in order to storage data, and the existing in the prior art explanation of the purposes of clear area SA1-SA4, so no longer given unnecessary details at this.
And according to as can be known above-mentioned, the end address (511H) of the 1st data storage area DSA1 the continue start address (1024H) of the 3rd data storage area DSA3 of the end address (1023H) of the start address (512H) of the 2nd data storage area DSA2, the 2nd data storage area DSA2 that continues, the start address (1536H) of the 4th data storage area DSA4 and continue in the end address (1535H) of the 3rd data storage area DSA3.
In addition, the start address (2048H) of the 1st the clear area SA1 end address (2063H) of the end address (2047H) of the 4th data storage area SDA4, the 1st clear area SA1 the continue start address (2080H) of the 3rd clear area SA3 of the end address (2079H) of the start address (2064H) of the 2nd clear area SA2, the 2nd clear area SA2 that continues that continues, the start address (2096H) of the 4th clear area SA4 and continue in the end address (2095H) of the 3rd clear area SA3.
Fig. 2 shows the programmed method process flow diagram of the Sheffer stroke gate type flash memory of one embodiment of the invention.Please merge with reference to figure 1 and Fig. 2, the programmed method of the Sheffer stroke gate type flash memory of present embodiment is that 2Kbytes+64bytes/page is that example illustrates with paging 101 size specifications temporarily, but not as limit.The programmed method of the Sheffer stroke gate type flash memory of present embodiment comprises the following steps: at first, as described in step S201, when a paging 101 in the inner block of Sheffer stroke gate type flash memory will be carried out data programing, determine will carry out k data storage area of data programing in this paging 101 and distinguish a pairing k clear area, wherein k is the positive integer that is not more than n.
In this step S201, before paging 101 will be carried out data programing, the programming software of Sheffer stroke gate type flash memory can be assigned continuous data input command (serial data input command earlier, be generally digital value 80H) to the order register (command register) of Sheffer stroke gate type flash memory inside, use notice Sheffer stroke gate type flash memory and will carry out data programing the paging 101 of its inside.
In addition, determine to carry out in the paging 101 data storage area and the clear area of data programing, it for example can specify the start address of the data storage area SDA1-SDA4 and the pairing clear area SA1-SA4 thereof that will carry out data programing in this paging 101, can determine data storage area and the clear area that will carry out data programing in this paging 101 by this.And thus, the programming software of Sheffer stroke gate type flash memory can judge in regular turn just whether the start address of each data storage area SDA1-SDA4 in this paging 101 and pairing clear area SA1-SA4 thereof is designated, and if designated, promptly represent it will carry out the data storage area and the clear area of data programing in paging 101 for this reason.And for convenience of description, that supposes that this paging 101 will carry out data programing only has data storage area SDA1 and a pairing clear area SA1 thereof, but is not limited to this.
As previously mentioned, because when Sheffer stroke gate type flash memory is carried out data programing (program) or reads (read), must be unit with a paging, and data programing or the mode of operation that reads must be programmed in regular turn/read to again till last clear area SA4 from first data storage area SDA1 in the paging 101.Therefore, behind step S201, the programmed method of the Sheffer stroke gate type flash memory of present embodiment can continue as described in the step S203, and the 1st data storage area SDA1 in the paging 101 begins to carry out data loading operations thus in regular turn, till the 4th clear area SA4.Wherein, this data loading operations flow process comprises: will be scheduled to data programmed and be loaded on data storage area SDA1, and will be loaded on clear area SA1 corresponding to the auxiliary data of this tentation data; In addition, obliterated data (that is digital value of 0xFFH) is loaded on all the other and does not carry out data programmed storage area SDA2-SDA4 and clear area SA2-SA4.
At last, the programmed method of the Sheffer stroke gate type flash memory of present embodiment can continue as described in the step S205, assigns the order register of program command to Sheffer stroke gate type flash memory inside.In this step S205, when all data storage area SDA1-SDA4 in the paging 101 and the data of pairing clear area SA1-SA4 in regular turn behind the loaded respectively thereof, the programming software of Sheffer stroke gate type flash memory will be assigned program command (program command, be generally the digital value of 10H) to the order register of Sheffer stroke gate type flash memory inside, programme with tentation data and auxiliary data that data storage area SDA1 and clear area SA1 are loaded respectively, and the obliterated data that data storage area SDA2-SDA4 and clear area SA2-SA4 are loaded is programmed.
Note that at this present invention in data programing operation once, the data programing operation has been carried out in each zone (comprising all data storage area and clear area) of whole paging, and its difference only is that its data programmed is different.By as can be known aforementioned, tentation data and its auxiliary data that the present invention deposits for specified data storage area and clear area (zone that meaning promptly really must programming data) its waist of can programming respectively, and for other zone, then all deposit obliterated data.
In addition, in known technology, because traditional Sheffer stroke gate type flash memory can't be not equal in the data volume of one-time programming under the condition of the memory capacity of all data storage area in the paging, simultaneously the programming of data is carried out in data storage area and corresponding clear area thereof.Therefore, in the face of this situation, the mode of known solution is that the data programing that this paging is carried out is repeatedly operated mostly, just can reach by this simultaneously the programming of data is carried out in data storage area and corresponding clear area thereof.Yet, from the above, the present invention does not have such problem and produces, it all can carry out the data programing operation because of the present invention to zones all in each paging, therefore the present invention can carry out the programming of data to data storage area and corresponding clear area thereof simultaneously in a data programing operation.
In other words, in the equivalence of the present invention real programming is carried out in the zone of wanting programming data in the paging, and to carrying out " vacation " programming in zone that need not programming data; And such mechanism just realizes by the design of obliterated data.Because the data programing operation only can change the state of storage unit in the Sheffer stroke gate type flash memory into logical zero from logical one, but can not transfer logical one to from logical zero, know as industry, if will transfer the state of storage unit to logical one from logical zero, must finish and can not operate by wiping (erase) operation by data programing.Therefore, as long as entrained data all are set at logical value 1 (that is digital value of aforementioned 0xFFH) in the obliterated data, so, even when utilizing obliterated data to be programmed in data zone/clear area, can the existing data in data zone/clear area not had any impact yet.
In view of the above, when the present invention carries out the data programming operation, can be in the operation of data programing to a paging in all zones that will programme carry out data programing (as previously mentioned, such running roughly only needs 300us), compared to known data programing operation (roughly needing more than the 600us), the time that data programing operation of the present invention can be saved half at least.
In addition, for whether desirable primary data storage area SDA1-SDA4 and pairing respectively clear area SA1-SA4 thereof have programmed finish, so that the programming software of Sheffer stroke gate type flash memory can carry out data programing to another paging.In the present embodiment, when the programming software of Sheffer stroke gate type flash memory is assigned program command to the order register of Sheffer stroke gate type flash memory inside, the programming software of this Sheffer stroke gate type flash memory can continue to detect preparation/busy pin (ready/busy, signal condition R/B) of the status register (status register) of Sheffer stroke gate type flash memory inside.
By this, when the signal condition that detects the preparation of the status register of Sheffer stroke gate type flash memory inside/busy pin (R/B) when the programming software of Sheffer stroke gate type flash memory is logical one, promptly represent tentation data and auxiliary data that data storage area SDA1 and clear area SA1 are loaded respectively, and the obliterated data that loaded of data storage area SDA2-SDA4 and clear area SA2-SA4 has been programmed and has been finished.Therefore, the programming software of Sheffer stroke gate type flash memory can carry out data programing to another paging again.
Yet, the tentation data and the auxiliary data that are loaded respectively as data storage area SDA1 and clear area SA1, and the obliterated data that loaded of data storage area SDA2-SDA4 and clear area SA2-SA4 programmed finish after, tentation data and auxiliary data that on behalf of data storage area SDA1 and clear area SA1, it loaded respectively, and the success of having programmed of the obliterated data that loaded of data storage area SDA2-SDA4 and clear area SA2-SA4.
Therefore, in the present embodiment, for tentation data and the auxiliary data that will guarantee that data storage area SDA1 and clear area SA1 are loaded respectively, and the success of having programmed of the obliterated data that loaded of data storage area SDA2-SDA4 and clear area SA2-SA4.After signal condition that the programming software of Sheffer stroke gate type flash memory detects the preparation of the status register of Sheffer stroke gate type flash memory inside/busy pin (R/B) was logical one, it also must detect the signal condition of passing through/fail (pass/fail) pin of the status register of Sheffer stroke gate type flash memory inside.
And when the signal condition of passing through/fail pin that detects the status register of Sheffer stroke gate type flash memory inside when the programming software of Sheffer stroke gate type flash memory is logical zero, promptly represent tentation data and auxiliary data that data storage area SDA1 and clear area SA1 are loaded respectively, and the success of having programmed of the obliterated data that loaded of data storage area SDA2-SDA4 and clear area SA2-SA4.Otherwise the programming software of Sheffer stroke gate type flash memory also can be again carries out data programing flow process as step S201-S205 to paging 101.
And the technology effect that can reach for the programmed method of the Sheffer stroke gate type flash memory that will realize the foregoing description, below will enumerate a kind of programmer of Sheffer stroke gate type flash memory again, so that the spirit that those skilled in the art can clearer understanding the present invention will set forth.
Fig. 3 shows the circuit system calcspar of programmer 300 of the Sheffer stroke gate type flash memory 301 of one embodiment of the invention.Please merge with reference to figure 1 and Fig. 3, the programmer 300 same elder generations of the Sheffer stroke gate type flash memory 301 of present embodiment are that 2Kbytes+64bytes/page is that example illustrates with paging 101 size specifications, but not as limit.The programmer 300 of the Sheffer stroke gate type flash memory 301 of present embodiment comprises decision signal generation unit 303, decision package 305, and control module 307.
In the present embodiment, when the paging 101 in the Sheffer stroke gate type flash memory 301 inner blocks will be carried out data programing, control module 307 can be before this paging 101 will be carried out data programing, assign the order register (not shown) of continuous data input command (80H) earlier, use notice Sheffer stroke gate type flash memory 301 and will carry out data programing the paging 101 of its inside to Sheffer stroke gate type flash memory 301 inside.
Then, decision signal generation unit 303 is understood generation 4 bit decisions signal DS[4:1], use and determine will carry out k data storage area of data programing in the paging 101 and distinguish a pairing k clear area.In the present embodiment, the 4 bit decisions signal DS[4:1 that produced of decision signal generation unit 303] state be the start address of specifying out the data storage area SDA1-SDA4 and the pairing clear area SA1-SA4 thereof that will carry out data programing in this paging 101.
And for convenience of description, what this paging 101 of same hypothesis will be carried out data programing only has data storage area SDA1 and a pairing clear area SA1 thereof, but be not limited to this, so the 4 bit decisions signal DS[4:1 that decision signal generation unit 303 is produced] state promptly be set at 0001B.
And what deserves to be mentioned is earlier at this, the 4 bit decisions signal DS[4:1 that control module 307 meetings are produced according to decision signal generation unit 303], and judge the start address of being made the data storage area SDA1-SDA4 and the pairing clear area SA1-SA4 thereof that will carry out data programing in this paging 101 by decision signal generation unit 303 indications, and generation control signal CS that can be corresponding is with the running of the designating unit in the control decision unit 305 309 with data supply unit 313.
In the present embodiment, decision package 305 comprises designating unit 309, arithmetic element 311, data supply unit 313, and selected cell 315.Wherein, designating unit 309 couples control module 307, the control signal CS that is produced in order to foundation control module 307, and corresponding 8 specification signal P[8:1 of generation].Wherein, because present embodiment only has data storage area SDA1 and pairing clear area SA1 thereof so a specification signal P[4:1 for what this paging 101 of hypothesis will be carried out data programing] state can finish to specification signal P4 by specification signal P1 begin the to continue state of keeping each 512 logical one.Afterwards, specification signal P[8:5] state just can finish to specification signal P8 by specification signal P5 begin the to continue state of keeping each 16 logical one.
Please continue again with reference to figure 1 and Fig. 3, when all data storage area SDA1-SDA4 in the paging 101 and the data of pairing clear area SA1-SA4 in regular turn behind the loaded respectively thereof, control module 307 can be assigned the order register of program command (10H) to Sheffer stroke gate type flash memory 301 inside, use tentation data and auxiliary data that data storage area SDA1 and clear area SA1 are loaded respectively and programme, and the obliterated data that data storage area SDA2-SDA4 and clear area SA2-SA4 are loaded is programmed.
Then, control module 307 is being assigned program command (10H) to the order register of Sheffer stroke gate type flash memory 301 inside, also can continue to detect the signal condition of the preparation/busy pin of the status register of Sheffer stroke gate type flash memory 301 inside, use when the signal condition of this preparation/busy pin is logical one, promptly represent tentation data and auxiliary data that data storage area SDA1 and clear area SA1 are loaded respectively, and the obliterated data that loaded of data storage area SDA2-SDA4 and clear area SA2-SA4 has been programmed and has been finished.
Then, when the signal condition that detects the preparation of the status register of Sheffer stroke gate type flash memory 301 inside/busy pin when control module 307 is logical one, it also can detect the signal condition of passing through/fail pin of the status register of Sheffer stroke gate type flash memory 301 inside, use when this signal condition by/failure pin when being logical zero, promptly represent paging 101 success of having programmed.Otherwise, the data programing that control module 307 can be carried out again paging 101 again.
So as can be known according to above-mentioned disclosed content, under the condition of the programmed method of the Sheffer stroke gate type flash memory of present embodiment and device memory capacity of all data storage area SDA1-SDA4 in the discontented paging 101 of institute's data programmed amount once, the data storage area SDA1 and the pairing clear area SA1 thereof that will carry out data programing in the paging 101 are loaded tentation data and auxiliary data respectively, and data storage area SDA2-SDA4 and the pairing clear area SA2-SA4 thereof that does not carry out data programing in the paging 101 loaded obliterated data.
Therefore, the programmed method of the Sheffer stroke gate type flash memory of present embodiment can carry out in the time of a data programing at Sheffer stroke gate type flash memory with device, can finish carrying out the data storage area SDA1 of data programing and the data programing of pairing clear area SA1 thereof in the paging 101, and be different from the settling mode that prior art proposes, so the programmed method of the Sheffer stroke gate type flash memory of present embodiment can reduce the data programing time of each paging with device, and then accelerate Sheffer stroke gate type flash memory overall data program speed.
Yet, spirit according to the desire elaboration of the invention described above institute, below will reintroduce a kind of read method of Sheffer stroke gate type flash memory, it can reduce the number of times that data read is carried out in interior each paging of Sheffer stroke gate type flash memory, can promote the fiduciary level that reads the interior stored data of each paging in the Sheffer stroke gate type flash memory simultaneously.
Fig. 4 shows the read method process flow diagram of the Sheffer stroke gate type flash memory of one embodiment of the invention.Please merge with reference to figure 1 and Fig. 4, the read method of the Sheffer stroke gate type flash memory of present embodiment is that 2Kbytes+64bytes/page is that example illustrates with paging 101 size specifications equally, but not as limit.The read method of the Sheffer stroke gate type flash memory of present embodiment comprises the following steps: at first, as described in step S401, when a paging 101 in the inner block of Sheffer stroke gate type flash memory will be carried out data read, determine to carry out k data storage area of data read in this paging 101 and distinguish a pairing k clear area.
In the present embodiment, before paging 101 will be carried out data read, must assign the order register (command register) of reading order (being generally the digital value of 00H) by the reading software of Sheffer stroke gate type flash memory earlier, use notice Sheffer stroke gate type flash memory and will carry out data read the paging 101 of its inside to Sheffer stroke gate type flash memory inside.
In addition, in step S401, determine to carry out k data storage area of data read in the paging 101 and distinguish a pairing k clear area, it for example can specify the start address of the data storage area SDA1-SDA4 and the pairing clear area SA1-SA4 thereof that will carry out data read in this paging 101, can determine data storage area and the clear area that will carry out data read in this paging 101 by this.And thus, the reading software of Sheffer stroke gate type flash memory can judge in regular turn just whether the start address of each data storage area SDA1-SDA4 in this paging 101 and pairing clear area SA1-SA4 thereof is designated, and if designated, promptly represent it will carry out the data storage area and the clear area of data read in paging 101 for this reason.And for convenience of description, that supposes that this paging 101 will carry out data programing only has data storage area SDA1 and a pairing clear area SA1 thereof, but is not limited to this.
Then, because when Sheffer stroke gate type flash memory is carried out data programing (program) or reads (read), it must be a unit with a paging, and data programing or the mode of operation that reads must be programmed in regular turn/read to again till last clear area SA4 from first data storage area SDA1 in the paging 101.Therefore, behind step S401, the read method of the Sheffer stroke gate type flash memory of present embodiment can continue as described in the step S403, and the 1st data storage area SDA1 in the paging 101 begins to carry out data read operation thus in regular turn, till the 4th clear area SA4.Wherein, this data read operation flow process comprises: stored tentation data in the SDA1 of reading of data storage area, and read corresponding to stored auxiliary data in the clear area SA1 of this tentation data; In addition, do not read remaining data storage area SDA2-SDA4 and clear area SA2-SA4 interior stored respectively tentation data and auxiliary data in this paging 101.
In the present embodiment, after the reading software of Sheffer stroke gate type flash memory has been judged the data storage area SDA1 and pairing clear area SA1 thereof that will carry out data read in the paging 101, the reading software of Sheffer stroke gate type flash memory also can be assigned to read and confirm the order register of order (being generally the digital value of 30H) to Sheffer stroke gate type flash memory inside, and through (that is the reading software of Sheffer stroke gate type flash memory detects the preparation/busy pin (ready/busy of the status register (status register) of Sheffer stroke gate type flash memory inside behind one section waiting time, R/B) signal condition is a logical one institute elapsed time by the logical zero transition), just can begin the data storage area SDA1 and the pairing clear area SA1 thereof that will carry out data read in the paging 101 are carried out data read operation.
In addition, the reading software of Sheffer stroke gate type flash memory also can continue to detect the signal condition of the preparation/busy pin of the status register of Sheffer stroke gate type flash memory inside, uses to judge described first paging whether data read finishes.Wherein, when signal condition of this preparation/busy pin is logical one, promptly represent this paging 101 data read finish, the reading software of Sheffer stroke gate type flash memory can be carried out data read to another paging by this.
So as can be known according to above-mentioned disclosed content, under the condition of the read method of the Sheffer stroke gate type flash memory of present embodiment memory capacity of all data storage area SDA1-SDA4 in the discontented paging 101 of the data volume that is once read, only read institute stores respectively in the data storage area SDA1 that will carry out data read in the paging 101 and the pairing clear area SA1 thereof tentation data and auxiliary data, and do not read in the data storage area SDA2-SDA4 that do not carry out data read in the paging 101 and the pairing clear area SA2-A4 thereof the tentation data and the auxiliary data of storage respectively.
Therefore, the read method of the Sheffer stroke gate type flash memory of present embodiment can carry out in the time of a data read at Sheffer stroke gate type flash memory, read out in the data storage area that will carry out data read in the paging and the pairing clear area thereof the tentation data and the auxiliary data that store respectively, can rise so read the fiduciary level of the stored data of each data storage area in the paging, and can also judge the block of Sheffer stroke gate type flash memory internal damage.Moreover, because the data read number of times of each paging only is 1 time, so can reduce Sheffer stroke gate type flash memory overall data reading times.
In sum, the programmed method and the device of Sheffer stroke gate type flash memory proposed by the invention, under the condition of its memory capacity of all data storage area in the discontented paging of institute's data programmed amount once, realize the data programing time of each paging of reduction, and then accelerate Sheffer stroke gate type flash memory overall data program speed.Moreover, the read method of Sheffer stroke gate type flash memory proposed by the invention, under the condition of its memory capacity of all data storage area in the discontented paging of the data volume that is once read, realize reducing the data read number of times of paging, and then reduce Sheffer stroke gate type flash memory overall data reading times.
Though the present invention discloses as above with preferred embodiment; but it is not in order to qualification the present invention, those skilled in the art, under the premise without departing from the spirit and scope of the present invention; can do some changes and modification, so protection scope of the present invention should be as the criterion with claim of the present invention.
Claims (16)
1. the programmed method of a Sheffer stroke gate type flash memory, wherein this Sheffer stroke gate type flash memory includes the identical paging of a plurality of memory capacity, and each paging inside has a n data storage area and the pairing n of a difference clear area thereof, wherein the start address of (i+1) individual data storage area continues in the end address of i data storage area, the start address of (i+1) individual clear area and continue in the end address of i clear area, and n is the positive integer more than or equal to 2, i is the positive integer less than n, the start address of the 1st clear area in this n clear area end address of n data storage area of continuing in addition, this programmed method comprises the following steps:
When one first paging in the described paging will be carried out data programing, determine will carry out k data storage area of data programing in this first paging and distinguish a pairing k clear area, wherein k is the positive integer that is not more than n;
Begun to carry out a data loading operations by the 1st data storage area in this first paging in regular turn, till n clear area, wherein this data loading operations flow process comprises:
Load a tentation data to this k data storage area, and load a auxiliary data corresponding to this tentation data to this k clear area; And
Load an obliterated data remaining (n-k) individual data storage area and (n-k) individual clear area to this first paging; And
This tentation data and this auxiliary data that this k data storage area and this k clear area are loaded are respectively programmed, and will be somebody's turn to do (n-k) individual data storage area and should (n-k) this obliterated data that individual clear area loaded programme.
2. the programmed method of Sheffer stroke gate type flash memory as claimed in claim 1 is wherein worked as this first paging and will be carried out before the data programing, and is further comprising the steps of:
Assign the order register of a continuous data input command, use and notify this Sheffer stroke gate type flash memory to carry out data programing this first paging of its inside to this Sheffer stroke gate type flash memory inside.
3. the programmed method of Sheffer stroke gate type flash memory as claimed in claim 1, wherein determine will to carry out this k data storage area of data programing in this first paging and the step of pairing respectively this k clear area comprises:
Whether the start address of judging each data storage area in this first paging and pairing clear area thereof in regular turn is designated, if designated, promptly be data storage area and the clear area that will carry out data programing in this first paging.
4. the programmed method of Sheffer stroke gate type flash memory as claimed in claim 1, further comprising the steps of:
After this data loading operations is finished in this first paging, assign the order register of a program command to this Sheffer stroke gate type flash memory inside, use this tentation data and this auxiliary data that make this k data storage area and this k clear area be loaded respectively and begin to programme, and make should (n-k) individual data storage area with should (n-k) this obliterated data that individual clear area loaded begin to programme.
5. the programmed method of Sheffer stroke gate type flash memory as claimed in claim 4, further comprising the steps of:
When this program command is assigned to this order register, detect the signal condition of a preparation/pin of having much to do of a status register of this Sheffer stroke gate type flash memory inside, use and judge this k data storage area and this k this tentation data and this auxiliary data that the clear area is loaded respectively, and be somebody's turn to do (n-k) individual data storage area and this (n-k) this obliterated data that individual clear area loaded and whether programme and finish;
Wherein, when being logical one as if the signal condition that detects this preparation/busy pin, represent this k data storage area and this k this tentation data and this auxiliary data that the clear area is loaded respectively, and should (n-k) individual data storage area finish with should (n-k) this obliterated data that individual clear area loaded having programmed.
6. the programmed method of Sheffer stroke gate type flash memory as claimed in claim 5, further comprising the steps of:
When this k data storage area and this k this tentation data and this auxiliary data that the clear area is loaded respectively, and should (n-k) individual data storage area with should (n-k) this obliterated data that individual clear area loaded have programmed finish after, detect a signal condition by/failure pin of this status register, to judge this first paging success of whether programming;
Wherein, if detect this signal condition by/failure pin when being logical zero, represent this first paging success of having programmed.
7. the read method of a Sheffer stroke gate type flash memory, wherein this Sheffer stroke gate type flash memory includes the identical paging of a plurality of memory capacity, and each paging inside has a n data storage area and the pairing n of a difference clear area thereof, wherein the start address of (i+1) individual data storage area continues in the end address of i data storage area, the start address of (i+1) individual clear area and continue in the end address of i clear area, and n is the positive integer more than or equal to 2, i is the positive integer less than n, the start address of the 1st clear area in this n clear area end address of n data storage area of continuing in addition, this read method comprises the following steps:
When one first paging in the described paging will be carried out data read, determine will carry out k data storage area of data read in this first paging and distinguish a pairing k clear area, wherein k is the positive integer that is not more than n; And
Begun to carry out a data read operation by the 1st data storage area in this first paging in regular turn, till n clear area, wherein this data read operation flow process comprises:
Read a stored tentation data in this k the data storage area, and read corresponding to a stored auxiliary data in this k clear area of this tentation data; And
Do not read remaining (n-k) individual data storage area in this first paging and (n-k) distinguish stored this tentation data and this auxiliary data in the individual clear area.
8. the read method of Sheffer stroke gate type flash memory as claimed in claim 7, further comprising the steps of:
Before this first paging will be carried out data read, assign the order register of a reading order to this Sheffer stroke gate type flash memory inside, use and notify this Sheffer stroke gate type flash memory to carry out data read this first paging of its inside.
9. the read method of Sheffer stroke gate type flash memory as claimed in claim 7, wherein determine will to carry out this k data storage area of data read in this first paging and the step of pairing respectively this k clear area comprises:
Whether the start address of judging each data storage area in this first paging and pairing clear area thereof in regular turn is designated, if designated, promptly be data storage area and the clear area that will carry out data read in this first paging.
10. the read method of Sheffer stroke gate type flash memory as claimed in claim 7, further comprising the steps of:
After in definite this first paging, will carrying out this k data storage area of data read and distinguishing pairing this k clear area, assign one and read this order register of confirming to order to this Sheffer stroke gate type flash memory inside, and after during the wait, begin this data read operation is carried out in this first paging.
11. the read method of Sheffer stroke gate type flash memory as claimed in claim 7 is further comprising the steps of:
After this data read operation is finished in this first paging, detect the signal condition of a preparation/busy pin of a status register of this Sheffer stroke gate type flash memory inside, use and judge whether this first paging reads and finish;
Wherein, when being logical one, representing this first paging to read and finish as if the signal condition that detects this preparation/busy pin.
12. the programmer of a Sheffer stroke gate type flash memory, wherein this Sheffer stroke gate type flash memory comprises the identical paging of a plurality of memory capacity, and each paging inside has a n data storage area and the pairing n of a difference clear area thereof, wherein the start address of (i+1) individual data storage area continues in the end address of i data storage area, the start address of (i+1) individual clear area and continue in the end address of i clear area, and n is the positive integer more than or equal to 2, i is the positive integer less than n, the start address of the 1st clear area in this n clear area end address of n data storage area of continuing in addition, this programmer comprises:
One decision signal generation unit is used for producing a decision signal, will carry out k data storage area of data programing and distinguish a pairing k clear area to determine one first paging in the described paging, and wherein k is the positive integer that is not more than n;
One decision package, couple this decision signal generation unit, in order to according to this decision signal and a control signal, begin to carry out a data loading operations by the 1st data storage area in this first paging in regular turn, till n clear area, wherein this data loading operations for load a tentation data this k data storage area, in the auxiliary data of this k clear area loading corresponding to this tentation data, and in this first paging remaining (n-k) individual data storage area and (n-k) individual clear area load an obliterated data; And
One control module, couple this Sheffer stroke gate type flash memory, this decision signal generation unit and this decision package, in order to this control signal to be provided and to assign the order register of a program command to this Sheffer stroke gate type flash memory inside, use this tentation data and this auxiliary data that this k data storage area and this k clear area are loaded respectively and programme, and will be somebody's turn to do (n-k) individual data storage area and should (n-k) this obliterated data that individual clear area loaded programme;
Wherein, this control module produces this control signal according to the state of this decision signal.
13. the programmer of Sheffer stroke gate type flash memory as claimed in claim 12, wherein before this first paging will be carried out data programing, this control module is also assigned a continuous data input command to this order register, uses and notifies this Sheffer stroke gate type flash memory to carry out data programing to this first paging of its inside.
14. the programmer of Sheffer stroke gate type flash memory as claimed in claim 12, wherein this decision package comprises:
One designating unit couples this control module, in order to according to this control signal, and produces a specification signal accordingly;
One arithmetic element couples this decision signal generation unit and this designating unit, in order to according to this decision signal and this specification signal, selects signal and produce one;
One data supply unit couples this control module, in order to according to this control signal, and corresponding this tentation data of generation, this auxiliary data and this obliterated data; And
One selected cell, couple this arithmetic element and this data supply unit, in order to select signal according to this, and provide this tentation data to load, provide this auxiliary data to load, and provide this obliterated data to load to this (n-k) individual data storage area and this (n-k) individual clear area to this k clear area corresponding to this tentation data to this k data storage area.
15. the programmer of Sheffer stroke gate type flash memory as claimed in claim 12, wherein this control module is being assigned this program command to this order register, also detect the signal condition of a preparation/pin of having much to do of a status register of this Sheffer stroke gate type flash memory inside, use and judge this k data storage area and this k this tentation data and this auxiliary data that the clear area is loaded respectively, and be somebody's turn to do (n-k) individual data storage area and this (n-k) this obliterated data that individual clear area loaded and whether programmed and finish;
Wherein, if this control module detects the signal condition of this preparation/pin of having much to do when being logical one, represent this k data storage area and this k this tentation data and this auxiliary data that the clear area is loaded respectively, and should (n-k) individual data storage area finish with should (n-k) this obliterated data that individual clear area loaded having programmed.
16. the programmer of Sheffer stroke gate type flash memory as claimed in claim 15, wherein when this k data storage area and this k this tentation data and this auxiliary data that the clear area is loaded respectively, and should (n-k) individual data storage area with should (n-k) this obliterated data that individual clear area loaded have programmed finish after, this control module also detects a signal condition by/failure pin of this status register, uses and judges this first paging success of whether programming;
Wherein, if this control module detects this signal condition by/failure pin when being logical zero, represent this first paging success of having programmed.
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| CN1754230A (en) * | 2003-01-28 | 2006-03-29 | 桑迪士克股份有限公司 | Non-volatile semiconductor memory with large erase blocks storing cycle counts |
| CN1933024A (en) * | 2005-09-15 | 2007-03-21 | 海力士半导体有限公司 | Method for operating flash memory chips |
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| CN1754230A (en) * | 2003-01-28 | 2006-03-29 | 桑迪士克股份有限公司 | Non-volatile semiconductor memory with large erase blocks storing cycle counts |
| CN1933024A (en) * | 2005-09-15 | 2007-03-21 | 海力士半导体有限公司 | Method for operating flash memory chips |
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