CN101378513B - Circuit for processing high gain analog signals - Google Patents
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Abstract
The invention provides a high-gain analog signal processing circuit which comprises amplifying circuits. The amplifying circuit comprises a difference calculation amplifier provided with a positive input end, a negative input end, a positive output end and a negative output end, and a positive input-stage capacitance array, a negative input-stage capacitance array, a positive output-stage capacitance array and a negative output-stage capacitance array which are provided with input ends and output ends. The circuit comprises a plurality of amplifying circuits; the positive output end of each amplifying circuit is connected to the input end of the negative input-stage capacitance array of the next amplifying circuit, while the negative output end is connected to the input end of the positive input-stage capacitance array of the next amplifying circuit; the phases of clock signals adopted by two adjacent amplifying circuits are opposite to each other. By adopting the high-gain analog signal processing circuit provided by the invention, high gain can be realized fast and the requirements of high-precision CMOS image sensor can be better met.
Description
Technical field
The present invention relates to analog signal processing circuit, relate in particular to a kind of circuit for processing high gain analog signals.
Background technology
In today that microelectric technique and image processing techniques develop rapidly, cmos image sensor (1.2V～5V), rate of finished products height, can become research, hot of research and development to advantages such as local pixel random accesss with its low cost, low-power consumption, single supply, low-work voltage, develop extremely rapidly, occupied low, middle resolution field at present.
The basic means that cmos image sensor adopts photo-sensitive cell to catch as image, the core of its photo-sensitive cell is a photodiode (photodiode), this diode can produce output current after accepting irradiate light, current's intensity is then corresponding with the intensity of illumination, so the signal of telecommunication that photo-sensitive cell is directly exported is simulated.After light sensitive diode was accepted the signal of telecommunication of illumination, generation simulation, the signal of telecommunication was at first amplified by the amplifier in this photo-sensitive cell, is directly changed into corresponding digital signal then.Each photo-sensitive cell all can produce final numeral output, is directly delivered dsp chip after the gained digital signal merges and handles.
For the picture tone that cmos image sensor taken come is true to nature, can correctly reflect the true colors of scenery, to carry out usually that color gain is regulated and the entire gain adjusting in the analog signal field of imageing sensor.
CN1992788A discloses a kind of amplifying circuit that is used for cmos image sensor, the single-ended signal that this circuit adopts the difference transport and placing device to come out from image sensor array converts the differential signal input a/d converter to, and has realized the function of color gain control and entire gain control.
Along with the development of cmos image sensor, more and more higher to the required precision of image, thus the size of single pixel is more and more littler, and to littler development.The size decreases of pixel makes the photosensitive region of pixel diminish, thereby causes the light sensitive diode light in the pixel to convert the sensitivity reduction of electricity to, so needs the gain of raising analog signal processing circuit.
The amplification circuit structure of above mentioning is single, and gain is not enough, can not satisfy the demand of present many high precision CMOS imageing sensors, thereby make that the imageing sensor shooting effect is undesirable.
Summary of the invention
Main purpose of the present invention is in order to solve the not enough problem of cmos image sensor gain, a kind of circuit for processing high gain analog signals that is used for the high precision CMOS imageing sensor to be provided.
The present inventor considers and a plurality of amplifying circuit cascades can be realized multistage amplification that total multiplication factor is the product of each grade multiplication factor, can realize high-gain.If simply with a plurality of amplifying circuit cascades, each amplifying circuit all can have half clock cycle to be in the common mode electrical level state after the amplification of carrying out analog signal, promptly do not carry out amplification work, therefore the present inventor considers and can provide different clocks to amplifying circuit, it is the inversion clock that each amplifying circuit adopts an amplifying circuit, therefore the work that all can have amplifying circuit to amplify in per half clock cycle of clock, realized the streamline amplification, the speed that reaches high-gain like this is very fast.
Circuit for processing high gain analog signals provided by the invention comprises amplifying circuit, this amplifying circuit comprises the difference transport and placing device, positive input level capacitor array, negative input stage capacitor array, positive output level capacitor array and negative output level capacitor array, described positive input level capacitor array, negative input stage capacitor array, positive output level capacitor array and negative output level capacitor array have input and output, described difference transport and placing device has the input anode, the input negative terminal, output plus terminal and output negative terminal, the input of described positive input level capacitor array is used to import analog picture signal, output is connected to the input anode of difference transport and placing device, the input of described negative input stage capacitor array is used to import reference level signal, output is connected to the input negative terminal of difference transport and placing device, the input of described positive output level capacitor array links to each other with the input negative terminal of the output of negative input stage capacitor array and difference transport and placing device, output links to each other with the output plus terminal of difference transport and placing device, the input of described negative output level capacitor array links to each other with the output of positive input level capacitor array and the input anode of difference transport and placing device, output links to each other with the output negative terminal of difference transport and placing device, described amplifying circuit is a plurality of, the output plus terminal of each amplifying circuit is connected to the input of the negative input stage capacitor array of next amplifying circuit, the output negative terminal is connected to the input of the positive input level capacitor array of next amplifying circuit, and the clock signal phase that adjacent two amplifying circuits adopt is opposite.
Adopt circuit for processing high gain analog signals provided by the invention the analog signal of input can be carried out many times of amplifications.Gain promptly is a multiplication factor, according to the gain calculating formula, in the amplifying circuit behind a plurality of cascades, the total multiplication factor that obtains from last amplifying circuit is the product of each grade multiplication factor, therefore than amplifying circuit of available technology adopting, multiplication factor is only high for one-level, thereby can realize high-gain.And each amplifying circuit adopts the reverse clock of a last amplifying circuit, be that each amplifying circuit all carries out amplification work in half clock cycle that a last amplifying circuit is in the common mode electrical level state, thereby guarantee that each whole clock cycle has two amplifying circuits to carry out amplification work in amplification process, have only an amplifying circuit to carry out amplification work than each whole clock cycle in the prior art and reach high-gain sooner.Therefore, adopt circuit for processing high gain analog signals provided by the invention can satisfy the demand of high precision CMOS imageing sensor better.
Description of drawings
Fig. 1 is the circuit block diagram of a kind of embodiment provided by the invention.
Embodiment
Circuit for processing high gain analog signals provided by the invention comprises amplifying circuit, this amplifying circuit comprises the difference transport and placing device, positive input level capacitor array, negative input stage capacitor array, positive output level capacitor array and negative output level capacitor array, described positive input level capacitor array, negative input stage capacitor array, positive output level capacitor array and negative output level capacitor array have input and output, described difference transport and placing device has the input anode, the input negative terminal, output plus terminal and output negative terminal, the input of described positive input level capacitor array is used to import analog picture signal, output is connected to the input anode of difference transport and placing device, the input of described negative input stage capacitor array is used to import reference level signal, output is connected to the input negative terminal of difference transport and placing device, the input of described positive output level capacitor array links to each other with the input negative terminal of the output of negative input stage capacitor array and difference transport and placing device, output links to each other with the output plus terminal of difference transport and placing device, the input of described negative output level capacitor array links to each other with the output of positive input level capacitor array and the input anode of difference transport and placing device, output links to each other with the output negative terminal of difference transport and placing device, described amplifying circuit is a plurality of, the output plus terminal of each amplifying circuit is connected to the input of the negative input stage capacitor array of next amplifying circuit, the output negative terminal is connected to the input of the positive input level capacitor array of next amplifying circuit, and the clock signal phase that adjacent two amplifying circuits adopt is opposite.
Realize that the anti-phase mode of clock signal that adjacent two amplifying circuits adopt can adopt any existing mode, for example, in circuit provided by the invention, introduce clock generator and time-delay mechanism.Described clock generator can be the clock generator of cmos image treatment system, clock generator by the cmos image treatment system provides required clock signal for amplifying circuit, the also clock generator that can carry for difference transport and placing device in the amplifying circuit, under the preferable case, adopt the clock generator of cmos image treatment system.Therefore, described circuit can also comprise clock generator and time-delay mechanism, described difference transport and placing device also has clock signal input terminal, described clock generator is connected with the clock signal input terminal of the difference transport and placing device of every odd number amplifying circuit, be used to every odd number amplifying circuit that clock signal is provided, described clock generator is connected to the clock signal input terminal of the difference transport and placing device of every even number amplifying circuit by time-delay mechanism, is used to adjacent two amplifying circuits that anti-phase clock signal is provided; Perhaps, described clock generator is connected with the clock signal input terminal of the difference transport and placing device of every even number amplifying circuit, be used to every even number amplifying circuit that clock signal is provided, described clock generator is connected to the clock signal input terminal of the difference transport and placing device of every odd number amplifying circuit by time-delay mechanism, is used to adjacent two amplifying circuits that anti-phase clock signal is provided.
Described clock generator mainly is responsible for producing the clock signal relevant with system works.The clock signal that clock generator provides is a consecutive pulses signal, and pulse each time arrives, and the device of received signal just changes a next state, finishes certain task.The cmos image treatment system adopts clock generator to be connected with each module in the system, described clock generator produces vibration by crystal oscillator, frequency division provides required multiple clock signal for each module in the system then, amplifying circuit is connected with clock generator equally, the clock signal that adopts clock generator to provide is once amplified work half clock cycle.Described clock generator is for producing the device of pulse signal, for example trigger or oscillator.
Described time-delay mechanism be can the clock cycle is anti-phase device, inverter for example.Inverter changes the clock cycle by high level state and low level state are reversed.For example, clock generator provides the consecutive pulses signal, the half period is a high level state before making in a clock cycle, the later half cycle is a low level state, inverter by with being connected of clock generator, can moment high level state be reversed to low level state, and low level state is reversed to high level state, thereby with moment clock cycle anti-phase, therefore adopt the time of inversion clock signal execution work will be than late half clock cycle of time of adopting the original clock signal execution work.Providing of clock signal will be described in detail hereinafter.
In described a plurality of amplifying circuit at least one also comprises the gain control signal end, described positive input level capacitor array, negative input stage capacitor array, positive output level capacitor array and negative output level capacitor array also have control end, and described control end links to each other with the gain control signal end.
After amplifying, be directly inputted into the A/D converter of cmos image sensor from the analog picture signal of cmos image sensor array output, handle again so that analog picture signal is converted to digital signal through a plurality of amplifying circuits.Because the A/D converter of cmos image sensor belongs to high-speed ADC, need to adopt the differential signal input, and the analog picture signal of exporting all is single-ended from the cmos image sensor array.Therefore, difference transport and placing device provided by the invention is the fully differential transport and placing device, and the characteristic of fully differential amplifier is to realize difference input and difference output.The single-ended analog picture signal V that therefore, will from image sensor array, export
InInput to the positive input level capacitor array of first amplifying circuit, with a reference level signal V
RefInput to the negative input stage capacitor array of first amplifying circuit, import as difference with this.According to the characteristic of fully differential amplifier, realized the conversion of single-ended signal, and compared single-ended work that differential work has stronger antijamming capability to ambient noise, can suppress the dynamic noise of imager chip preferably to differential signal.
The cmos image processor is realized gain-adjusted from gain control signal end outputing gain control signal by the size that changes described amplifying circuit input stage and output stage electric capacity.Cmos image sensor uses bus system to come control capacitance, all has a plurality of electric capacity to link to each other with bus by switching circuit in each capacitor array, by the part in a plurality of electric capacity of indication selection connection of gain control signal, to reach the purpose that changes gain.
Difference transport and placing device provided by the present invention and positive and negative input, positive and negative output stage capacitor array are conventionally known to one of skill in the art, no longer do detailed description at this.
In the cmos image sensor field, described gain controlling is color gain control and entire gain control.In order correctly to reflect the true colors of captured scenery, can regulate color gain and entire gain respectively.Adjusting to gain will be described in more detail below.
Owing to need generally in the rear end data image signal is handled to determine that the black background value is to guarantee picture contrast, therefore last amplifying circuit also comprises just adjusting black background electric capacity and the negative black background electric capacity of regulating with input, output and control end in described a plurality of amplifying circuits, the described input of just regulating black background electric capacity is used to import first offset voltage, and output is connected to the input anode of the difference transport and placing device of last amplifying circuit in described a plurality of amplifying circuit; The input of described negative adjusting black background electric capacity is used to import second offset voltage, and output is connected to the input negative terminal of the difference transport and placing device of last amplifying circuit in described a plurality of amplifying circuit; The described black background electric capacity of just regulating links to each other with the gain control signal end with the negative control end of regulating black background electric capacity.Described black background control will be described in detail hereinafter.
Below so that two amplifying circuit cascades are described the present invention as a kind of embodiment.Fig. 1 is the circuit block diagram of embodiment provided by the invention.
As shown in Figure 1, circuit for processing high gain analog signals provided by the invention comprises first amplifying circuit and second amplifying circuit, described first amplifying circuit comprises first order difference transport and placing device op1, is used for single-ended analog picture signal is converted to the differential signal output of amplification; Described first amplifying circuit also comprises the first positive input level capacitor array c1, the first negative input stage capacitor array c3, the first positive output level capacitor array c4 and the first negative output level capacitor array c2; The input of the first positive input level capacitor array c1 is used to import analog picture signal V
In, output is connected to first order difference transport and placing device input anode inp1; The input of the described first negative input stage capacitor array c3 is used to import reference level signal V
Ref, output is connected to first order difference transport and placing device input negative terminal inn1, and the control end of the described first positive input level capacitor array c1 and the first negative input stage capacitor array c3 all links to each other with the first color gain control signal end a; Described first defeated bear out a grade electric capacity c2 and is connected between first order difference transport and placing device output out_ and the input inp1, the described first positive output level capacitor array c4 is connected between first order difference transport and placing device output out and the input inn1, and the control end of the first negative output level capacitor array c2 and the first positive output level capacitor array c4 all links to each other with the second color gain control signal end b.
Described second amplifying circuit comprises second level difference transport and placing device op2, is used for that the differential signal from first order difference transport and placing device op1 output is carried out the second time and amplifies; Described second amplifying circuit also comprises the second positive input level capacitor array c5, the second negative input stage capacitor array c7, the second positive output level capacitor array c8 and the second negative output level capacitor array c6; The input of the described second positive input level capacitor array c5 is connected to first order difference transport and placing device output negative terminal out_, and control end links to each other with the first entire gain control signal end c, and output is connected to the input anode inp2 of second level difference transport and placing device; The input of the described second negative input stage capacitor array c7 is connected to first order difference transport and placing device output plus terminal out, and control end links to each other with the first entire gain control signal end c, and output is connected to second level difference transport and placing device input negative terminal inn2; The described second negative output level capacitor array c6 is connected between second level difference transport and placing device output outn and the input inp2, the described second positive output level capacitor array c8 is connected between second level difference transport and placing device output outp and the input inn2, and control end links to each other with the second entire gain control signal end d.
In order to guarantee to handle the black background value of image, circuit for processing high gain analog signals provided by the invention also comprises just adjusting black background electric capacity c9 and the negative black background electric capacity c10 that regulates with input, output and control end, and the described input of just regulating black background electric capacity c9 is used to import the first offset voltage V
Ofp, output is connected in second level difference transport and placing device input anode inp2; The input of described negative adjusting black background electric capacity c10 is used to import the second offset voltage V
Ofn, output is connected to second level difference transport and placing device input negative terminal inn2, and the offset voltage value that then is used to regulate black background is: V
Offset=(V
Ofp-V
Ofn) * C
10/ C
8Or V
Offset=(V
Ofp-V
Ofn) * C
9/ C
6
Adopt two fully differential transport and placing devices in the present embodiment, the end of first order difference transport and placing device op1 is used for the signal V that the input picture sensor front end is exported
In, the other end is used to import fixing reference level V
RefAccording to the characteristic of fully differential amplifier, can realize the conversion of single-ended signal to differential signal.
In order to reach high-gain faster, circuit for processing high gain analog signals provided by the invention also comprises clock generator 1 and time-delay mechanism 2, described difference transport and placing device also comprises clock signal input terminal in, described clock generator 1 is connected with the clock signal input terminal in of the difference transport and placing device op1 of first amplifying circuit, be used to first amplifying circuit that clock signal is provided, described clock generator 1 is connected to the clock signal input terminal in of the difference transport and placing device op2 of second amplifying circuit by time-delay mechanism 2, is used to two amplifying circuits that anti-phase clock signal is provided.
Described first amplifying circuit receives the clock signal from clock generator 1, is in the common mode electrical level state at the positive half period of clock, realizes enlarging function at the negative half-cycle of clock.At the positive half period of clock, the analog picture signal after the input of the described first positive input level capacitor array c1 input exposure, this moment, the positive negative output of first order difference transport and placing device op1 was in the common mode electrical level state; Negative half-cycle at clock, analog picture signal before the input input exposure of the described first positive input level capacitor array c1, this moment, first order difference transport and placing device op1 realized enlarging function, analog picture signal before the amplification exposure and the difference (signal of presentation video signal magnitude) between the analog picture signal after the exposure, the realization first order is amplified, and the differential wave after will amplifying inputs to second level difference transport and placing device op2; When the clock positive half period arrived once more, the positive-negative output end of described first order difference transport and placing device op1 recovered the common mode electrical level state.
Described second amplifying circuit receives from clock generator 1 and through the clock signal of time-delay mechanism 2, and is therefore anti-phase with the first amplifying circuit clock signal, realizes enlarging function at the positive half period of clock, is in the common mode electrical level state at the negative half-cycle of clock.Negative half-cycle at clock, the positive-negative output end of second level difference transport and placing device op2 is in the common mode electrical level state, positive half period at clock, described second level difference transport and placing device op2 amplifies through differential wave after the first order amplification and the difference between the common mode electrical level, realize the second level amplification of signal, when the clock negative half-cycle arrived once more, the output of described second level difference transport and placing device op2 was in the common mode electrical level state once more.Therefore as can be seen, described first order difference transport and placing device op1 and second level difference transport and placing device op2 can realize the continuous amplification to signal in a complete clock cycle, realize that promptly streamline amplifies; Two difference transport and placing devices of streamline amplification ratio that second level difference transport and placing device op2 adopts the inversion clock of first order difference transport and placing device op1 to carry out adopt easier the reaching at a high speed of twice amplification of same clock.The multiplication factor that total like this multiplication factor equals the first order multiply by partial multiplication factor, is easy to reach high-gain.
According to the characteristic of switching capacity amplifying circuit, the analog picture signal before analog picture signal after the exposure and the exposure is taken a sample respectively, subtract each other the signal that obtains representing this picture signal size then.At the positive half period of clock, described first order difference transport and placing device op1 positive-negative output end is output common mode level V all
Cm, from the input input exposure back signal V of the first positive input level capacitor array c1
In1; At the negative half-cycle of clock, from the input input exposure front signal V of the first positive input level capacitor array c1
In2, and described first order difference transport and placing device op1 realization enlarging function, the difference of these two signals is amplified.Because the characteristic of difference input is from the input input reference level V of the first negative input stage capacitor array c3
Ref, then described difference is V
In1=(V
In2-V
Ref)-(V
In1-V
Ref)=V
In2-V
In1.The output-transfer function of first order difference transport and placing device op1 is:
V
out1＝V
out-V
out_＝V
in1*(C
in1/C
out1)
Wherein, V
OutBe the output plus terminal level signal of the first difference transport and placing device op1, V
Out_Be the output negative terminal level signal of the first difference transport and placing device op1, C
In1Be the total capacitance of first order difference transport and placing device op1 input, C
Out1Total capacitance for first order difference transport and placing device op2 output.
Second level difference transport and placing device op2 adopts the inversion clock of first order difference transport and placing device op1, and at the clock negative half-cycle, described second level difference transport and placing device op2 positive-negative output end is output common mode level V all
CmAt the positive half period of clock, described second level difference transport and placing device op2 realizes enlarging function, amplifies signal and common mode electrical level V after the first order is amplified
CmDifference, realize that amplify the second time of signal, do not consider to regulate the signal of black background input capacitance, then second level difference transport and placing device op2 positive and negative terminal output valve is:
V
outp-V
cm＝-(V
cm-V
out)*(C
in2/C
out2)
V
cm-V
outn＝(V
cm-V
out_)*(C
in2/C
out2)
Then partial output-transfer function is:
V
out2＝V
outp-V
outn＝-(V
cm-V
out)*(C
in2/C
out2)+V
cm+(V
cm-V
out_)*(C
in2/C
out2)-V
cm
＝(V
out-V
cm+V
cm-V
out_)*(C
in2/C
out2)＝(V
out-V
out_)*(C
in2/C
out2)
＝V
in1*(C
in1/C
out1)*(C
in2/C
out2)
Wherein, C
In2Be the total capacitance of second level difference transport and placing device op2 input, C
Out2Total capacitance for second level difference transport and placing device op2 output.
If consider to regulate the signal V of black background input capacitance
OfpAnd V
Ofn, then partial output-transfer function is:
V
out2＝V
in1*(C
in1/C
out1)*(C
in2/C
out2)+V
offset
As can be seen from the above equation, by regulating first order difference transport and placing device op1 input total capacitance C
In1, i.e. the capacitance of c1, c3, and output total capacitance C
Out1, i.e. the capacitance of c2, c4, or adjusting second level difference transport and placing device op2 input total capacitance C
In2, i.e. the capacitance of c5, c7, and output total capacitance C
Out2, promptly the capacitance of c6, c8 just can gain big or small by conditioning signal.
Color gain control:
So it is red in input by control color gain control signal, green, the different first order difference transport and placing device op1 first positive input level capacitor array c1 that constantly correspondingly regulate of blue different colours signal, the first negative input stage capacitor array c3, (output capacitance is at the denominator of gain formula for the first negative output level capacitor array c2 and the first positive output level capacitor array c4, improve gain, electric capacity is regulated to the direction that reduces), change the size of input and output capacitor value, just can regulate red respectively, green, the gain size of blue tristimulus signals, thereby realize color gain control, making color difference signal is zero.
Entire gain control (promptly changing the gain of red, green, blue color signal simultaneously):
In like manner, (output capacitance is at the denominator of gain formula to regulate the second positive input level capacitor array c5, the second negative input stage capacitor array c7, the second negative output terminal capacitor array c6 and the second positive input level capacitor array c8 of second level difference transport and placing device op2 by control entire gain control signal, improve gain, electric capacity is regulated to the direction that reduces), change the size of input and output capacitor value, just can regulate the entire gain size, make image meet the requirements of brightness, thereby realize entire gain control.
Black background control:
The offset voltage value of described adjusting black background is: V
Offset=(V
Ofp-V
Ofn) * C
10/ C
8Or V
Offset=(V
Ofp-V
Ofn) * C
9/ C
6, wherein, V
Ofp≠ V
OfnHere, C
10/ C
8Or C
9/ C
6Be necessary for a fixed value, therefore by regulating first and second offset voltage V
OfpAnd V
OfnLevel value, just can regulate V
OffsetSize, thereby realize the control of picture black background.To V
OfpAnd V
OfnAdjusting should make V
OffsetCan not be greater than amplifier maximum output voltage value and amplifier minimum output voltage value poor.
When regulating entire gain by the second positive output level capacitor array c8 and the second negative output level capacitor array c6, unaffected in order to guarantee the picture black background, i.e. V
OffsetConstant, C then
10With C
9The adjusting multiple must and C
8And C
6Unanimity could guarantee C
10/ C
8Or C
9/ C
6Be same fixed value.Therefore the described black background electric capacity c9 that just regulating also links to each other with entire gain signal controlling end d with the negative control end of regulating black background electric capacity c10, just regulating black background electric capacity c9 and negatively regulating black background electric capacity c10 regulating with identical multiple in ride gain, so that regulate the offset voltage V of black background by the entire gain Signal Regulation second positive output level capacitor array c8 and the second negative output level capacitor array c6
OffsetRemain unchanged, thereby guarantee that the picture black background is unaffected.
The present embodiment first order is amplified the control of realization color gain, and the control of realization entire gain is amplified in the second level and black background is controlled.By changing the connection of control signal, the first order is amplified can realize entire gain control, and control of realization color gain and black background control are amplified in the second level; Or the first order is amplified and the input capacitance control of second level amplification realizes the linear color gain controlling, and the output capacitance that the first order is amplified and amplify the second level is controlled and realized entire gain control; Or the input capacitance that the first order is amplified and amplify second level control realizes linear entire gain control, the output capacitance control color gain control that the first order is amplified and amplify the second level.
Claims (8)
1. circuit for processing high gain analog signals, described circuit comprises amplifying circuit, this amplifying circuit comprises difference transport and placing device, positive input level capacitor array, negative input stage capacitor array, positive output level capacitor array and negative output level capacitor array, described positive input level capacitor array, negative input stage capacitor array, positive output level capacitor array and negative output level capacitor array have input and output, and described difference transport and placing device has input anode, input negative terminal, output plus terminal and output negative terminal; The input of described positive input level capacitor array is used to import analog picture signal, and output is connected to the input anode of difference transport and placing device; The input of described negative input stage capacitor array is used to import reference level signal, and output is connected to the input negative terminal of difference transport and placing device; The input of described positive output level capacitor array links to each other with the input negative terminal of the output of negative input stage capacitor array and difference transport and placing device, and output links to each other with the output plus terminal of difference transport and placing device; The input of described negative output level capacitor array links to each other with the output of positive input level capacitor array and the input anode of difference transport and placing device, and output links to each other with the output negative terminal of difference transport and placing device; It is characterized in that, described amplifying circuit is a plurality of, the output plus terminal of the difference transport and placing device of each amplifying circuit is connected to the input of the negative input stage capacitor array of next amplifying circuit, the output negative terminal is connected to the input of the positive input level capacitor array of next amplifying circuit, and the clock signal phase that adjacent two amplifying circuits adopt is opposite.
2. circuit according to claim 1 is characterized in that described circuit also comprises clock generator and time-delay mechanism, and described difference transport and placing device also has clock signal input terminal; Described clock generator is connected with the clock signal input terminal of the difference transport and placing device of every odd number amplifying circuit, is used to every odd number amplifying circuit that clock signal is provided; Described clock generator is connected to the clock signal input terminal of the difference transport and placing device of every even number amplifying circuit by time-delay mechanism, is used to adjacent two amplifying circuits that anti-phase clock signal is provided; Perhaps,
Described clock generator is connected with the clock signal input terminal of the difference transport and placing device of every even number amplifying circuit, is used to every even number amplifying circuit that clock signal is provided; Described clock generator is connected to the clock signal input terminal of the difference transport and placing device of every odd number amplifying circuit by time-delay mechanism, is used to adjacent two amplifying circuits that anti-phase clock signal is provided.
3. circuit according to claim 2 is characterized in that, described clock generator is trigger or oscillator.
4. circuit according to claim 2 is characterized in that, described time-delay mechanism is an inverter.
5. circuit according to claim 1, it is characterized in that, last amplifying circuit comprises that also just regulating black background electric capacity regulates black background electric capacity with bearing in described a plurality of amplifying circuit, described each of just regulating in black background electric capacity and the described negative adjusting black background electric capacity all has input, output and control end, the described input of just regulating black background electric capacity is used to import first offset voltage, and output is connected to the input anode of the difference transport and placing device of last amplifying circuit in described a plurality of amplifying circuit; The input of described negative adjusting black background electric capacity is used to import second offset voltage, and output is connected to the input negative terminal of the difference transport and placing device of last amplifying circuit in described a plurality of amplifying circuit; The described black background electric capacity of just regulating links to each other with the gain control signal end with the negative control end of regulating black background electric capacity.
6. circuit according to claim 1 or 5, it is characterized in that, in described a plurality of amplifying circuit at least one also comprises the gain control signal end, described positive input level capacitor array, negative input stage capacitor array, positive output level capacitor array and negative output level capacitor array also have control end, and described control end links to each other with the gain control signal end.
7. circuit according to claim 6 is characterized in that, described gain control signal end is color gain control signal end and/or entire gain control signal end.
8. circuit according to claim 5, it is characterized in that, two amplifying circuits in described a plurality of amplifying circuit comprise the gain control signal end, and, the gain control signal end of an amplifying circuit is a color gain control signal end, and the gain control signal end of another amplifying circuit is an entire gain control signal end.
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| Application Number | Priority Date | Filing Date | Title |
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| CN2007101475934A CN101378513B (en) | 2007-08-28 | 2007-08-28 | Circuit for processing high gain analog signals |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN2007101475934A CN101378513B (en) | 2007-08-28 | 2007-08-28 | Circuit for processing high gain analog signals |
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| CN101378513A CN101378513A (en) | 2009-03-04 |
| CN101378513B true CN101378513B (en) | 2011-01-12 |
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| CN2007101475934A Expired - Fee Related CN101378513B (en) | 2007-08-28 | 2007-08-28 | Circuit for processing high gain analog signals |
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| CN112104811B (en) * | 2020-09-21 | 2021-06-29 | 中国科学院长春光学精密机械与物理研究所 | Low-latency multi-group imaging control system |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2002320146A (en) * | 2001-02-19 | 2002-10-31 | Innotech Corp | Variable gain amplifier, solid-state imaging device and method for reading optical signal |
| CN1671077A (en) * | 2004-03-15 | 2005-09-21 | 清华大学 | Image pickup and image transmission system for minitype aircraft |
| CN1992788A (en) * | 2005-12-29 | 2007-07-04 | 比亚迪股份有限公司 | Signal processing circuit of analog image for CMOS image sensor |
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2007
- 2007-08-28 CN CN2007101475934A patent/CN101378513B/en not_active Expired - Fee Related
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2002320146A (en) * | 2001-02-19 | 2002-10-31 | Innotech Corp | Variable gain amplifier, solid-state imaging device and method for reading optical signal |
| CN1671077A (en) * | 2004-03-15 | 2005-09-21 | 清华大学 | Image pickup and image transmission system for minitype aircraft |
| CN1992788A (en) * | 2005-12-29 | 2007-07-04 | 比亚迪股份有限公司 | Signal processing circuit of analog image for CMOS image sensor |
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| CN101378513A (en) | 2009-03-04 |
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