CN101377952B - Method and apparatus for reading and writing SRAM data - Google Patents
Method and apparatus for reading and writing SRAM data Download PDFInfo
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- CN101377952B CN101377952B CN2007100768270A CN200710076827A CN101377952B CN 101377952 B CN101377952 B CN 101377952B CN 2007100768270 A CN2007100768270 A CN 2007100768270A CN 200710076827 A CN200710076827 A CN 200710076827A CN 101377952 B CN101377952 B CN 101377952B
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- 238000000034 method Methods 0.000 title claims abstract description 16
- 239000004973 liquid crystal related substance Substances 0.000 claims description 13
- 238000010586 diagram Methods 0.000 description 3
- 230000005540 biological transmission Effects 0.000 description 2
- 239000011159 matrix material Substances 0.000 description 2
- 238000001208 nuclear magnetic resonance pulse sequence Methods 0.000 description 2
- 230000002093 peripheral effect Effects 0.000 description 2
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
- G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
- G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
- G11C11/41—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming static cells with positive feedback, i.e. cells not needing refreshing or charge regeneration, e.g. bistable multivibrator or Schmitt trigger
- G11C11/413—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing, timing or power reduction
- G11C11/417—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing, timing or power reduction for memory cells of the field-effect type
- G11C11/419—Read-write [R-W] circuits
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Abstract
The invention is applicable to the field of integrated circuits and provides a reading and writing method of data in SRAM and a device thereof, the method comprises the following steps: when a serial reading and writing pulse signal is effective, the data is written into the SRAM; the and/or computation of the serial reading and writing pulse signal and an internal scan clock signal is carried out, a parallel reading pulse signal is generated; when the parallel reading pulse signal is effective and reverse with the phase of the effective serial reading and writing pulse signal, the data which is written into the SRAM is parallelly read. The invention adopts the serial reading and wiring and the parallel reading which are effective to the clock of the level to allow the serial reading and writing and the parallel reading to have no time sequence conflict, thereby ensuring the correctness of data reading and writing.
Description
Technical field
The invention belongs to integrated circuit fields, relate in particular to data write method and device among a kind of SRAM.
Background technology
At present, liquid crystal indicator (Liquid Crystal Display in a lot of small-medium sizes, LCD) all be built-in with static RAM (Static Random Access Memory in the chip for driving, SRAM), be used for store various kinds of data, be expert at, column decoder, store the 16bit of data or serial read-write and the parallel read-out of 18bit or 24bit under the control of write buffer and read/write circuit.Because the control timing of carrying out the serial read-write is by outside multipoint control unit (Multipoint Control Unit, MCU) read-write clock provides, and the sequential of parallel read-out is provided by the scan clock of SRAM inside, this just very possible generation should serial be read and write the situation of parallel read-out again to some storage unit in the middle of the SRAM or a certain bit byte (byte), most SRAM integrated circuit are controlled read-write operation with a read/write control line, such as 6 transistor (Transistor, T) SRAM, this is difficult to will be this should serial to read and write again, and the conflict of parallel read-out separates, such as before data parallel is read, just in this storage unit, carrying out the operation that serial is write, be easy to cause losing of data.
Prior art is to increase a first-in first-out (First In First Out between SRAM and MCU to the solution of the problems referred to above, FIFO) circuit module, so-called fifo circuit module is the SRAM of the 8T type of a dual-port just, as shown in Figure 1, ultimate principle is: outside MCU writes clock in the middle of data line DATA_BUS is written to data to be written FIFO by oneself, SRAM is sent to the data read of FIFO to SRAM by its inner scan clock with MCU, just be written to the data of FIFO at first, read away by SRAM at first, if the data in FIFO are read until then by SRAM, FIFO has been write full, FIFO can feed back a SRAM_BUSY signal to MCU, and control MCU does not write to avoid loss of data FIFO again.Because in the chip for driving of embedded SRAM, the area of SRAM accounts for 75% of chip area, the SRAM of the 8T SRAM area than 6T again is a lot of greatly, and this method generally requires the FIFO area very little, otherwise can the speed of the sequential that reads and writes data be limited to some extent, so consider that from read or write speed with to FIFO area aspect this method is not suitable for large-scale use at undersized chip.
In a word, it is excessive that the use of fifo circuit makes the chip for driving area in the prior art, is unfavorable for that chip applies on a large scale, and in addition, the cost of this chip and power consumption are also bigger.
Summary of the invention
The purpose of the embodiment of the invention is to provide data write method among a kind of SRAM, and be intended to solve prior art and use fifo circuit solving serial read-write and parallel read-out timing conflict, so that the excessive problem of chip area.
The embodiment of the invention is achieved in that data write method among a kind of SRAM, said method comprising the steps of:
When serial reading signal is effective, data are write SRAM;
Serial reading signal and inner scanning clock signal are carried out and/exclusive disjunction, produce parallel read pulse signal; Wherein, if between inner scanning clock low period, carry out the parallel read-out of data, then serial reading signal and inner scanning clock signal are carried out exclusive disjunction, if between inner scanning clock high period, carry out the parallel read-out of data, then serial reading signal and inner scanning clock signal carried out and computing;
When the phase place when described parallel read pulse signal is effective and effective with described serial reading signal is opposite, the data parallel of said write SRAM is read.
Another purpose of the embodiment of the invention is to provide a kind of integrated circuit, comprises SRAM, and described integrated circuit also comprises:
One read-write control circuit, receive the serial reading signal and the inner scanning clock signal of input end, serial reading signal and inner scanning clock signal are carried out and/exclusive disjunction, produce parallel read pulse signal, when described parallel read pulse signal effectively and when opposite, trigger the data parallel that writes SRAM and read with serial reading useful signal phase place;
When described read-write control circuit for logic gates and when carrying out serial reading signal and inner scanning clock signal with computing, the parallel read pulse signal of generation is effective between the high period of inner scanning clock; When described read-write control circuit for or logic gates and when serial reading signal and inner scanning clock signal carried out exclusive disjunction, the parallel read pulse signal of generation is effective between the low period of inner scanning clock.
Another purpose of the embodiment of the invention is to provide a kind of liquid crystal indicator, comprises an integrated circuit, and described integrated circuit comprises SRAM, and described integrated circuit also comprises:
One read-write control circuit, receive the serial reading signal and the inner scanning clock signal of input end, serial reading signal and inner scanning clock signal are carried out and/exclusive disjunction, produce parallel read pulse signal, when described parallel read pulse signal effectively and when opposite, trigger the data parallel that writes SRAM and read with serial reading useful signal phase place;
When described read-write control circuit for logic gates and when carrying out serial reading signal and inner scanning clock signal with computing, the parallel read pulse signal of generation is effective between the high period of inner scanning clock; When described read-write control circuit for or logic gates and when serial reading signal and inner scanning clock signal carried out exclusive disjunction, the parallel read pulse signal of generation is effective between the low period of inner scanning clock.
The embodiment of the invention is by adopting serial read-write and parallel read-out effective to the clock of level, and after the serial of outside MCU being read and write the inner scanning clock signal process read-write control circuit processing of clock signal and SRAM, the clock signal of reading as data parallel, thereby make serial read-write and parallel read-out not have timing conflict, and then guaranteed the correctness of reading and writing data.
Description of drawings
Fig. 1 be prior art provide make serial read-write and the asynchronous control device structural representation of parallel read-out;
Fig. 2 is the realization flow figure of the asynchronous method of the serial read-write of data among the SRAM that provides of the embodiment of the invention and parallel read-out;
Fig. 3 is the pulse sequence figure of the 1st kind of situation being provided with of the significant level that carries out serial read-write and parallel read-out that the embodiment of the invention provides;
Fig. 4 be a preferred embodiment of the present invention provide carry out parallel read-out the time the synoptic diagram of pulse signal;
Fig. 5 is the pulse sequence figure that possible occur of the 1st kind of situation of the significant level setting of carrying out serial read-write and parallel read-out that provides of the embodiment of the invention;
Fig. 6 is that the output signal after handling through read-write control circuit with exterior read-write clock and inner scanning clock among the SRAM that provides of the embodiment of the invention is the synoptic diagram of parallel read-out clock;
Fig. 7 is the structural drawing of the SRAM of the serial read-write that provides of the embodiment of the invention and parallel read-out coexistence.
Embodiment
In order to make purpose of the present invention, technical scheme and advantage clearer,, the present invention is further elaborated below in conjunction with drawings and Examples.Should be appreciated that specific embodiment described herein only in order to explanation the present invention, and be not used in qualification the present invention.
In the embodiment of the invention, outside MCU directly is connected with SRAM, when serial read-write clock pulse signal is effective, carry out the serial read-write of data, carry out the parallel read-out of data when the phase place when parallel read pulse signal is effective and effective with serial reading signal is opposite, realized that by simple circuit the sequential of serial read-write and parallel read-out is asynchronous.
Fig. 2 shows the realization flow of the asynchronous method of the serial read-write of data among the SRAM that the embodiment of the invention provides and parallel read-out, and details are as follows:
In step S201, when serial reading signal is effective, data are write SRAM.
In the embodiment of the invention, adopt serial reading signal effective, can be arranged on the serial read-write of carrying out data between the high level of MCU read-write clock or low period as required the level of the read-write clock of outside MCU.
In step S202, serial reading signal and inner scanning clock signal are carried out and/exclusive disjunction, produce parallel read pulse signal.
In the embodiment of the invention, be provided with between the low level of inner scanning clock or high period storage unit is scanned so that data parallel is read, clash for fear of sequential simultaneously with the serial read-write, the parallel read-out that also needs data are set carries out during the non-significant level of serial read-write, and the phase place when promptly parallel read pulse signal is effective with described serial reading signal is opposite.When being provided with, following four kinds of situations are arranged roughly:
1, carries out the serial read-write of data between exterior read-write clock low period, carry out the parallel read-out of data between inner scanning clock low period.At this moment, serial reading signal can be directly provided by the read-write clock of outside MCU, parallel read pulse signal can with exterior read-write clock and inner scanning clock by a read-write control circuit mutually " or " generation afterwards, be specially with two clock signals input one " or " logic gates, with the output signal of this gate circuit as parallel read pulse signal.
2, carry out the serial read-write of data between exterior read-write clock low period, carry out the parallel read-out of data between inner scanning clock high period.At this moment, serial reading signal can be directly provided by the read-write clock of outside MCU, parallel read pulse signal can with exterior read-write clock and inner scanning clock by a read-write control circuit mutually " with " generation afterwards, be specially with two clock signals input one " with " logic gates, with the output signal of this gate circuit as parallel read pulse signal.
3, carry out the serial read-write of data between exterior read-write clock high period, carry out the parallel read-out of data between inner scanning clock low period.At this moment, serial reading signal can be directly provided by the read-write clock of outside MCU, parallel read pulse signal can with exterior read-write clock and inner scanning clock by a read-write control circuit mutually " or " generation afterwards, be specially with two clock signals input one " or " logic gates, with the output signal of this gate circuit as parallel read pulse signal.
4, carry out the serial read-write of data between exterior read-write clock high period, carry out the parallel read-out of data between inner scanning clock high period.At this moment, serial reading signal can be directly provided by the read-write clock of outside MCU, parallel read pulse signal can with exterior read-write clock and inner scanning clock by a read-write control circuit mutually " with " generation afterwards, be specially with two clock signals input one " with " logic gates, with the output signal of this gate circuit as parallel read pulse signal.
In aforesaid four kinds of situations, " with " logic gates and " or " read-write control circuit such as logic gates all can together be built in the integrated circuit with SRAM, this integrated circuit can be used as the chip for driving of liquid crystal indicator, constituted the driving module of liquid crystal indicator jointly with MCU and some peripheral components, the serial read-write of data does not have the sequential of conflict with parallel read-out among this driving module control SRAM.
In step S203,, the data parallel of said write SRAM is read when described parallel read pulse signal effectively and when opposite with described effective serial reading signal phase.
According to four kinds among the step S202 situation is set, respectively effectively and carry out the parallel read-out of data when opposite with described effective serial reading signal phase at parallel read pulse signal, repeating step S201 proceeds the serial read-write of data then, and then parallel read-out.In the embodiment of the invention, serial reading signal is provided by outside MCU, its speed is very fast, SRAM inner scanning clock speed is then slower, can only reach 1/3rd of serial read or write speed at the soonest, so in the low level of clock period of inner scanning clock, the significant level that the external clock of a lot of serial read-writes will be arranged, as shown in Figure 3, but because in an inner clock period, address to the scanning of SRAM is constant, will carry out repeatedly parallel read-out at an inner scanning to the data in the same address in the clock period like this, and power consumption is wasted when the parallel read-out of this repetition to a great extent.
In order to reduce power consumption, the pulse signal that Fig. 4 shows that a preferred embodiment of the present invention provides when carrying out parallel read-out, be example wherein with the 1st kind of situation among the step S201, be specially with a counter inner scanning clock and exterior read-write clock are counted through the clock signal after the logical "or", and count twice, promptly the high level to the exterior read-write clock is counted twice when inner scanning clock low level, guaranteed correctly reading of data like this, reduced power consumption, this counter can be built in the chip for driving of liquid crystal indicator.Wherein counting twice is to consider that exterior read-write clock signal and inner scanning clock signal are two incoherent clock signals, through after the logical "or", be difficult to guarantee that first time clock of counting is a complete high level, as shown in Figure 5, if counter is only counted words once, be difficult to guarantee with correct the reading of data, so counter to this " or " twice of the clock signal of logic gates counting, so that second high level that the counter meter goes out is a complete time clock, guarantee in the correctness of same memory address being read continuously sense data after twice.
In like manner, as if the 2nd, the 3rd or the 4th kind of situation of the significant level of serial read-write and parallel read-out being arranged to described in step S202, need the pulse count signal twice of counter to the output of logic gates separately equally, principle is identical with above-mentioned principle, repeats no more.
Output signal after handling through read-write control circuit with exterior read-write clock and inner scanning clock among the SRAM that Fig. 6 provides for the embodiment of the invention is the synoptic diagram of parallel read-out clock, for convenience of description, only shows the part relevant with the embodiment of the invention.Wherein, SRAM can be built in the chip for driving of liquid crystal indicator, and MCU and chip for driving and some peripheral components have constituted the driving module of liquid crystal indicator jointly, MCU carries out the serial read-write of data in each storage unit in SRAM during the significant level of serial read-write by its read-write clock, the driving module of liquid crystal indicator, and is shown on LCD screen data parallel read-out during the significant level of parallel read-out of storing among the SRAM according to the needs that show.Wherein that situation is set is the same for the significant level of the serial read-write of data and parallel read-out, repeats no more.
Fig. 7 shows the structure of the SRAM of serial read-write that the embodiment of the invention provides and parallel read-out coexistence, it can be embedded in the chip of liquid crystal indicator, and the data among the SRAM carry out under the control of the driving module of liquid crystal indicator that serial writes, series read-out and parallel read-out.For convenience of description, only show the part relevant among the figure with the embodiment of the invention.
As shown in Figure 7, be storage unit in the frame of broken lines among the figure, this storage unit is the SRAM of 6T type, SRAM is the matrix form storage organization that a plurality of storage unit are formed, its total memory capacity is the line number * columns of matrix, parallel read-out is exactly reading of data line one full line that word line is chosen, wherein pre-charge module is used for making the level unanimity of two ends bit line to the bit-line pre-charge at two ends, sensitive comparer is used for that the level differences according to the two ends bit line compares data when parallel read-out, is latching to data sensing latch device.Serial read-write is exactly that data to be written are written among the SRAM in the little storage unit of being chosen simultaneously by word line and bit line by data transmission bus one by one, or from little storage unit, data are delivered to MCU again by data transmission bus one by one, wherein, also need to use sensitive comparer during the serial read data.
In the embodiment of the invention, twice of the non-significant level counting of during inner scanning clock significant level, the serial of exterior read-write clock being read and write, as parallel read pulse signal, thereby guaranteed the correctness that parallel data is read, and, the embodiment of the invention only comprises SRAM, a simple logic gates and a counter of a 6T type, has reduced area of chip greatly, and cost and power consumption also have reduction further.
The above only is preferred embodiment of the present invention, not in order to restriction the present invention, all any modifications of being done within the spirit and principles in the present invention, is equal to and replaces and improvement etc., all should be included within protection scope of the present invention.
Claims (6)
1. data write method among the SRAM is characterized in that, said method comprising the steps of:
When serial reading signal is effective, data are write SRAM;
Serial reading signal and inner scanning clock signal are carried out and/exclusive disjunction, produce parallel read pulse signal; Wherein, if between inner scanning clock low period, carry out the parallel read-out of data, then serial reading signal and inner scanning clock signal are carried out exclusive disjunction, if between inner scanning clock high period, carry out the parallel read-out of data, then serial reading signal and inner scanning clock signal carried out and computing;
When the phase place when described parallel read pulse signal is effective and effective with described serial reading signal is opposite, the data parallel of said write SRAM is read.
2. the method for claim 1 is characterized in that, when the data parallel of said write SRAM is read, same memory address is read twice continuously.
3. an integrated circuit comprises SRAM, it is characterized in that, described integrated circuit also comprises:
One read-write control circuit, receive the serial reading signal and the inner scanning clock signal of input end, serial reading signal and inner scanning clock signal are carried out and/exclusive disjunction, produce parallel read pulse signal, when described parallel read pulse signal effectively and when opposite, trigger the data parallel that writes SRAM and read with serial reading useful signal phase place;
When described read-write control circuit for logic gates and when carrying out serial reading signal and inner scanning clock signal with computing, the parallel read pulse signal of generation is effective between the high period of inner scanning clock; When described read-write control circuit for or logic gates and when serial reading signal and inner scanning clock signal carried out exclusive disjunction, the parallel read pulse signal of generation is effective between the low period of inner scanning clock.
4. integrated circuit as claimed in claim 3 is characterized in that, described integrated circuit further comprises:
One counter is used for described parallel read pulse signal-count, when data parallel is read in control same address is read twice continuously.
5. a liquid crystal indicator comprises an integrated circuit, and described integrated circuit comprises SRAM, it is characterized in that, described integrated circuit also comprises:
One read-write control circuit, receive the serial reading signal and the inner scanning clock signal of input end, serial reading signal and inner scanning clock signal are carried out and/exclusive disjunction, produce parallel read pulse signal, when described parallel read pulse signal effectively and when opposite, trigger the data parallel that writes SRAM and read with serial reading useful signal phase place;
When described read-write control circuit for logic gates and when carrying out serial reading signal and inner scanning clock signal with computing, the parallel read pulse signal of generation is effective between the high period of inner scanning clock; When described read-write control circuit for or logic gates and when serial reading signal and inner scanning clock signal carried out exclusive disjunction, the parallel read pulse signal of generation is effective between the low period of inner scanning clock.
6. liquid crystal indicator as claimed in claim 5 is characterized in that, described integrated circuit further comprises:
One counter is used for described parallel read pulse signal-count, when data parallel is read in control same address is read twice continuously.
Priority Applications (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN2007100768270A CN101377952B (en) | 2007-08-30 | 2007-08-30 | Method and apparatus for reading and writing SRAM data |
| PCT/CN2008/072208 WO2009030169A1 (en) | 2007-08-30 | 2008-08-29 | Method for controlling sram data read-write, integrated circuit and liquid crystal display device with the integrated circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN2007100768270A CN101377952B (en) | 2007-08-30 | 2007-08-30 | Method and apparatus for reading and writing SRAM data |
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| CN101377952A CN101377952A (en) | 2009-03-04 |
| CN101377952B true CN101377952B (en) | 2010-12-08 |
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| CN2007100768270A Expired - Fee Related CN101377952B (en) | 2007-08-30 | 2007-08-30 | Method and apparatus for reading and writing SRAM data |
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| WO (1) | WO2009030169A1 (en) |
Families Citing this family (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102541462A (en) * | 2010-12-28 | 2012-07-04 | 上海芯豪微电子有限公司 | Broadband read-write memory device |
| US9183922B2 (en) | 2013-05-24 | 2015-11-10 | Nvidia Corporation | Eight transistor (8T) write assist static random access memory (SRAM) cell |
| US8995210B1 (en) * | 2013-11-26 | 2015-03-31 | International Business Machines Corporation | Write and read collision avoidance in single port memory devices |
| KR20230103586A (en) | 2021-12-31 | 2023-07-07 | 엘지디스플레이 주식회사 | Data Communication circuit and Display Device including the same |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1635477A (en) * | 2003-12-30 | 2005-07-06 | 中国科学院空间科学与应用研究中心 | Real-time error detection and correction chip |
| US7016235B2 (en) * | 2004-03-03 | 2006-03-21 | Promos Technologies Pte. Ltd. | Data sorting in memories |
| CN1804990A (en) * | 2006-01-20 | 2006-07-19 | 西安西北工业大学科技产业集团公司 | Method of design of control circuit in static storage in LCD drive chipset |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| KR0154998B1 (en) * | 1994-10-13 | 1998-11-16 | 김광호 | Data alignment circuit for image processing memory |
| US6181640B1 (en) * | 1997-06-24 | 2001-01-30 | Hyundai Electronics Industries Co., Ltd. | Control circuit for semiconductor memory device |
| JP2002025275A (en) * | 2000-07-10 | 2002-01-25 | Toshiba Corp | Semiconductor memory |
| JP2002093173A (en) * | 2000-09-20 | 2002-03-29 | Mitsubishi Electric Corp | Synchronous multi-port memory |
| KR101189256B1 (en) * | 2005-12-29 | 2012-10-09 | 매그나칩 반도체 유한회사 | Device and Method for Controlling SRAM in DDI |
| US7420858B2 (en) * | 2006-02-17 | 2008-09-02 | International Business Machines Corporation | Methods and apparatus for read/write control and bit selection with false read suppression in an SRAM |
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- 2007-08-30 CN CN2007100768270A patent/CN101377952B/en not_active Expired - Fee Related
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1635477A (en) * | 2003-12-30 | 2005-07-06 | 中国科学院空间科学与应用研究中心 | Real-time error detection and correction chip |
| US7016235B2 (en) * | 2004-03-03 | 2006-03-21 | Promos Technologies Pte. Ltd. | Data sorting in memories |
| CN1804990A (en) * | 2006-01-20 | 2006-07-19 | 西安西北工业大学科技产业集团公司 | Method of design of control circuit in static storage in LCD drive chipset |
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| WO2009030169A1 (en) | 2009-03-12 |
| CN101377952A (en) | 2009-03-04 |
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Assignee: SHENZHEN BYD MICROELECTRONICS Co.,Ltd. Assignor: BYD Co.,Ltd. Contract fulfillment period: 2008.4.25 to 2015.8.16 Contract record no.: 2008440000068 Denomination of invention: Method and apparatus for reading and writing SRAM data License type: General permission Record date: 20080504 |
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Address after: 518119 No.1 Yan'an Road, Kuiyong street, Dapeng New District, Shenzhen City, Guangdong Province Patentee after: BYD Semiconductor Co.,Ltd. Address before: 518119 No.1 Yan'an Road, Kuiyong street, Dapeng New District, Shenzhen City, Guangdong Province Patentee before: SHENZHEN BYD MICROELECTRONICS Co.,Ltd. Address after: 518119 No.1 Yan'an Road, Kuiyong street, Dapeng New District, Shenzhen City, Guangdong Province Patentee after: BYD Semiconductor Co.,Ltd. Address before: 518119 No.1 Yan'an Road, Kuiyong street, Dapeng New District, Shenzhen City, Guangdong Province Patentee before: BYD Semiconductor Co.,Ltd. |
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