CN101364610B - Groove type power metal oxide semiconductor and preparation thereof - Google Patents
Groove type power metal oxide semiconductor and preparation thereof Download PDFInfo
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- CN101364610B CN101364610B CN2007101404337A CN200710140433A CN101364610B CN 101364610 B CN101364610 B CN 101364610B CN 2007101404337 A CN2007101404337 A CN 2007101404337A CN 200710140433 A CN200710140433 A CN 200710140433A CN 101364610 B CN101364610 B CN 101364610B
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Abstract
The invention is a groove-type power metal oxide semi-transistor, which is provided with a gate, a drain electrode, a source electrode and a baseplate. The section structure of the semi-transistor includes a first doped semiconductor, two second doped semiconductors, an oxide layer and a polysilicon layer, wherein, the first doped semiconductor forms the baseplate and is provided with a groove; the two doped semiconductors are arranged on the baseplate; the drain electroce is formed on one side of the groove; the source electrode is formed on the other side of the groove; the groove extends downwards from the position between the drain electrode and the source electrode into the baseplate; the oxide layer is positioned on the inner wall surface of the groove and extends downwards from the position between the drain electrode and the source electrode along the inner wall surface of the groove to the baseplate; and the polysilicon layer is positioned in the groove and wrapped in the oxide layer to form the gate.
Description
Technical field
The present invention is a kind of groove type power metal oxide semiconductor and preparation method thereof, refers to have drain especially and source electrode all is positioned at the structure on the substrate, and gate groove type power metal oxide semiconductor in the groove and preparation method thereof between drain and source electrode.
Background technology
First figure is the groove-type power transistor arrangement profile of commonly using, and has wherein comprised the light doped semiconductor of source electrode 11, gate 12, N type heavily-doped semiconductor 13, P type doped semiconductor 14, N type 15, N type heavily-doped semiconductor 16, drain 17 and groove 18.
The high potential assembly of commonly using; For example: dual diffusion drain MOS transistor (DoubleDiffusion Drain Metal-Oxide-Semiconductor Field Effect Transistor; DDDMOSFET) and lateral diffusion metal oxide semiconductor (Lateral DiffusionMetal-Oxide-Semiconductor Field Effect Transistor; LDMOSFET) etc., owing to have bigger structure and be not suitable for being applied to power transistor (Power MOS).Therefore, commonly use the manufacture method of power transistor (Power MOS), the main employing has the groove-type power transistor (Trench Power MOSFET) than minor structure.In the middle of the groove-type power transistor arrangement of commonly using, source electrode 11 is the tops that are positioned at structure.Structural body has a groove 18, and gate 12 promptly is positioned in the middle of the groove 18.In addition, two sides at groove 18 have N type heavily-doped semiconductor 13; The below of N type heavily-doped semiconductor 13 is a P type doped semiconductor 14.Part in P type doped semiconductor 14 and groove 18 belows is the light doped semiconductor 15 of N type, and the light doped semiconductor 15 of N type mainly is used for promoting transistorized breakdown voltage.The part of below is a N type heavily-doped semiconductor 16, and drain 17 promptly is positioned at the bottom of chip.
The groove-type power transistor of commonly using must be made by the higher crystalline substance of heap of stone of use cost because body construction is comparatively special.On the other hand, the groove-type power transistor arrangement of commonly using is subject to effect on structure own, and groove must have the darker degree of depth, makes passage length improve, and causes the electric current of each assembly to reduce, and causes reliability to reduce.
The groove-type power transistor of commonly using has following shortcoming:
1. the groove-type power transistor of commonly using must be made by the higher crystalline substance of heap of stone of use cost, increases to make required cost.
2. the groove-type power transistor of commonly using has long passage length, makes the electric current of each assembly reduce, and causes reliability to reduce.
Therefore, how improving the above-mentioned shortcoming of commonly using, effectively reduce and make required cost and the transistorized reliability of bring to power, is to be concern person of the present invention.
Summary of the invention
The objective of the invention is to groove type power metal oxide semiconductor that proposes a novelty and progress and preparation method thereof; Utilization places drain and source electrode on the substrate; And between drain and source electrode, adopt the plough groove type structure, and gate is designed in the middle of groove, make it have better reliability degree; And can make with general wafer material, effectively reduce and make required cost.
For reaching above-mentioned purpose, the present invention proposes a kind of groove type power metal oxide semiconductor, has a gate, a drain, one source pole and a substrate, and its cross-section structure comprises:
One first doping type semiconductor is to form this substrate, and tool one groove;
2 second doping type semiconductors are to be positioned on this substrate, and form this drain in one of this groove side; Opposite side in this groove forms this source electrode; This ditch mortise system is by extending downward between this drain and this source electrode among this substrate;
One oxide layer is to be positioned at this trench wall surface, and along this trench wall surface by extending downward this substrate between this drain and this source electrode;
One polysilicon layer is to be positioned at this groove, is coated among this oxide layer, and forms this gate.
Like described groove type power metal oxide semiconductor, wherein this first doping type semiconductor system is a P type doped semiconductor.
Like described groove type power metal oxide semiconductor, wherein this 2 second doping type semiconductors system is N type doped semiconductor.
Like described groove type power metal oxide semiconductor, wherein one of this 2 second doping type semiconductor is to be a light doping type semiconductor.
Like described groove type power metal oxide semiconductor, wherein one of this 2 second doping type semiconductor is to be a heavy doping N-type semiconductor N.
Like described groove type power metal oxide semiconductor, wherein has identical thickness with these oxidation series of strata and this oxide layer between between this source electrode and this gate between this gate between this drain.
Like described groove type power metal oxide semiconductor, wherein be thicker than this oxide layer between between this source electrode and this gate between these oxidation series of strata between this drain and this gate.
Like described groove type power metal oxide semiconductor, wherein this drain system has the identical degree of depth with this source electrode.
Like described groove type power metal oxide semiconductor, wherein the degree of depth of this drain system is deeper than the degree of depth of this source electrode.
Like described groove type power metal oxide semiconductor, wherein more comprise a shallow trench isolation (STI), this shallow trench isolation system is between this drain and this gate.
Like described groove type power metal oxide semiconductor, it is to be a planar trenches formula power transistor (Planner Trench MOS).
A kind of groove type power metal oxide semiconductor has a gate, a drain, one source pole and a substrate, and its plan structure comprises:
One trench area is to comprise an oxide layer, and these oxidation series of strata are coated on a polysilicon layer wherein, and these polysilicon series of strata form this gate; This oxide layer more covers one first doping type semiconductor region, and this first doping type semiconductor fauna forms this substrate;
2 second doping type semiconductor regions lie in two sides of this trench area, and form this drain in a side; Form this source electrode in opposite side, and cover this substrate.
Like described groove type power metal oxide semiconductor, wherein this first doping type semiconductor fauna comprises a P type doped semiconductor.
Like described groove type power metal oxide semiconductor, wherein this 2 second doping type semiconductors fauna comprises N type doped semiconductor.
Like described groove type power metal oxide semiconductor, wherein one of this 2 second doping type semiconductor region is to comprise a light doping type semiconductor.
Like described groove type power metal oxide semiconductor, wherein one of this 2 second doping type semiconductor region is to comprise a heavy doping N-type semiconductor N.
Like described groove type power metal oxide semiconductor, wherein more comprise a shallow trench isolation (STI) district, this shallow trench isolation fauna and is covered within this oxide layer between this drain and this gate.
Like described groove type power metal oxide semiconductor, it is to be a planar trenches formula power transistor (Planner Trench MOS)
A kind of groove type power metal oxide semiconductor manufacture method comprises the following step:
One first doping type semiconductor is provided, and forms a substrate;
On this substrate, form one first oxide layer;
Definition one second doping type semiconductor regions on this substrate, and form a drain;
On this first oxide layer, form a hard light shield;
Definition one trench region on this hard light shield;
On this substrate, form a groove;
Form one second oxide layer in this trench wall surface;
In this groove, form a polysilicon layer, use forming a gate;
Cover on one the 3rd oxide layer this polysilicon layer in this groove;
Definition one another second doping type semiconductor regions, and form one source pole.
Like described groove type power metal oxide semiconductor manufacture method, wherein this first doping type semiconductor system is a P type doped semiconductor.
Like described groove type power metal oxide semiconductor manufacture method, wherein this second doping type semiconductor system is N type doped semiconductor.
Like described groove type power metal oxide semiconductor manufacture method, wherein this another second doping type semiconductor system is N type doped semiconductor.
Like described groove type power metal oxide semiconductor manufacture method, wherein this second doping type semiconductor system is a light doping type semiconductor.
Like described groove type power metal oxide semiconductor manufacture method, wherein this another second doping type semiconductor system is a heavy doping N-type semiconductor N.
Like described groove type power metal oxide semiconductor manufacture method, wherein more comprise a step: define a shallow trench isolation (STI) zone in this polysilicon layer, and form this shallow trench isolation.
Like described groove type power metal oxide semiconductor manufacture method, wherein defining this second doping type semiconductor regions is to utilize a light shield definition.
Like described groove type power metal oxide semiconductor manufacture method, wherein this hard light shield is to comprise a nitration case, a boron-doping glassy layer and one second polysilicon layer.
Like described groove type power metal oxide semiconductor manufacture method, wherein define this trench region and lie in and utilize a light shield definition on this hard light shield.
The present invention has advantage:
1. groove type power metal oxide semiconductor proposed by the invention, its volume size is similar with the groove type power metal oxide semiconductor of commonly using.
2. groove type power metal oxide semiconductor proposed by the invention has better reliability degree.
3. groove type power metal oxide semiconductor proposed by the invention, each assembly can have higher electric current.
4. groove type power metal oxide semiconductor proposed by the invention has insulation structure of shallow groove, can produce higher breakdown voltage.
5. groove type power metal oxide semiconductor proposed by the invention can be made with general wafer material, effectively reduces and makes required cost.
Embodiment
Second figure (A) (B) (C) is the groove type power metal oxide semiconductor section of structure of preferred embodiment of the present invention, has wherein comprised drain contact hole 21, drain 22, shallow trench isolation 23, substrate 24, groove 25, oxide layer 26, gate 27, source contact hole 28 and source electrode 29.
Be different from the groove type power metal oxide semiconductor of commonly using; In the middle of the cross-section structure of groove type power metal oxide semiconductor proposed by the invention; Drain 22 all is positioned on the formed substrate 24 of P type doped semiconductor with source electrode 29, and groove 25 is between drain 22 and source electrode 29.Drain 22 is to adopt the mode of dual diffusion with the structure of source electrode 29, and drain 22 is to be made up of the light doped semiconductor of N type, adopts light doping to can be used to increase and connects the face breakdown voltage; Source electrode 29 then is to be made up of N type heavily-doped semiconductor, and employing heavy doping can be in order to lower the resistance of source electrode.In the middle of groove 25, the inner wall surface of groove 25 has covered layer of oxide layer 26, has coated one deck polysilicon layer among the oxide layer 26, gate 27 be exactly thus polysilicon layer constitute.Oxide layer 26 between gate 27 and drain 22 has the thickness of broad, forms a shallow trench isolation 23 (STI).The purposes of shallow trench isolation 23 is main to be to be used for avoiding 22 pairs of gates of drain 27 oxide layer 26 on every side of higher-pressure region to cause the collapse phenomenon.
The 3rd figure is the groove type power metal oxide semiconductor structure vertical view of preferred embodiment of the present invention, has wherein comprised the second doping type semiconductor region 31, the second doping type semiconductor region 32 and trench area 33.
In the plan structure of groove type power metal oxide semiconductor proposed by the invention, source electrode system is positioned at the second doping type semiconductor region 31; Drain system is positioned at the second doping type semiconductor region 32, and source electrode and drain all cover on the substrate, and have a trench area 33 each other.Be to comprise an oxide layer in the trench area 33, and under oxide layer, cover a polysilicon layer, these polysilicon series of strata form a gate.Polysilicon layer covers on this substrate equally.
The 4th figure is that the groove type power metal oxide semiconductor of preferred embodiment of the present invention is made flow chart, has wherein comprised the following step:
Step 41: one first doping type semiconductor is provided, and forms a substrate;
Step 42: on this substrate, form one first oxide layer;
Step 43: definition one second doping type semiconductor regions on this substrate, and form a drain;
Step 44: on this first oxide layer, form a hard light shield;
Step 45: definition one trench region on this hard light shield;
Step 46: on this substrate, form a groove;
Step 47: form one second oxide layer in this trench wall surface;
Step 48: in this groove, form a polysilicon layer, use forming a gate;
Step 49: define a shallow trench isolation region in this polysilicon layer, and form this shallow trench isolation;
Step 410: cover on one the 3rd oxide layer this polysilicon layer in this groove;
Step 411: definition one another second doping type semiconductor regions, and form one source pole.
The 5th figure is that the groove type power metal oxide semiconductor of preferred embodiment of the present invention is made the flow process decomposing schematic representation, has wherein comprised substrate 51, first oxide layer 52, drain 53, hard light shield 54, nitration case 541, boron-doping glassy layer 542, second polysilicon layer 543, groove 55, second oxide layer 56, gate 57, shallow trench isolation 58, source electrode 59 and metal level 510.
Groove type power metal oxide semiconductor proposed by the invention, its manufacture method at first provide one first doping type semiconductor in step 41, and this first doping type semiconductor system is a P type doped semiconductor, and forms a substrate 51.Then, on this substrate, form one first oxide layer 52 in step 42.After first oxide layer 52 produces, in step 43, on this substrate, utilize light shield to define one second doping type semiconductor regions, and form a drain 53 in this zone by the dual diffusing, doping mode of high temperature.Wherein, this second doping type semiconductor system is the light doped semiconductor of N type.After forming on the substrate, then in the middle of step 44, on this first oxide layer, form a hard light shield 54 at the light doped semiconductor of N type.Hard light shield system is made up of a nitration case 541, a boron-doping glassy layer 542 and 543 of one second polysilicon layers.Be nitration case 541 on first oxide layer, be boron-doping glassy layer 542 on the nitration case 541, the top is second polysilicon layer 543.In the middle of step 45, prior to definition one groove 55 zones on this hard light shield 54; On this substrate, form a groove 55 in step 46 again.After groove 55 forms, in step 47, form one second oxide layer 56 in this trench wall surface.Then, in step 48, in this groove, form a polysilicon layer, and utilize boron-doping glass to define a shallow trench isolation 58 zones in this polysilicon layer in step 49.Then cover on one the 3rd oxide layer this polysilicon layer in this groove, and form this shallow trench isolation 58 in step 410.Define another second doping type semiconductor regions in step 411 again, and form this source electrode 59.Wherein, this another second doping type semiconductor system is a N type heavy doping N-type semiconductor N.Form a metal level 510 in upper surface at last, pull out a drain contact, pull out a gate contact and pull out the one source pole contact from the second doping type semiconductor again from another second doping type semiconductor from polysilicon layer.
In sum, the groove type power metal oxide semiconductor that the present invention carried utilizes drain and source electrode are placed on the substrate; And between drain and source electrode, adopt the plough groove type structure, and gate is designed in the middle of this groove; Not only have better reliability degree, more can effectively reduce cost of manufacture, progressive novel and practical; Like its change design; For example do not have shallow trench isolation (STI) structure, utilize other flow process to make transistor arrangement that the present invention carried or utilize different materials to make etc., so long as have drain and source electrode all is positioned on the substrate, and between drain and source electrode, have groove structure; And gate is positioned at groove, all is the scope that the present invention protected.
Claims (16)
1. a groove type power metal oxide semiconductor has a gate, a drain, one source pole and a substrate, it is characterized by its cross-section structure and comprises:
One first doping type semiconductor forms this substrate, and tool one groove;
2 second doping type semiconductors are positioned on this substrate, and form this drain in one of this groove side; Opposite side in this groove forms this source electrode; This groove system is by extending downward between this drain and this source electrode among this substrate;
One oxide layer is positioned at this trench wall surface, and along this trench wall surface by extending downward this substrate between this drain and this source electrode;
One polysilicon layer is to be positioned at this groove, is coated among this oxide layer, and forms this gate;
Wherein more comprise a shallow trench isolation, this shallow trench isolation is between this drain and this gate.
2. groove type power metal oxide semiconductor according to claim 1 is characterized by:
Wherein this second doping type semiconductor is a P type doped semiconductor.
3. groove type power metal oxide semiconductor according to claim 1 is characterized by:
Wherein this 2 second doping type semiconductor is-N type doped semiconductor.
4. groove type power metal oxide semiconductor according to claim 1 is characterized by:
Wherein one of this 2 second doping type semiconductor is a light doping type semiconductor.
5. groove type power metal oxide semiconductor according to claim 1 is characterized by:
Wherein one of this 2 second doping type semiconductor is a heavy doping N-type semiconductor N.
6. groove type power metal oxide semiconductor according to claim 1 is characterized by:
Wherein has identical thickness with this oxide layer and this oxide layer between between this source electrode and this gate between this gate between this drain.
7. groove type power metal oxide semiconductor according to claim 1 is characterized by:
Wherein be thicker than this oxide layer between between this source electrode and this gate between this oxide layer between this drain and this gate.
8. groove type power metal oxide semiconductor according to claim 1 is characterized by:
Wherein this drain has the identical degree of depth with this source electrode.
9. groove type power metal oxide semiconductor according to claim 1 is characterized by:
Wherein the degree of depth of this drain is deeper than the degree of depth of this source electrode.
10. groove type power metal oxide semiconductor according to claim 1 is characterized by:
It is a planar trenches formula power transistor.
11. a groove type power metal oxide semiconductor has a gate, a drain, one source pole and a substrate, it is characterized by its plan structure and comprises:
One trench area is to comprise an oxide layer, and these oxidation series of strata are coated on a polysilicon layer wherein, and these polysilicon series of strata form this gate; This oxide layer more covers one first doping type semiconductor region, and this first doping type semiconductor fauna forms this substrate:
2 second doping type semiconductor regions are positioned at two sides of this trench area, and form this drain in a side; Form this source electrode in opposite side, and cover this substrate;
Wherein more comprise a shallow trench isolation district, this shallow trench isolation district is positioned between this drain and this gate, and is covered within this oxide layer.
12. groove type power metal oxide semiconductor according to claim 11 is characterized by: wherein this first doping type semiconductor region comprises a P type doped semiconductor.
13. groove type power metal oxide semiconductor according to claim 11 is characterized by: wherein this 2 second doping type semiconductor region comprises N type doped semiconductor.
14. groove type power metal oxide semiconductor according to claim 11 is characterized by: wherein one of this 2 second doping type semiconductor region comprises a light doping type semiconductor.
15. groove type power metal oxide semiconductor according to claim 11 is characterized by: wherein one of this 2 second doping type semiconductor region comprises a heavy doping N-type semiconductor N.
16. groove type power metal oxide semiconductor according to claim 11 is characterized by: it is a planar trenches formula power transistor.
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| Application Number | Priority Date | Filing Date | Title |
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| CN2007101404337A CN101364610B (en) | 2007-08-10 | 2007-08-10 | Groove type power metal oxide semiconductor and preparation thereof |
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| Application Number | Priority Date | Filing Date | Title |
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| CN2007101404337A CN101364610B (en) | 2007-08-10 | 2007-08-10 | Groove type power metal oxide semiconductor and preparation thereof |
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| CN101364610A CN101364610A (en) | 2009-02-11 |
| CN101364610B true CN101364610B (en) | 2012-06-27 |
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Granted publication date: 20120627 |