CN101359306A - Detecting method for internal memory regulating result and computer system thereof - Google Patents
Detecting method for internal memory regulating result and computer system thereof Download PDFInfo
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Abstract
The invention discloses a memory adjustment result detection method and the computer system thereof. The method includes the steps: the computer system is started; the memory adjustment program of the BIOS in the computer system is executed; after the memory adjustment program is executed, the acquired a plurality of read time parameters and write time parameters are written into a non-volatile memory. The memory adjustment result detection method has the advantages that the acquired a plurality of read time parameters and write time parameters are written into the non-volatile memory during the startup process of the computer and the execution process of the BIOS.
Description
Technical field
The present invention relates to the internal memory control method in a kind of computer system, and be particularly related to a kind of internal memory adjustment (training) detection method and computer system thereof as a result.
Background technology
In general, have a Memory Controller Hub (memory controller) on the mainboard of computer system, this Memory Controller Hub can design within north bridge chips (north-bridge chip) or central processing unit (CPU).And memory modules, for example two built-in memory modules (dual in-line memory module is called for short DIMM) then can insert (plug) memory module slot on mainboard, for example dimm socket.Therefore, Memory Controller Hub can carry out the transmission of data with memory modules.
Moreover Memory Controller Hub and memory bank all are to weld (soldered) on mainboard, connect and have metal wire (metal traces) between Memory Controller Hub and the memory bank.In addition, memory modules also has a daughter board (daughter board), one side the golden finger (gold fingers) that has of daughter board can be inserted in memory module slot.And also weld a plurality of random access memory chips (hereinafter to be referred as dram chip) on the daughter board, have metal wire between dram chip and the golden finger and connect.
When Memory Controller Hub sends when writing instruction (write command), data can be sent to dram chip and storage from Memory Controller Hub.And when Memory Controller Hub sent reading command (read command), data can be sent to Memory Controller Hub from dram chip, and were passed to CPU and handle.
With Double Data Rate (double data rate is hereinafter to be referred as DDR) memory modules or the two built-in memory modules (DDR DIMM) of Double Data Rate is example, and a DDR transaction (DDR transaction) comprises the steps:
At first, Memory Controller Hub is sent instruction by order line (command lines) and address wire (address lines).And when next instruction frequency (command clock), all DDR memory modules can be by reading this instruction on order line and the address wire, and the decision relevant DDR memory modules of instruction therewith.Then, all dram chips in this DDR memory modules are promptly prepared storage or reading of data according to instruction.
Then, when instruction was reading command, all dram chips on the specific DDR memory modules can begin driving data serial signal (being called for short the DQ signal) and data-triggered (strobe) signal (being called for short the DQS signal).Perhaps, when instruction was instructed for writing, DQ signal and DQS signal were then driven by Memory Controller Hub.Afterwards, DQ signal and DQS signal can begin operation (toggling).In general, supposing has eight dram chips in the memory modules, then have 64 DQ signals and 8 DQS signals, and the DQ signal is a Data transmission, and the DQS signal is Data transmission frequency (data clock).
Please refer to Figure 1A and Figure 1B, it is depicted as the signal on the DDR memory modules.In general, four DDR memory modules of Memory Controller Hub 300 may command.For convenience of explanation, two DDR memory modules 100,200 only are shown among Figure 1A and Figure 1B.Wherein, Figure 1A is depicted as four instruction frequencies (CMDCLK0～3), four chip select signals (chip select signal, CS0～3), command signal, the address signal of Memory Controller Hub 300 outputs.By among the figure as can be known, comprise 8 dram chips 101～108, a buffer (register) 120 in the DDR memory modules 100; Comprise 8 dram chips 201～208, a buffer (register) 220 in the 2nd DDR memory modules 200.Moreover two DDR memory modules 100,200 insert first and second memory bank 150,250.And command signal and address signal that Memory Controller Hub 300 produces, for example, address signal (A0～A13), row address trigger pip (rowaddress strobe, abbreviation RAS signal), column address trigger pip (column address strobe, abbreviation CAS signal), write-enable signal (write enable, abbreviation WE signal), can be passed to the buffer 120,220 of all DDR memory modules 100,200.
Moreover (CS0～CS4) is to the buffer 120,220 of other DDR memory modules 100,200 for exportable four groups of instruction frequency signals (CMDCLK0～3) of Memory Controller Hub 300 and four chip select signals.That is to say, utilize the signal shown in Figure 1A can learn that dram chip 101～108 in the DDR memory modules 100 or the dram chip 201～208 in the 2nd DDR memory modules 200 need reading of data or write the address of data.
Please refer to Figure 1B, it is depicted as DQ signal and DQS signal on the DDR memory modules.By Figure 1B as can be known, in the DDR memory modules 100 8 dram chips 101～108 are arranged; 8 dram chips 201～208 are arranged in the 2nd DDR memory modules 200, and each chip needs 1 DQS signal of 8 DQ signal collocation, and 8 DQ signals are called bit channel (byte lane).That is to say that the data speed that bit channel transmitted is to be controlled by corresponding 1 DQS signal.
Therefore, shown in Figure 1B, first dram chip 101,201 in a DDR memory modules 100 and the 2nd DDR memory modules 200 is connected to DQ0～DQ7 signal and DQS0 signal; Second dram chip 102,202 in the one DDR memory modules 100 and the 2nd DDR memory modules 200 is connected to DQ8～DQ15 signal and DQS1 signal; The 3rd dram chip 103,203 in the one DDR memory modules 100 and the 2nd DDR memory modules 200 is connected to DQ16～DQ23 signal and DQS2 signal; The 4th dram chip 104,204 in the one DDR memory modules 100 and the 2nd DDR memory modules 200 is connected to DQ24～DQ31 signal and DQS3 signal; The 5th dram chip 105,205 in the one DDR memory modules 100 and the 2nd DDR memory modules 200 is connected to DQ32～DQ39 signal and DQS4 signal; The 6th dram chip 106,206 in the one DDR memory modules 100 and the 2nd DDR memory modules 200 is connected to DQ40～DQ47 signal and DQS5 signal; The 7th dram chip 107,207 in the one DDR memory modules 100 and the 2nd DDR memory modules 200 is connected to DQ48～DQ55 signal and DQS6 signal; And the 7th dram chip 107,207 in a DDR memory modules 100 and the 2nd DDR memory modules 200 is connected to DQ56～DQ63 signal and DQS7 signal.
That is to say, when instruction when reading a DDR memory modules 100,8 dram chips 101～108 on the DDR memory modules 100 can begin to drive DQ0-63 signal and DQS0-7 signal.Perhaps, when instruction when writing a DDR memory modules 100, DQ0-63 signal and DQS0-7 signal are then driven by Memory Controller Hub 300.Afterwards, DQ0-63 signal and DQS0-7 signal can begin operation (toggling).
Please refer to Fig. 2 A, it is depicted as the relation between the DQ signal and DQS signal on the transmission ends.According to the specification of DDR internal memory, when data were being transmitted, DQ signal and DQS signal be alignment (align) mutually.With DQ0～DQ7 signal and DQS0 signal is example, the data of DQ0～DQ7 must align rising edge (rising edge) and the falling edge (falling edge) of DQS0.That is to say that when reading command, all dram chips can be considered transmission ends (transiver) and export the DQ signal and DQS signal and Memory Controller Hub can be considered receiving end (receiver) and receives the DQ signal and the DQS signal; Otherwise in writing when instruction, Memory Controller Hub can be considered transmission ends and exports the DQ signal and DQS signal and all dram chip can be considered receiving end and receives the DQ signal and the DQS signal.And the DQ signal of transmission ends output must align mutually with the DQS signal.
As everyone knows, very numerous of memory modules manufacturer on the market are inserted in the identical computer system and the user can buy the memory modules of different vendor arbitrarily.And the memory modules that different vendor's manufacturing is come out is except the difference of dram chip, and the wiring of daughter board (lay out) also is inequality.So the transmission delay of each signal (propagation delay) can be inequality, thus cause that data can't be correct write dram chip or can't be correct read by dram chip.
Please refer to Fig. 2 B, it is depicted as the relation between the DQ signal and DQS signal on the receiving end.Also promptly, when DQ0～7 signals and DQS0 signal are passed to receiving end, can cause DQ0～7 signals can't align usually with the DQS0 signal.By Fig. 2 B as can be known, the DQ6 signal propagation delay is very serious, might cause that data on the DQ6 can't be correct write dram chip or can't be correct read by dram chip, thereby cause the memory modules can't regular event.
Moreover, when the designer of computer system process, in order to allow different memory modules all can successfully read and write at the research and development mainboard.The designer must buy the memory modules of various different vendors and insert on the memory module slot, afterwards, tests all memory modules.Because therefore the daughter board of different memory modules design difference, dram chip difference and speed difference can cause some memory modules to read smoothly or to write.
In order to address the above problem, the designer must be connected to all signal wires on the oscillograph on the memory bank on the mainboard, and watches all signal qualities in the process of test memory module.For instance, suppose to carry out writing or produce DQ6 Signal Fail (just the data of DQ6 can't read or write) during reading order, at this moment, the designer just must analyze the relation between DQ6 signal and the DQS0 signal.Usually, the reason that can fail is that all the DQ6 signal can't align with the DQS0 signal, to such an extent as to and the serious Memory Controller Hub of situation or dram chip can't read data on the DQ6 accurately.That is to say that the designer of known computer systems only can seek relation between DQ6 signal and the DQS0 signal by observed phenomenon on the oscillograph, and manages queueing problem.
Yet when the kind of memory modules was a lot, test memory module and queueing problem will become hard work, also can postpone the time of mainboard shipment except inefficent.
Summary of the invention
In view of this, the object of the present invention is to provide a kind of detecting method for internal memory regulating result and computer system thereof, to improve the defective of prior art.
The present invention proposes detecting method for internal memory regulating result in a kind of computer system, comprises the following steps: computer system power-on; An internal memory of a Basic Input or Output System (BIOS) is adjusted program in the computer system; And, carry out this internal memory adjustment program after, a plurality of time for reading parameters and a plurality of write time parameter that obtains write a nonvolatile memory.
The present invention also proposes a kind of computer system that writes down internal memory regulating result, comprising: a central processing unit; One internal memory comprises a memory modules; One chipset is connected to internal memory and central processing unit, and wherein a Memory Controller Hub is integrated in the chipset; One Basic Input or Output System (BIOS) is connected to chipset, and has internal memory adjustment program; And a nonvolatile memory is connected to chipset; Wherein, in the process of computer system power-on, central processing unit is carried out internal memory and is adjusted program, and a plurality of time for reading parameters that will obtain and a plurality of write time parameter write to nonvolatile memory.
The present invention also proposes a kind of computer system that writes down internal memory regulating result, comprising: a central processing unit, integrate a Memory Controller Hub; One internal memory is connected to central processing unit, and internal memory comprises a memory modules; One chipset is connected to central processing unit; One Basic Input or Output System (BIOS) is connected to chipset, and has internal memory adjustment program; And a nonvolatile memory is connected to chipset; Wherein, in the process of computer system power-on, central processing unit can be carried out internal memory and adjust program, and a plurality of time for reading parameters that will obtain and a plurality of write time parameter write to nonvolatile memory.
The invention has the advantages that computer booting and carry out the process of BIOS, with a plurality of time for reading parameters and a plurality of write time parameter write non-volatile memory that obtains.
In order further to understand feature of the present invention and technology contents, see also following about detailed description of the present invention and accompanying drawing, yet accompanying drawing only provide with reference to and explanation, be not to be used for the present invention is limited.
Description of drawings
Figure 1A and Figure 1B are depicted as the signal on the DDR memory modules.
Fig. 2 A is depicted as the relation between the DQ signal and DQS signal on the transmission ends.
Fig. 2 B is depicted as the relation between the DQ signal and DQS signal on the receiving end.
Figure 3 shows that reading the DQ signal adjusts program and read DQS signal adjustment program.
Fig. 4 A is depicted as first embodiment that the present invention can write down the computer system of internal memory regulating result.
Fig. 4 B is depicted as second embodiment that the present invention can write down the computer system of internal memory regulating result.
Figure 5 shows that detecting method for internal memory regulating result process flow diagram in the computer system of the present invention.
Embodiment
In general, the deviser of computer system can design an internal memory and adjust program (memory training codes) in Basic Input or Output System (BIOS) (hereinafter to be referred as BIOS).In the initialized process of computer system, the internal memory that CPU can carry out among the BIOS is adjusted program, and after internal memory adjustment program was finished, memory modules promptly can successful writing and read.
So-called internal memory is adjusted program, promptly be to utilize Memory Controller Hub control DQ signal and DQS signal respectively other time delay reach DQ signal and DQS signal alignment on the receiving end.Therefore, internal memory adjustment program can write DQ signal adjustment program (write DQ), writes DQS signal adjustment program (write DQS), reads DQ signal adjustment program (read DQ), read DQS signal adjustment program (read DQS).
Because can align when dram chip output DQS signal and DQ signal, therefore, DQS signal and DQ signal can't align when being passed to Memory Controller Hub.And the so-called DQ of reading signal is adjusted program and is read DQS signal adjustment program, promptly be that Memory Controller Hub can be adjusted the DQS signal that receives and the time of DQ signal severally when reading, make DQS and all DQ signal alignment, and make the DQ signal all can be read smoothly.
What is called writes the DQ signal and adjusts program and write DQS signal adjustment program, promptly be when the write memory module, Memory Controller Hub can be controlled the time of DQS signal and DQ signal severally, makes can reach DQS signal and DQ signal alignment when DQS signal and DQ signal arrive the DRAM sheet.That is to say, Memory Controller Hub is individually controlled the signal relation between DQS signal and the DQ signal, can not align when making output DQS signal and DQ signal, but DQS signal and DQ signal can be reached DQS signal and DQ signal alignment when arriving dram chip.
Please refer to Fig. 3, it is depicted as and reads DQ signal adjustment program and read DQS signal adjustment program.When DQ0～8 signals and DQS0 signal are passed to Memory Controller Hub, can't align between DQ0～8 signals and the DQS0 signal.At this moment, internal memory adjustment program can be adjusted the relation between DQ0～8 signals and the DQS0 signal, reaches DQ0～8 signals and DQS0 signal alignment.As shown in Figure 3, DQ6 signal delay is the most serious, because of setting Δ tQ
DQ6Be 0, and other signal can postpone according to DQ6.Therefore, the mistiming between DQS0 signal and the DQ6 signal is Δ tQ
DQS0, and internal memory adjustment program can be with DQS0 signal delay Δ tQ
DQS0Time; Mistiming between DQ0 signal and the DQ6 signal is Δ tQ
DQ0, and internal memory adjustment program can be with DQ0 signal delay Δ tQ
DQ0Time; Mistiming between DQ1 signal and the DQ6 signal is Δ tQ
DQ1, and internal memory adjustment program can be with DQ1 signal delay Δ tQ
DQ1Time; Mistiming between DQ2 signal and the DQ6 signal is Δ tQ
DQ2, and internal memory adjustment program can be with DQ2 signal delay Δ tQ
DQ2Time; Mistiming between DQ3 signal and the DQ6 signal is Δ tQ
DQ3, and internal memory adjustment program can be with DQ3 signal delay Δ Δ tQ
DQ3Time; Mistiming between DQ4 signal and the DQ6 signal is Δ tQ
DQ4, and internal memory adjustment program can be with DQ4 signal delay Δ tQ
DQ4Time; Mistiming between DQ5 signal and the DQ6 signal is Δ tQ
DQ5, and internal memory adjustment program can be with DQ5 signal delay Δ tQ
DQ5Time; And the mistiming between DQ7 signal and the DQ6 signal is Δ tQ
DQ7, and internal memory adjustment program can be with DQ7 signal delay Δ tQ
DQ7Time.
That is to say, can obtain a plurality of time for reading parameter (Δ tQ after utilizing the above-mentioned DQ of reading signal adjustment program and reading DQS signal adjustment program
DQS0, Δ tQ
DQ0～Δ tQ
DQ7).Profit can obtain a plurality of write time parameters in writing after the DQ signal is adjusted program and write DQS signal adjustment program in a like fashion.And successfully set when finishing when a plurality of time for reading parameters and a plurality of write time parameter, memory modules can be finished initialization (initial) and can read or write data smoothly.Otherwise, when above-mentioned a plurality of time for reading parameters and a plurality of write time parameter can't successfully be set when finishing, memory modules initialization (initial) failure and can't read or write data.
According to embodiments of the invention, when CPU can carry out internal memory among the BIOS and adjusts program, the no matter memory modules success that whether is initialised, CPU is stored in a plurality of time for reading parameters and a plurality of write time parameter in one nonvolatile memory, flash memory for example, and Computer System Design person can learn time relationship between all signals according to a plurality of time for reading parameters and a plurality of write time parameter of storage, and utilizes these to concern and judge.Therefore can solve the known oscillograph that must utilize and to learn time relationship between all signals.
Please refer to Fig. 4 A, it is depicted as first embodiment that the present invention can write down the computer system of internal memory regulating result.Computer system have a central processing unit (CPU) 500, a chipset (chip set) 505, one BIOS 508, a nonvolatile memory 506, with an internal memory 510.Wherein, a chipset 505 comprises a north bridge chips (north bridge chip) 502, one South Bridge chip (south bridge chip) 504, and north bridge chips 502 be connected to internal memory 510, central processing unit 500, with South Bridge chip 504; South Bridge chip 504 is connected to north bridge chips 502, BIOS 508 and nonvolatile memory 506.And the internal memory 510 among Fig. 4 A comprises at least one memory modules, and has an internal memory to adjust program 509 among the BIOS 508, and Memory Controller Hub 503 is integrated in the north bridge chips 502 of chipset 505.
Please refer to Fig. 4 B, it is depicted as second embodiment that the present invention can write down the computer system of internal memory regulating result.Computer system have a central processing unit (CPU) 550, a chipset 555, a BIOS 558, a nonvolatile memory 556, with an internal memory 560.Wherein, a chipset 555 comprises a north bridge chips 552, a South Bridge chip 554, and central processing unit 550 is connected to internal memory 560; North bridge chips 552 is connected to central processing unit 550 and South Bridge chip 554; South Bridge chip 554 is connected to north bridge chips 552, BIOS 558 and nonvolatile memory 556.And the internal memory 560 among Fig. 4 B comprises at least one memory modules, and has an internal memory to adjust program 559 among the BIOS 558, and Memory Controller Hub 551 is integrated in the central processing unit 550.
In the process of computer system power-on, when the internal memory of central processing unit 500 in carrying out BIOS 508 adjusted program, write in the nonvolatile memory adjusting a plurality of time for reading parameters and a plurality of write time parameter that memory modules obtained.Therefore, Computer System Design person can judge according to a plurality of time for reading parameters and a plurality of write time parameter of storage.Moreover, many special purpose computer players (power user) all can carry out overclocking with memory modules, and utilize the present invention, the special purpose computer player also can be after memory modules carries out overclocking and starts shooting again, utilize a plurality of time for reading parameters and a plurality of write time parameter of nonvolatile memory stored, come to learn the memory modules relation between all signals in success and the memory modules that whether is initialised.
Please refer to Fig. 5, it is depicted as detecting method for internal memory regulating result process flow diagram in the computer system of the present invention.At first, when computer system power-on, as step S1, the internal memory of carrying out among the BIOS is adjusted program, as step S2.Afterwards, with a plurality of time for reading parameters and a plurality of write time parameter write non-volatile memory that obtains, as step S3.Therefore, can learn the relation between all signals according to a plurality of time for reading parameters of nonvolatile memory stored and a plurality of write time parameter and can judge.
Therefore, the invention has the advantages that computer booting and carry out the process of BIOS, with a plurality of time for reading parameters and a plurality of write time parameter write non-volatile memory that obtains.And can judge relation between all signals according to a plurality of time for reading parameters and a plurality of write time parameter.
Moreover above-mentioned memory modules can apply to the DDR memory modules, for example, and the two built-in memory modules (DDR DIMM) of Double Data Rate.
In sum; though the present invention with preferred embodiment openly as above; yet it is not in order to limit the present invention; any those of ordinary skills; without departing from the spirit and scope of the present invention; when can doing various changes and retouching, so protection scope of the present invention is as the criterion when looking the scope that claims define.
Claims (14)
1. a detecting method for internal memory regulating result is characterized in that, comprises the following steps:
With computer system power-on;
Carry out the internal memory of Basic Input or Output System (BIOS) in the aforementioned calculation machine system and adjust program; And
After carrying out above-mentioned internal memory adjustment program, with a plurality of time for reading parameters and a plurality of write time parameter write non-volatile memory that obtains.
2. method according to claim 1 is characterized in that, wherein above-mentioned nonvolatile memory is a flash memory.
3. method according to claim 1 is characterized in that, comprises in the wherein above-mentioned internal memory adjustment program that reading the DQ signal adjusts program and read DQS signal adjustment program, in order to obtain above-mentioned these time for reading parameters.
4. method according to claim 1 is characterized in that, comprises in the wherein above-mentioned internal memory adjustment program that writing the DQ signal adjusts program and write DQS signal adjustment program, in order to obtain above-mentioned these write time parameters.
5. a computer system that writes down internal memory regulating result is characterized in that, comprising:
Central processing unit;
Internal memory comprises memory modules;
Chipset is connected to above-mentioned internal memory and above-mentioned central processing unit, and wherein Memory Controller Hub is integrated in the said chip group;
Basic Input or Output System (BIOS) is connected to the said chip group, and has internal memory adjustment program; And
Nonvolatile memory is connected to the said chip group;
Wherein, in the process of aforementioned calculation machine system boot, above-mentioned central processing unit is carried out above-mentioned internal memory and is adjusted program, and a plurality of time for reading parameters that will obtain and a plurality of write time parameter write to above-mentioned nonvolatile memory.
6. computer system according to claim 5 is characterized in that, wherein above-mentioned nonvolatile memory is a flash memory.
7. computer system according to claim 5 is characterized in that, wherein above-mentioned internal memory adjustment program is adjusted program and read DQS signal adjustment program for reading the DQ signal, in order to obtain above-mentioned these time for reading parameters in the above-mentioned internal memory.
8. computer system according to claim 5 is characterized in that, wherein above-mentioned internal memory adjustment program is for writing the adjustment of DQ signal and writing the adjustment of DQS signal, in order to obtain above-mentioned these write time parameters in the above-mentioned internal memory.
9. computer system according to claim 5 is characterized in that, wherein above-mentioned memory modules is the Double Data Rate memory modules.
10. a computer system that writes down internal memory regulating result is characterized in that, comprising:
Central processing unit is integrated Memory Controller Hub;
Internal memory is connected to above-mentioned central processing unit, and above-mentioned internal memory comprises memory modules;
Chipset is connected to above-mentioned central processing unit;
Basic Input or Output System (BIOS) is connected to the said chip group, and has internal memory adjustment program; And
Nonvolatile memory is connected to the said chip group;
Wherein, in the process of aforementioned calculation machine system boot, above-mentioned central processing unit can be carried out above-mentioned internal memory and adjust program, and a plurality of time for reading parameters that will obtain and a plurality of write time parameter write to above-mentioned nonvolatile memory.
11. computer system according to claim 10 is characterized in that, wherein above-mentioned nonvolatile memory is a flash memory.
12. computer system according to claim 10 is characterized in that, wherein above-mentioned internal memory adjustment program is adjusted program and is read DQS signal adjustment program for reading the DQ signal, in order to obtain above-mentioned these time for reading parameters in the above-mentioned internal memory.
13. computer system according to claim 10 is characterized in that, wherein above-mentioned internal memory adjustment program is adjusted program and is write DQS signal adjustment program for writing the DQ signal, in order to obtain above-mentioned these write time parameters in the above-mentioned internal memory.
14. computer system according to claim 10 is characterized in that, wherein above-mentioned memory modules is the Double Data Rate memory modules.
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Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101847104A (en) * | 2010-05-19 | 2010-09-29 | 深圳市九洲电器有限公司 | Method, system and embedded device for configuring memory parameters |
| US8060785B2 (en) | 2009-06-11 | 2011-11-15 | Asustek Computer Inc. | Method for tuning parameters in memory and computer system using the same |
| CN101923503B (en) * | 2009-06-11 | 2012-08-29 | 华硕电脑股份有限公司 | Method for regulating internal parameters of internal storage and computer system using same |
| CN110928736A (en) * | 2019-12-06 | 2020-03-27 | 迈普通信技术股份有限公司 | Memory parameter debugging method and device |
| CN111143104A (en) * | 2019-12-29 | 2020-05-12 | 苏州浪潮智能科技有限公司 | Memory exception processing method and system, electronic device and storage medium |
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2008
- 2008-09-26 CN CN 200810161091 patent/CN101359306B/en active Active
Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US8060785B2 (en) | 2009-06-11 | 2011-11-15 | Asustek Computer Inc. | Method for tuning parameters in memory and computer system using the same |
| CN101923503B (en) * | 2009-06-11 | 2012-08-29 | 华硕电脑股份有限公司 | Method for regulating internal parameters of internal storage and computer system using same |
| CN101847104A (en) * | 2010-05-19 | 2010-09-29 | 深圳市九洲电器有限公司 | Method, system and embedded device for configuring memory parameters |
| CN110928736A (en) * | 2019-12-06 | 2020-03-27 | 迈普通信技术股份有限公司 | Memory parameter debugging method and device |
| CN111143104A (en) * | 2019-12-29 | 2020-05-12 | 苏州浪潮智能科技有限公司 | Memory exception processing method and system, electronic device and storage medium |
| US11977744B2 (en) | 2019-12-29 | 2024-05-07 | Inspur Suzhou Intelligent Technology Co., Ltd. | Memory anomaly processing method and system, electronic device, and storage medium |
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|---|---|
| CN101359306B (en) | 2012-12-05 |
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