CN101355043A - Encapsulation body for electronic element and preparation method thereof - Google Patents
Encapsulation body for electronic element and preparation method thereof Download PDFInfo
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- CN101355043A CN101355043A CNA2008101086343A CN200810108634A CN101355043A CN 101355043 A CN101355043 A CN 101355043A CN A2008101086343 A CNA2008101086343 A CN A2008101086343A CN 200810108634 A CN200810108634 A CN 200810108634A CN 101355043 A CN101355043 A CN 101355043A
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/11—Manufacturing methods
Abstract
The invention provides an electronic component package and a method for manufacturing the same. The method comprises the following steps that a wafer is provided and comprises a plurality of crystal grain zones to bear the weight of or form a plurality of chips, and a plurality of conductive electrodes are arranged on or above the chips; a photo mask is provided and a photoetching process is carried out to form a patterned photoresist layer on the wafer; the patterned photoresist layer comprises a plurality of openings which correspond to the pattern of a photo mask; the pattern comprises a relatively wide first picture composition which is connected with at least one relatively narrow second picture composition; the patterned photoresist layer is taken as a mask to carry out etching to the wafer, thereby forming a plurality of holes so as to expose the conductive electrodes; the holes have asymmetric side walls; and finally, the patterned photoresist layer is removed. The method adopts the one-step continuous etching step to manufacture the holes with asymmetric side walls, thereby shorting manufacturing process, and reducing manufacturing cost.
Description
Technical field
The present invention is relevant for a kind of manufacture method of electronic element packaging body, particularly relevant for electronic element packaging body of a kind of via (via hole) with asymmetry sidewall and preparation method thereof.
Background technology
Generally speaking, electronic element packaging body can be that the mode that cover plate, wafer and loading plate pile up is made.Wherein can form one and pass the via of wafer, and pass through the signal of the conductive layer transmission wafer of via.Yet the vertical sidewall of above-mentioned via can cause conductive layer to be difficult for deposition, and then increases the degree of difficulty of processing procedure.
Therefore, need a kind of manufacture method of electronic element packaging body badly, to solve the above problems.
Summary of the invention
In view of this, one embodiment of the invention provide a kind of manufacture method of electronic element packaging body, and it comprises: a wafer is provided, comprises a plurality of die region, to carry or to form a plurality of wafers, on the described wafer or top comprises a plurality of conductive electrodes; One light shield is provided and implements a lithographic process to form a patterning photoresist layer on wafer, patterning photoresist layer comprises a plurality of openings, the pattern of the corresponding light shield of wherein said opening, this pattern comprises first composition of a relative broad, and this first composition also links second composition of at least one relative narrower; With patterning photoresist layer is the cover curtain, and wafer is carried out etching, forms a plurality of holes to expose described conductive electrode, and wherein said hole has the sidewall of asymmetry; And remove patterning photoresist layer.
The manufacture method of electronic element packaging body of the present invention, this second composition from junction to the far-end convergent.
The inside that the manufacture method of electronic element packaging body of the present invention, described hole are passed described wafer is with as via.
The manufacture method of electronic element packaging body of the present invention also comprises: form an insulating barrier covering described wafer, and extend on the sidewall and described conductive electrode of described via; And remove this insulating barrier that is positioned at described via bottom, and expose the surface of described conductive electrode.
The manufacture method of electronic element packaging body of the present invention, described via comprise a first side wall and one second sidewall, wherein at least this second sidewall slope in this wafer face.
The manufacture method of electronic element packaging body of the present invention, this first side wall adjacent to a cutting area and essence perpendicular to this wafer face.
The manufacture method of electronic element packaging body of the present invention, this first side wall are corresponding to this first composition, and this second sidewall is corresponding to this second composition.
The manufacture method of electronic element packaging body of the present invention also comprises forming a conductor layer on this insulating barrier, and this conductor layer extends on the surface of this second sidewall of this via and this conductive electrode.
Another embodiment of the present invention provides a kind of manufacture method of electronic element packaging body, comprise: a wafer is provided, comprise a plurality of die region, to carry or to form a plurality of wafers, wafer has a first surface and a relative second surface, wherein on the first surface or top comprises a plurality of conductive electrodes, to electrically connect described wafer; Form an encapsulated layer, to cover the first surface of wafer; One light shield is provided and implements a lithographic process to form a patterning photoresist layer on the second surface of this wafer, this patterning photoresist layer comprises a plurality of openings, the pattern of the corresponding light shield of wherein said opening, this pattern comprises first composition of a relative broad, and a side of first composition also links second composition of at least one convergent; With patterning photoresist layer is cover curtain, and the second surface of wafer is carried out etching, forms a plurality of vias to expose described conductive electrode, and wherein said hole has the sidewall of asymmetry; Remove patterning photoresist layer; Form the second surface of an insulating barrier, and extend on the sidewall and conductive electrode of described via with the covering wafer; And remove the insulating barrier of described via bottom, it exposes the surface of described conductive electrode.
The manufacture method of electronic element packaging body of the present invention, described conductive electrode comprise a conductive contact pad or a rerouting line layer.
The manufacture method of electronic element packaging body of the present invention, described via comprise a first side wall and one second sidewall, and perpendicular to this wafer face, this second sidewall slope is in this wafer face adjacent to a cutting area and essence for this first side wall.
The manufacture method of electronic element packaging body of the present invention, this first side wall are corresponding to this first composition, and this second sidewall is corresponding to this second composition.
The manufacture method of electronic element packaging body of the present invention also comprises forming a plurality of conductor layers on this insulating barrier, and described conductor layer extends on the surface of second sidewall of described via and described conductive electrode from this second surface.
The manufacture method of electronic element packaging body of the present invention also comprises: form a protective layer inserting described via, and extend on the second surface of this wafer; And cut apart this wafer to isolate a plurality of encapsulated wafers.
Yet another embodiment of the invention provides a kind of electronic element packaging body, and it comprises: a substrate; One metal level is positioned in this substrate; One has the via of asymmetry sidewall, is formed among this substrate and exposes this metal level; And a conductive layer, be formed on the surface of this substrate, and extend on the asymmetry sidewall of this via to electrically connect this metal level.
Electronic element packaging body of the present invention, this via comprise a first side wall and one second sidewall, and the horizontal sextant angle between the surface of the horizontal sextant angle between the surface of this first side wall and this substrate and this second sidewall and this substrate is unequal.
Electronic element packaging body of the present invention, this horizontal sextant angle of this first side wall are less than or equal to 90 degree.
Electronic element packaging body of the present invention, this horizontal sextant angle of this second sidewall are less than or equal to 90 degree.
Electronic element packaging body of the present invention, this via have one first opening and one second opening, and this first opening is less than this second opening.
Further embodiment of this invention provides a kind of manufacture method of electronic element packaging body.This manufacture method comprises: provide a top to be formed with the substrate of metal level; Engage an encapsulated layer on the first surface of this substrate; Be coated with a photo anti-corrosion agent material layer on the second surface of this substrate; By an asymmetry light shield, this photo anti-corrosion agent material layer of patterning is to form a patterning photoresist layer with asymmetry sidewall; And carrying out an etching step, the via that has the asymmetry sidewall with formation is among this substrate; Form an insulating barrier to coat this via; Remove this insulating barrier of part to expose this metal level in this via bottom; And form a conductive layer on the second surface of this substrate, and extend in this via to electrically connect this metal level.
Because the patterns of openings of above-mentioned patterning photoresist can cause different etching speeds, therefore, can pass through disposable continuous etching step, make hole, and then shorten and make flow process and reduce cost of manufacture with asymmetry sidewall.
Description of drawings
Fig. 1 to Fig. 6 shows the schematic diagram according to a kind of electronic element packaging body of making of the embodiment of the invention;
Fig. 7 to Fig. 9 shows the vertical view according to the image sensing element packaging body back side of the embodiment of the invention behind pattern-making photoresist layer;
Figure 10 shows the flow chart according to a kind of electronic element packaging body of making of the embodiment of the invention;
Figure 11 to Figure 16 shows the profile of making a kind of electronic element packaging body according to an embodiment of the invention.
Embodiment
Next, by embodiment and cooperation back accompanying drawing formula, to describe notion of the present invention and the concrete mode of implementing in detail.In graphic or description, element similar or same section uses same or analogous symbolic representation.And the shape of the element in graphic or thickness can enlarge, to simplify or convenient the sign.In addition, the element that does not illustrate or describe can have the form known to those skilled in the art.
The present invention will be with a specific embodiment of making Image Sensor (image sensor) packaging body as an illustration.Yet scrutable is that notion of the present invention can certainly be applied to other semiconductor element that need make via (via hole).That is, in packaging body embodiment of the present invention, it can be applicable to the various electronic components (electroniccomponents) that comprise active member or passive device (active or passive elements), digital circuit or analog circuit integrated circuits such as (digital or analog circuits), for example relates to photoelectric cell (opto electronic devices), MEMS (micro electro mechanical system) (Micro Electro Mechanical System; MEMS), physical quantitys such as microfluid system (micro fluidic systems) or utilization heat, light and pressure change the physics sensor of measuring (Physical Sensor).Particularly can select to use wafer-level packaging (wafer scale package; WSP) processing procedure is to Image Sensor, light-emitting diode (light-emitting diodes; LEDs), solar cell (solarcells), radio-frequency (RF) component (RF circuits), accelerometer (accelerators), gyroscope (gyroscopes), little brake (micro actuators), surface acoustic wave element (surfaceacoustic wave devices), pressure sensor (process sensors) or ink gun semiconductor wafers such as (ink printer heads) encapsulate.
Wherein above-mentioned wafer-level packaging processing procedure mainly refers to after wafer stage is finished encapsulation step, cut into independently packaging body again, yet, in a specific embodiment, the semiconductor wafer redistribution that for example will separate is on a carrying wafer, carry out encapsulation procedure again, what also can claim is the wafer-level packaging processing procedure.In addition, above-mentioned wafer-level packaging processing procedure also is applicable to borrow and piles up the multi-disc wafer that (stack) mode arrangement has integrated circuit, to form the electronic element packaging body of multilevel integration (multi-layer integrated circuit devices).
Figure 10 shows the flow chart according to a kind of electronic element packaging body of making of the embodiment of the invention.As shown in figure 10, at first, as step S5, S10 and shown in Figure 1, one wafer 100 is provided, comprises a plurality of die region, to carry or to form a plurality of wafers 102, wafer 100 has a first surface S1 and a relative second surface S2, wherein on the first surface S1 or top comprises a plurality of conductive electrodes 106, and to electrically connect described wafer 102 (hereinafter referred to as the substrate 102 of wafer), described conductive electrode comprises a conductive contact pad or a rerouting line layer.Then form an encapsulated layer 108, to cover the first surface S1 of wafer.In a selectable step, as step S15, further thinning wafer is to reduce the height of packaging body.
See also step S20, S25 and Fig. 2 to Fig. 4, form a patterning photoresist layer 114a on the second surface S2 of wafer, for example carry out the exposure photo-etching processing procedure by 116 pairs of photo anti-corrosion agent material layers of light shield 114 with specific pattern 118, make patterning photoresist layer 114a form a plurality of openings 122, wherein specific pattern comprise a broad first composition, 138, the first compositions 138 a side and link second composition 136 of at least one convergent.With patterning photoresist layer 114a is cover curtain, and the second surface S2 of wafer 100 is carried out etching, forms a plurality of vias 128 to expose described conductive electrode 106, and wherein said via 128 has sidewall 124a, the 124b of asymmetry.
See also step S30, S35 and Fig. 5, remove patterning photoresist layer 114a after, form an insulating barrier 126 covering the second surface S2 of wafer 100, and extend on the sidewall 124 and conductive electrode 106 of described via 128.The insulating barrier of removing described via 128 bottoms is to expose the surface of described conductive electrode 106.Wherein, described conductive electrode 106 can comprise a sedimentary deposit or the rerouting line layer that a conductive contact pad, metal material constitute.124 of the sidewalls of via 128 comprise a first side wall 124a and one second sidewall 124b, and the first side wall 124a approaches cutting area SC and essence perpendicular to the wafer face, and the second sidewall 124b then favours the wafer face.And according to Fig. 3, Fig. 7 or shown in Figure 8, the first side wall 124a corresponding to first composition, 138, the second sidewall 124b corresponding to second composition 136.Form a plurality of conductor layers 130 afterwards on insulating barrier 126, conductor layer extends on the surface of the second sidewall 124b of described via 128 and conductive electrode 106 from second surface S2.
See also step S40, S45 and Fig. 6; forming one for example is that the protective layer 132 of soldering-resistance layer is to insert via 128; and extend on the second surface S2 of wafer, and to be provided with for example be the conductive projection 134 of scolder spheroid or weld pad, it can be embedded in the protective layer 132 to electrically connect conductor layer 130.Cut apart wafer to isolate a plurality of encapsulated wafers along cutting area S C afterwards.
In above-mentioned packaging body, because the asymmetric side wall construction of via, therefore for example can select to make sidewall 124a comparatively precipitous, can save the size of via, and be positioned at conductor layer on the sidewall 124a because not as the usefulness of signal transmission near cut section, therefore, need not consider its tack, otherwise, as the conductor layer of the usefulness of signal transmission, the gradient of the sidewall 124b at its place is comparatively gentle, therefore can improve the sputter and the adhesive ability of conductor layer.
To the foregoing description, below just Fig. 1 to Fig. 6 do more detailed description, it shows that making a kind of according to embodiments of the invention for example is the schematic diagram of the electronic element packaging body of Image Sensor.As shown in Figure 1, provide one for example to be the wafer 100 of silicon or other suitable semi-conducting material, it comprises substrate 102, and be formed with a photo-sensitive cell (photosensitive device) 104 and one conductive electrode 106 above this substrate 102, it is as a conductive contact pad (conductive contact pad).In one embodiment, above-mentioned photo-sensitive cell 104 can be complementary metal oxide semiconductor element (complementary metal-oxide-semiconductor; CMOS) or charge coupled cell (charge-coupled device; CCD), in order to pick-up image or image.And above-mentioned conductive contact pad 106 can for example be copper (copper; Cu), aluminium (aluminum; Al), tungsten (tungsten; W) or other suitable metal material, and this conductive contact pad 106 electrically connects above-mentioned photo-sensitive cell 104, to transmit the signal of photo-sensitive cell 104.
And for example shown in Figure 1, provide one for example be the encapsulated layer 108 of glass, quartz (quartz), opal (opal), plastic cement or other transparent base as cover plate, and this encapsulated layer 108 is arranged at above-mentioned substrate 102 tops.In one embodiment, can be to form a wall 110 earlier in above-mentioned substrate 102 tops, then, be coated with an adhesion coating (adhesive layer) 112 in above-mentioned wall 110 tops, and this encapsulated layer 108 be attached at above-mentioned substrate 102 tops afterwards.In another embodiment, also can be earlier above-mentioned wall 110 to be formed on the encapsulated layer 108, then, coating adhesion coating 112 afterwards, is arranged at substrate 102 tops with encapsulated layer 108 on wall 110.
Above-mentioned wall 110 is preferable can be epoxy resin (epoxy), polyimide resin (polyimide; PI), photoresist (photoresist) material or other suitable material, and by coating method, for example rotary coating, spraying or drench curtain coating cloth, or other depositional mode that is fit to forms.And above-mentioned adhesion coating 112 also can be the sticker that contains epoxy resin.In addition, also can optionally form a protective layer (figure shows) on one and formation wall 110 rightabout outer surfaces of above-mentioned encapsulated layer 108, to avoid scratch.
As shown in Figure 2, after encapsulated layer 108 is set, by for example being cmp (chemical mechanical polishing; CMP) method or etching (etching), milling (milling), grinding (grinding) or the mode of grinding (polishing) are ground above-mentioned substrate 102, with the thickness of this substrate 102 of thinning.Then, be coated with a photo anti-corrosion agent material (photoresist material) layer 114 on the back side of above-mentioned substrate 102.One light shield (mask) 116 is provided, and this light shield 116 have a pattern 118 can for light by or stop that light passes through.Please consult Fig. 3 earlier, the vertical view of the above-mentioned light shield 116 in its display part.As shown in Figure 3, the pattern 118 of above-mentioned light shield 116 can comprise first composition 138 and second a narrower composition 136 of a broad, its by with the junction of first composition 138 towards the far-end convergent, for example be the triangle pattern of going up convergent in cross section Y.And for example shown in Figure 2, carry out a step of exposure 120, the light of part can pass pattern 118, and the photo anti-corrosion agent material layer 114 of exposed portion, and pattern 118 is copied to photo anti-corrosion agent material layer 114.In addition, above-mentioned pattern 118 also can be the design of a taper or arc.
What deserves to be mentioned is that above-mentioned photo anti-corrosion agent material layer 114 can be negative type photoresist material or positive light anti-etching agent material, and the pattern 118 of light shield 116 also can the different design according to the difference of photo anti-corrosion agent material layer 114.For example, when photo anti-corrosion agent material layer 114 was the positive light anti-etching agent material, pattern 118 can be to allow light to pass through.And when photo anti-corrosion agent material layer 114 was the negative type photoresist material, pattern 118 can be to stop that light passes through.
As shown in Figure 4, after exposure, above-mentioned photo anti-corrosion agent material layer 114 develops, remove the photo anti-corrosion agent material layer 114 that part has been exposed, to form a patterning photoresist layer 114a, it has the opening 122 of a corresponding above-mentioned pattern 118, and the surface of opening 122 expose portion substrates 102 whereby.That is to say that the pattern of the opening 122 of patterning photoresist 114a can be the figure of a convergent, for example is triangle or taper (taper).
In Fig. 4, then, carry out an etching step, remove part substrate 102, expose the hole with asymmetry sidewall 128 of joint sheet 106 among substrate 102 to form one.In one embodiment, by for example being ten thousand formulas of dry ecthing (dry-etching), substrate 102 surfaces that etching part is above-mentioned.Because opening 122 patterns of patterning photoresist layer 114a are towards one dimension direction convergent.Therefore, when carrying out etching step, can cause along the substrate of the remaining different deep thickness of a certain party greater than the etching speed of the narrow portion of its convergent at the etching speed (etching rate) of opening 122 wider parts, can make hole 128 whereby with asymmetry sidewall.
In addition, when etching step, opening 122 shapes of above-mentioned patterning photoresist layer 114a can cause the etching speed of different base 102, and then cause the substrate 102 of different-thickness residual.Therefore, utilize aforesaid way, can be in single time continuity etching step, preparation has the hole 128 of asymmetry sidewall, and does not need photoetching/etching (photolithography/etching) processing procedure through repeatedly.So, according to the mode that the embodiment of the invention disclosed, can shorten the time of processing procedure, and reduce the cost of making.
As shown in Figure 5, after the making of finishing above-mentioned hole 128, remove above-mentioned patterning photoresist layer 114a, then, form an insulating barrier 126 on the back side of substrate 102, and extend on the asymmetry sidewall of hole 128.In one embodiment, above-mentioned insulating barrier 126 can be silica (silicon oxide), silicon nitride (siliconnitride), silicon oxynitride (silicon oxynitride) or other other suitable insulation material, and by chemical vapour deposition (CVD) (chemical vapor deposition; CVD) method, electricity slurry heavier-duty chemical vapour deposition (CVD) (plasma enhanced chemical vapordeposition; PECVD) mode of method or coating (coating) forms.
As shown in Figure 5, then, hole 128 is as a via (via hole) (after this with via 128 expressions), and a conductor layer (conductive trace layer) 130 is formed on the back side of substrate 102, and extends in the via 128.In one embodiment, by for example being the mode of sputter (sputtering), evaporation (evaporating) or plating (electroplating), deposition one for example is copper, aluminium (aluminum; Al) or nickel (nickel; Ni) conductive material layer (not illustrating) is on the back side of substrate 102, and this conductive material layer can be filled in the above-mentioned via 128 with asymmetry sidewall 124a, 124b, to electrically connect conductive contact pad 106.Afterwards, by photoetching/etch process, the patterning conductive material layer is to form above-mentioned conductor layer 130.Because the sidewall that above-mentioned hole 128 has asymmetry makes to be easier to above-mentioned conductive material layer is deposited or extends on the angled side walls.In addition, owing to only need sidewall on one side is made as inclination, and another side can keep vertical.Therefore, also can save the area of substrate 102, and then make packaging body with relative reduced size.
It should be noted that the step of above-mentioned patterning conductive material layer, layout is transmitted the transmission line of signal again, and therefore, above-mentioned conductor layer 130 also can be called rerouting line layer (redistribution layer).In addition, via 128 also can be called the via with asymmetric sidewall.
As shown in Figure 6, coating one for example be the protective layer 132 of soldering-resistance layer (solder mask) on the back side of substrate 102, and cover conductor layer 130, then, this protective layer 132 of patterning is with expose portion conductor layer 130.Being coated with a scolder on the conductor layer 130 that exposes, and carrying out a reflow (reflow) step, for example is that the conductive projection 134 of scolder spheroid or weld pad is on the back side of substrate 102 to form one.After finishing above-mentioned steps, carry out a cutting step along cutting area, to cut out an image sensing element packaging body 140.
Fig. 7 to Fig. 9 shows the vertical view according to the image sensing element packaging body back side of the embodiment of the invention behind pattern-making photoresist layer 114a.Compared to the foregoing description, its difference is opening 122 patterns of patterning photoresist 114a.To embodiment shown in Figure 9, the production method of similar element and material can be similar to the aforementioned embodiment at Fig. 7.Therefore, at this and repeat no more.
As shown in Figure 7, patterning photoresist layer 114a has the opening 122 of an exposure substrate 102, and the pattern 123 of this opening 122 is made of one second composition 136 and one first composition 128.Above-mentioned second composition 136 can be a pattern, triangle for example, and first composition 138 can be a rectangle (rectangle).Because the pattern 123 of opening 122 can cause the etching speed of different substrates 102.Therefore, can pass through this mode, in single time continuity etching step, make hole with asymmetry sidewall.
As shown in Figure 8, the pattern 123 of opening 122 is made of one second composition 136 and one first composition 138, and this second composition 136 can be similar to second composition shown in Figure 7, and first composition 138 also can for example be the polygon (polygon) of pentagon (pentagon).Similarly, the pattern 123 of opening 122 can cause the etching speed of different substrates 102, and the substrate 102 of generation different-thickness is remaining.In view of the above, can in disposable continuous etching step, make hole with asymmetry sidewall.
As shown in Figure 9, in the pattern 123 of opening 122, first composition 138 can be similar to first composition shown in Figure 7, and second composition 136 then can be a convergent pattern, and the side of this second composition 136 is with the past convergent of non-linear mode as camber line.As the foregoing description, the pattern 123 of opening 122 can cause the etching speed of different substrates 102, and the substrate 102 of generation different-thickness is remaining.Therefore, can in single time continuity etching step, make hole with asymmetry sidewall.
What deserves to be mentioned is, above-mentioned second composition 136 also can be made up of the composition of a plurality of convergents, as the design of a plurality of Fig. 7 or second composition shown in Figure 9, and various difform first compositions 138 of arranging in pairs or groups, for example be the design of rectangle, pentagon, polygon or circle etc.According to the described mode of the embodiment of the invention, can make the patterns of openings of the patterning photoresist layer that causes different etching speeds, whereby, and can single etching step, make hole with asymmetry sidewall.
And when distance between two second compositions 136 is excessive, in-between zone may be because of keeping too much so that degree of depth deficiency, therefore, mask pattern can form another opening 136a that independently narrows between the two, its direction that narrows is then reverse with second composition 136, reason is the far-end spacing broad of two second compositions 136, need form opening in addition and increase etched scope.
Below be described further at the angle of inclination of the asymmetric sidewall of hole.Scrutable is that in the following example, above-mentioned wafer can comprise the substrate that the top is formed with a plurality of die region; Above-mentioned conductive electrode can be the sedimentary deposit that metal material constitutes; Encapsulated layer can be used as a cover plate; Wall can be used as a support portion; Conductor layer can be used as the conductive layer that transmits signal; And conductive projection can be to use the scolder spheroid as conducting position.
Figure 11 to Figure 16 shows the profile of making a kind of electronic element packaging body according to another embodiment of the present invention.Though the present invention with the specific embodiment of making Image Sensor as an illustration.Scrutable is that notion of the present invention can certainly be applied to the making of other semiconductor element.
In Figure 11, provide a top to be formed with the substrate 702 of Image Sensor (imagesensor) 704 and metal level 706.Above-mentioned substrate 702 is preferable can be the base material of silicon material.In one preferred embodiment, by a CMOS (Complementary Metal Oxide Semiconductor) (complementary metal-oxide semiconductor; CMOS) processing procedure forms above-mentioned Image Sensor 704.Then, utilize a metallization process (metallization process), form above-mentioned metal level 706, and electrically connect Image Sensor 704 in above-mentioned substrate 702 tops.
Above-mentioned Image Sensor 704 can be metal oxide semiconductor device or charge coupled cell (charge-coupled device; CCD).And above-mentioned metal level 706 can be copper (copper; Cu), aluminium (aluminum; Al) or tungsten (tungsten; W).
Though it should be noted that graphic middle metal level 706 only represents with individual layer.Scrutable is that above-mentioned metal level 706 also can be to comprise the multiple layer metal layer to insert and put dielectric layer, and each metal interlevel is with intraconnections (interconnection) structure of metal plug electric connection.In the embodiment of multiple layer metal layer, the metal level of the bottom can be directly to be formed in the substrate, and the metal level of top layer can be the metal level top that is stacked in the bottom, and electrically connects Image Sensor.
As shown in figure 12, then, a cover plate 708 is set in above-mentioned substrate 702 tops.In one embodiment, to provide for example be glass, quartz (quartz), for example be the macromolecular material of polyester (polyester) or the cover plate 708 of other suitable transparent material.Then, form a support portion (support member) 710 on cover plate 708, and be coated with an adhesion coating 712 on this support portion 710.Afterwards, this cover plate 708 is engaged in the top of substrate 702.
In another embodiment, also can be to be coated with adhesion coating 712 in substrate 702, above-mentioned support portion 710 is formed on the adhesion coating 712.Afterwards, above-mentioned cover plate 708 is arranged on the support portion 710, to engage this cover plate 708 in substrate 702.Above-mentioned support portion 710 is preferable can be epoxy resin (epoxy), polyimide resin (polyimide; PI), photoresist (photoresist) material or other suitable material.And above-mentioned adhesion coating 712 also can be the sticker that contains epoxy resin.
In addition, also can optionally form a protective layer (figure shows) on one and formation support portion 710 rightabout outer surfaces of above-mentioned cover plate 708, to avoid scratch.
In Figure 13, grind (grinding) above-mentioned substrate 702, with the above-mentioned substrate 702 of thinning.In one embodiment, by for example being cmp (chemicalmechanical polishing; CMP) method is ground suitable substrate 702 thickness in a back side to one of substrate 702.The thickness of the substrate 702 after the above-mentioned grinding is preferable can be between 50～750 microns (μ m).
Then, an indentation (notching) step is carried out at the back side of above-mentioned substrate 702, form a groove 714 among substrate 702.Afterwards, by for example being the mode of a continuous etch process or laser drill (laser drill), forming a hole 716 with asymmetry sidewall (asymmetrical sidewall) among substrate 702, and expose above-mentioned metal level 706.In above-mentioned continuous etched embodiment, for example can be by one first etching step, the back side of etching substrate 702, has vertical and symmetric hole (figure does not show) to form one, then, carry out one second etching step again, have the hole 716 of asymmetry with formation.Certainly, this utilizes the mode of continuous etch process, also can be to form the opening (figure does not show) with asymmetry sidewall earlier, then, runs through this opening again, exposes above-mentioned metal level 706, to form above-mentioned hole 716 with asymmetry sidewall.
In another embodiment, above-mentioned hole 716 with asymmetry sidewall also can be to form a photo anti-corrosion agent material layer (figure does not show) earlier on the back side of substrate 702, then, utilize an asymmetry light shield, the above-mentioned photo anti-corrosion agent material layer of patterning is to form a patterning photoresist layer with asymmetry sidewall.Afterwards, carry out an etching step again, to form above-mentioned hole 716 with asymmetry sidewall.
As shown in figure 13, above-mentioned hole 716 has a first side wall 7161 and one second sidewall 7162, and the surface of this first side wall 7161 and substrate 702 has a horizontal sextant angle α, and the surface of second sidewall 7162 and substrate 702 has a horizontal sextant angle β.Wherein, the horizontal sextant angle β of the horizontal sextant angle α of the first side wall 7161 of above-mentioned hole 716 and second sidewall is unequal.In one embodiment, the horizontal sextant angle α of above-mentioned the first side wall 7161 is less than or equal to 90 °, and the horizontal sextant angle β of second sidewall 7162 is less than or equal to 90 °.For example, the horizontal sextant angle α of above-mentioned the first side wall 7161 is preferable between 90 °～70 °, also can be between 85 °～50 ° and the horizontal sextant angle β of second sidewall 7162 is preferable.
Figure 14 shows the front view at the back side of the image sensing element packaging body of Figure 13.Though Figure 14 only shows a single hole 716.Scrutable is that above-mentioned hole 716 can be a plurality of holes, and centers on the zone that forms Image Sensor.
As shown in figure 14, above-mentioned groove 714 forms along precut line (dotted line), and around image sensing wafer.Above-mentioned hole 716 is formed among the substrate 702, and exposing metal layer 706.In addition, above-mentioned hole 716 has one first opening 718 that is adjacent to metal level 706 and one second opening 720 that is away from metal level 706, and wherein second opening 720 is greater than first opening 718.
In Figure 15, compliance ground forms an insulating barrier 722 on the back side of above-mentioned substrate 702, and extends among the above-mentioned hole 716.In one embodiment, utilizing for example is chemical vapour deposition (CVD) (chemical vapor deposition; CVD) method, electricity slurry heavier-duty chemical vapour deposition (CVD) (plasma enhanced chemical vapor deposition; PECVD) mode of method or coating (coating), forming for example is that the insulating barrier 722 of silica (siliconoxide), silicon nitride, silicon oxynitride (silicon oxynitride) or other suitable insulation material is on the back side of substrate 702.
Then, remove the insulating barrier 722 that partly is formed in the hole 716, with exposing metal layer 706.Afterwards, form a conductive layer 724 on the back side of above-mentioned substrate 702, and extend among the hole 716, to form a via (viahole) 725 with asymmetry sidewall.In one embodiment, utilizing for example is the mode of sputter (sputtering), evaporation (evaporating), plating (electroplating) or electroless plating (electroless plating), it for example is that the metal deposition layer (figure shows) of aluminium (aluminum), copper (copper) or nickel (nickel) is on the back side of substrate 702 that compliance forms one, and this metal deposition layer more extends among the hole 716, to electrically connect metal level 706.
It should be noted that because the sidewall of above-mentioned hole, make to be easier to metal deposition layer is formed among the hole with asymmetry.That is to say that above-mentioned hole has the opening of different size, make above-mentioned metal deposition layer be easier to be formed among the hole.Moreover this conductive layer can electrically connect the metal level in the sensing element zone by the via that passes substrate.So, the extension joint sheet (extension pad) that can not need formation one in addition and conductive layer to electrically connect.Therefore, also can reduce cost of manufacture.
Afterwards, carry out a photoetching and etch process (photolithography/etching), the above-mentioned metal deposition layer of patterning is to form above-mentioned conductive layer 724.By the step of above-mentioned pattern metal sedimentary deposit, the signal transducting wire road of the image sensing element packaging body of the follow-up formation of layout (redistributed process) again.
In Figure 16, coating soldering-resistance layer 726 is on the back side of substrate 702, and cover part conductive layer 724, with expose portion conductive layer 724.Then, form a scolder spheroid 728 on the back side of substrate 702, and electrically connect conductive layer 724.In one embodiment, after forming soldering-resistance layer 726, be coated with a scolder on the conductive layer 724 that exposes.Then, carry out a reflow (reflow) step, to form above-mentioned scolder spheroid 728.Afterwards, utilize the precut line of cutting blade (cutter), be divided into each crystal grain, to finish the making of an image sensing element packaging body 750 along each crystal grain.
Figure 16 shows the profile of an image sensing element packaging body 750 according to an embodiment of the invention.In Figure 16, the substrate 702 that provides a top to be formed with an Image Sensor 704 and a metal level 706, and this Image Sensor 704 is electrically connected to each other with metal level 706.Then, a cover plate 708 is arranged in this substrate 702.Afterwards, among above-mentioned substrate 702, formation one has the via 725 of asymmetry sidewall.And for example shown in Figure 16, a conductive layer 724 is formed on one and the sensing element 704 rightabout back sides of this substrate 702, and electrically connects metal levels 706 by above-mentioned via 725.Afterwards, a scolder spheroid 728 is formed on the back side of substrate 702, and electrically connects conductive layer 706.
It should be noted that because above-mentioned conductive layer by being formed at the via with asymmetry sidewall among the substrate, is electrically connected to metal level.Make the signal of Image Sensor to conduct to the outside, and need not walk around the outside of the substrate that forms Image Sensor by metal level, via and conductive layer.Therefore, can shorten the signal conducting path of Image Sensor.In addition, because the signal conducting path need not be formed at the outside of image sensing element packaging body, therefore, also can reduce the problem that conductive layer damages in manufacturing process.
The above only is preferred embodiment of the present invention; so it is not in order to limit scope of the present invention; any personnel that are familiar with this technology; without departing from the spirit and scope of the present invention; can do further improvement and variation on this basis, so the scope that claims were defined that protection scope of the present invention is worked as with the application is as the criterion.
Being simply described as follows of symbol in the accompanying drawing:
100: wafer 102: substrate
104: photo-sensitive cell 106: conductive electrode
108: encapsulated layer 110: wall
112: adhesion coating 114: the photo anti-corrosion agent material layer
114a: patterning photoresist layer 116: light shield
118: pattern 120: step of exposure
122: opening 123: opening figure
124: sidewall 124a: the first side wall
124b: second sidewall 126: look edge layer
128: via 130: conductor layer
132: protective layer 134: conductive projection
136: the second composition 136a: opening narrows
S1: first surface S2: second surface
702: substrate 704: Image Sensor
706: metal level 708: cover plate
710: support portion 712: adhesion coating
714: groove 716: hole
7167: 7162: the second sidewalls of the first side wall
720: the second openings of 718: the first openings
722: look edge layer 724: conductive layer
725: via 726: soldering-resistance layer
728: scolder spheroid 750: image sensing element packaging body.
Claims (20)
1. the manufacture method of an electronic element packaging body is characterized in that, comprising:
One wafer is provided, comprises a plurality of die region, to carry or to form a plurality of wafers, on the described wafer or top comprises a plurality of conductive electrodes;
One light shield is provided and implements a lithographic process to form a patterning photoresist layer on this wafer, this patterning photoresist layer comprises a plurality of openings, wherein said opening is to pattern that should light shield, this pattern comprises first composition of a relative broad, and this first composition also links second composition of at least one relative narrower;
With this patterning photoresist layer is the cover curtain, and this wafer is carried out etching, forms a plurality of holes to expose described conductive electrode, and wherein said hole has the sidewall of asymmetry; And
Remove this patterning photoresist layer.
2. the manufacture method of electronic element packaging body according to claim 1 is characterized in that, this second composition from junction to the far-end convergent.
3. the manufacture method of electronic element packaging body according to claim 1 is characterized in that, the inside that described hole passes described wafer is with as via.
4. the manufacture method of electronic element packaging body according to claim 3 is characterized in that, also comprises:
Form an insulating barrier covering described wafer, and extend on the sidewall and described conductive electrode of described via; And
Removal is positioned at this insulating barrier of described via bottom, and exposes the surface of described conductive electrode.
5. the manufacture method of electronic element packaging body according to claim 4 is characterized in that, described via comprises a first side wall and one second sidewall, wherein at least this second sidewall slope in this wafer face.
6. the manufacture method of electronic element packaging body according to claim 5 is characterized in that, this first side wall adjacent to a cutting area and essence perpendicular to this wafer face.
7. the manufacture method of electronic element packaging body according to claim 6 is characterized in that, this first side wall is corresponding to this first composition, and this second sidewall is corresponding to this second composition.
8. the manufacture method of electronic element packaging body according to claim 7 is characterized in that, also comprises forming a conductor layer on this insulating barrier, and this conductor layer extends on the surface of this second sidewall of this via and this conductive electrode.
9. the manufacture method of an electronic element packaging body is characterized in that, comprising:
One wafer is provided, comprises a plurality of die region, to carry or to form a plurality of wafers, this wafer has a first surface and a relative second surface, and wherein on this first surface or top comprises a plurality of conductive electrodes, to electrically connect described wafer;
Form an encapsulated layer, to cover the first surface of this wafer;
One light shield is provided and implements a lithographic process to form a patterning photoresist layer on the second surface of this wafer, this patterning photoresist layer comprises a plurality of openings, wherein said opening is to pattern that should light shield, this pattern comprises first composition of a relative broad, and a side of this first composition also links second composition of at least one convergent;
With this patterning photoresist layer is cover curtain, and the second surface of this wafer is carried out etching, forms a plurality of vias to expose described conductive electrode, and wherein said hole has the sidewall of asymmetry;
Remove this patterning photoresist layer;
Form an insulating barrier covering the second surface of this wafer, and extend on the sidewall and conductive electrode of described via; And
Remove the insulating barrier of described via bottom, and expose the surface of described conductive electrode.
10. the manufacture method of electronic element packaging body according to claim 9 is characterized in that, described conductive electrode comprises a conductive contact pad or a rerouting line layer.
11. the manufacture method of electronic element packaging body according to claim 10, it is characterized in that, described via comprises a first side wall and one second sidewall, and perpendicular to this wafer face, this second sidewall slope is in this wafer face adjacent to a cutting area and essence for this first side wall.
12. the manufacture method of electronic element packaging body according to claim 11 is characterized in that, this first side wall is corresponding to this first composition, and this second sidewall is corresponding to this second composition.
13. the manufacture method of electronic element packaging body according to claim 12, it is characterized in that, comprise also forming a plurality of conductor layers on this insulating barrier that described conductor layer extends on the surface of second sidewall of described via and described conductive electrode from this second surface.
14. the manufacture method of electronic element packaging body according to claim 13 is characterized in that, also comprises:
Form a protective layer inserting described via, and extend on the second surface of this wafer; And
Cut apart this wafer to isolate a plurality of encapsulated wafers.
15. an electronic element packaging body is characterized in that, comprises:
One substrate;
One metal level is positioned in this substrate;
One has the via of asymmetry sidewall, is formed among this substrate and exposes this metal level; And
One conductive layer is formed on the surface of this substrate, and extends on the asymmetry sidewall of this via to electrically connect this metal level.
16. electronic element packaging body according to claim 15, it is characterized in that, this via comprises a first side wall and one second sidewall, and the horizontal sextant angle between the surface of the horizontal sextant angle between the surface of this first side wall and this substrate and this second sidewall and this substrate is unequal.
17. electronic element packaging body according to claim 16 is characterized in that, this horizontal sextant angle of this first side wall is less than or equal to 90 degree.
18. electronic element packaging body according to claim 16 is characterized in that, this horizontal sextant angle of this second sidewall is less than or equal to 90 degree.
19. electronic element packaging body according to claim 15 is characterized in that, this via has one first opening and one second opening, and this first opening is less than this second opening.
20. the manufacture method of an electronic element packaging body is characterized in that, comprising:
Provide a top to be formed with the substrate of metal level;
Engage an encapsulated layer on the first surface of this substrate;
Be coated with a photo anti-corrosion agent material layer on the second surface of this substrate;
By an asymmetry light shield, this photo anti-corrosion agent material layer of patterning is to form a patterning photoresist layer with asymmetry sidewall; And
Carry out an etching step, the via that has the asymmetry sidewall with formation is among this substrate;
Form an insulating barrier to coat this via;
Remove this insulating barrier of part to expose this metal level in this via bottom; And
Form a conductive layer on the second surface of this substrate, and extend in this via to electrically connect this metal level.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN2008101086343A CN101355043B (en) | 2007-07-26 | 2008-05-30 | Encapsulation body for electronic element and preparation method thereof |
Applications Claiming Priority (3)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN200710136968 | 2007-07-26 | ||
| CN200710136968.7 | 2007-07-26 | ||
| CN2008101086343A CN101355043B (en) | 2007-07-26 | 2008-05-30 | Encapsulation body for electronic element and preparation method thereof |
Publications (2)
| Publication Number | Publication Date |
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| CN101355043A true CN101355043A (en) | 2009-01-28 |
| CN101355043B CN101355043B (en) | 2010-07-21 |
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| Application Number | Title | Priority Date | Filing Date |
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| CN2008101086343A Expired - Fee Related CN101355043B (en) | 2007-07-26 | 2008-05-30 | Encapsulation body for electronic element and preparation method thereof |
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| CN (1) | CN101355043B (en) |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101996953A (en) * | 2009-08-19 | 2011-03-30 | 精材科技股份有限公司 | Chip package and fabrication method thereof |
| CN102969286A (en) * | 2012-12-19 | 2013-03-13 | 苏州晶方半导体科技股份有限公司 | Semiconductor chip packaging structure and method |
| CN106098711A (en) * | 2015-04-28 | 2016-11-09 | 精材科技股份有限公司 | Wafer encapsulation body and manufacture method thereof |
| WO2017156829A1 (en) * | 2016-03-17 | 2017-09-21 | 深圳市华星光电技术有限公司 | Substrate packaging method |
-
2008
- 2008-05-30 CN CN2008101086343A patent/CN101355043B/en not_active Expired - Fee Related
Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101996953A (en) * | 2009-08-19 | 2011-03-30 | 精材科技股份有限公司 | Chip package and fabrication method thereof |
| CN101996953B (en) * | 2009-08-19 | 2016-03-02 | 精材科技股份有限公司 | Chip packing-body and manufacture method thereof |
| CN102969286A (en) * | 2012-12-19 | 2013-03-13 | 苏州晶方半导体科技股份有限公司 | Semiconductor chip packaging structure and method |
| CN102969286B (en) * | 2012-12-19 | 2016-07-20 | 苏州晶方半导体科技股份有限公司 | Semiconductor chip package and method for packing |
| CN106098711A (en) * | 2015-04-28 | 2016-11-09 | 精材科技股份有限公司 | Wafer encapsulation body and manufacture method thereof |
| WO2017156829A1 (en) * | 2016-03-17 | 2017-09-21 | 深圳市华星光电技术有限公司 | Substrate packaging method |
Also Published As
| Publication number | Publication date |
|---|---|
| CN101355043B (en) | 2010-07-21 |
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