CN101355034A - Method for forming photoetch pattern and method for manufacturing dual-damascene structure - Google Patents
Method for forming photoetch pattern and method for manufacturing dual-damascene structure Download PDFInfo
- Publication number
- CN101355034A CN101355034A CNA2007100443438A CN200710044343A CN101355034A CN 101355034 A CN101355034 A CN 101355034A CN A2007100443438 A CNA2007100443438 A CN A2007100443438A CN 200710044343 A CN200710044343 A CN 200710044343A CN 101355034 A CN101355034 A CN 101355034A
- Authority
- CN
- China
- Prior art keywords
- layer
- speed
- material layer
- rotate
- based end
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Images
Landscapes
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
- Formation Of Insulating Films (AREA)
Abstract
The invention provides a method for forming a photoetch pattern, comprising the following steps of: providing a semiconductor pedestal with a dielectric layer which is provided with a first opening; forming a first material layer in the first opening on the dielectric layer, at least filled in the first opening; forming a second material layer on the first material layer; forming a photoresist layer on the second material layer, patterning the photoresist layer to form a second opening pattern, and arranging at least one second opening pattern above the first opening. The invention also provides a method for manufacturing a dual-damascene structure. With the method, the line width of the formed photoetch pattern has excellent consistency.
Description
Technical field
The present invention relates to technical field of manufacturing semiconductors, particularly a kind of formation method and double mosaic structure manufacture method of photoengraving pattern.
Background technology
Along with the continuous development of semiconductor integrated circuit manufacturing process, integrated level is more and more higher, and live width is more and more littler, for reducing power consumption, improves response speed, and when making the interconnection line of back segment, the copper that adopts low-resistivity is as interconnect material.Because copper is difficult to etching, need to adopt dual-damascene technics to form the copper interconnecting line structure; Patent publication No. is the method that the Chinese patent application file of CN 1866495A discloses a kind of manufactured copper dual-damascene structure; in its disclosed Chinese patent application file; at first; Semiconductor substrate is provided, and this Semiconductor substrate includes dielectric layer, has dual damascene hole (being connecting hole and groove) in this dielectric layer; then; on this dual damascene hole sidewall and bottom deposit protective layer and barrier layer, then, in described dual damascene hole, form copper metal layer.
General, the method that forms the dual damascene hole of described Chinese patent application file has two kinds: connecting hole preferential (forming groove after promptly forming connecting hole earlier) or groove preferential (forming connecting hole after promptly forming groove earlier).No matter be connecting hole preferentially or the preferential method of groove, all need two step photoetching and etching technics, after dielectric layer is given birth to formation elder generation formation connecting hole, need photoetching once more and etching to form groove, perhaps form earlier after the groove, need photoetching once more and etching to form connecting hole; But, be at first to form connecting hole or groove all can to cause semiconductor-based basal surface no longer be smooth surface, the first spin coating of needs is used for the anti-reflecting layer of planarization, connecting hole in the filling semiconductor substrate or groove, and then the spin coating photoresist layer carries out follow-up photoetching process; Yet at first connecting hole of Xing Chenging or groove are owing to have different density degree at the dielectric layer diverse location, and feasible anti-reflecting layer surface smoothness variation influences the second follow-up step photoetching process.
Fig. 1 to Fig. 5 forms the generalized section of each step corresponding structure of the method for dual damascene hole for the preferential mode of existing a kind of connecting hole.
As shown in Figure 1, at first provide the semiconductor-based end 30, form first dielectric layer 32 on the described semiconductor-based end 30, form second dielectric layer 34 on described first dielectric layer 32, described second dielectric layer 104 is an advanced low-k materials.
As shown in Figure 2, spin coating photoresist layer 36 on described second dielectric layer 34 forms connecting hole pattern 38 by exposure imaging.
As shown in Figure 3, second dielectric layer 34 of the described connecting hole pattern of etching 38 bottoms forms connecting hole 38a in described second dielectric layer 34.
As shown in Figure 4, remove described first photoresist layer 36, and the anti-reflecting layer 40 that on described connecting hole 38a neutralizes second dielectric layer 34, forms, spin coating second photoresist layer 42 on described anti-reflecting layer 40 forms channel patterns 44 by exposure imaging technology.
As shown in Figure 5, the anti-reflecting layer 40 and second dielectric layer 34 of the described channel patterns of etching 44 bottoms are transferred to described channel patterns 44 in second dielectric layer 34, remove described second photoresist layer 42 and anti-reflecting layer 40, form groove 44a.
Because the connecting hole 38a in second dielectric layer 34 is in the density depth difference of diverse location, and large stretch of spacious zone is arranged in the subregion on second dielectric layer, 34 surfaces, make that the surface flatness of the anti-reflecting layer 40 of formation is relatively poor on described connecting hole 38a neutralizes second dielectric layer 34, in the comparatively intensive zone of connecting hole 38a, anti-reflecting layer 40 is thinner, and the anti-reflecting layer 40 on spacious zone large stretch of on the comparatively sparse zone of connecting hole 38a or second dielectric layer 34 is thicker, makes comparatively to produce depression in anti-reflecting layer 40 surfaces of close quarters at connecting hole 38a; This makes the consistency variation of live width of the channel patterns 44 that photoetching forms, and has reduced to form the lithographic process window of channel patterns 44.
Summary of the invention
The invention provides a kind of formation method and double mosaic structure manufacture method of photoengraving pattern, the live width of the photoengraving pattern that this method forms has consistency preferably.
The formation method of a kind of photoengraving pattern provided by the invention comprises:
The semiconductor-based end with dielectric layer, be provided, in described dielectric layer, have first opening;
Form first material layer on the described first opening neutralization medium layer, described first material layer fills up described first opening at least;
On described first material layer, form second material layer;
Form photoresist layer on described second material layer, and graphically this photoresist layer forms second patterns of openings, at least one second patterns of openings is positioned at described first opening top.
Optionally, but first material layer is a spin-on material, and the step that forms first material layer is as follows:
To described dielectric layer surface ejection first material, rotate the described semiconductor-based end with first rate;
To rotate the described semiconductor-based end greater than second speed of described first rate;
Rotate the described semiconductor-based end with third speed less than described second speed;
Stop to spray first material;
To rotate the described semiconductor-based end greater than described third speed and less than the 4th speed of second speed.
Optionally, but first material layer is a spin-on material, and the step that forms first material layer comprises:
To described dielectric layer surface ejection first material, rotate the described semiconductor-based end, make described first material fill up described first opening at least;
Return and carve described first material, make first material surface in described first opening be lower than described dielectric layer surface;
Spray first material once more, and rotate at the described semiconductor-based end, make described first material cover whole semiconductor-based basal surface.
Optionally, but second material layer is a spin-on material, and the step that forms second material layer comprises:
Spray second material to described first material surface, rotate the described semiconductor-based end with the 5th speed;
To rotate the described semiconductor-based end greater than the 6th speed of described the 5th speed;
To rotate the described semiconductor-based end less than the 7th speed of described the 6th speed;
Stop to spray second material;
To rotate the described semiconductor-based end greater than described the 7th speed and less than the 8th speed of the 6th speed.
Optionally, described first material layer and second material layer are the organic antireflecting material.
Optionally, described organic antireflecting material is DUO248.
Optionally, described second material layer is a low temperature oxide layer.
Optionally, the method that forms described low temperature oxide layer is chemical vapour deposition (CVD).
Optionally, this method further comprises: forming anti-reflecting layer before the spin coating photoresist on described second material layer.
Optionally, this method further comprises:
Described second patterns of openings is transferred in the described dielectric layer, in described dielectric layer, formed second opening;
Remove described photoresist layer, second material layer and first material layer.
The present invention also provides a kind of double mosaic structure manufacture method, comprising:
The semiconductor-based end with dielectric layer, be provided, in described dielectric layer, have connecting hole;
Form first material layer on described connecting hole neutralization medium layer, described first material layer fills up described connecting hole at least;
On described first material layer, form second material layer;
Form photoresist layer on described second material layer, and graphically this photoresist layer forms channel patterns, at least one channel patterns is positioned at described connecting hole top;
Described channel patterns is transferred in the described dielectric layer, in described dielectric layer, formed groove;
Remove described photoresist layer, second material layer and first material layer.
Optionally, but first material layer is a spin-on material, and the step that forms first material layer is as follows:
To described dielectric layer surface ejection first material, rotate the described semiconductor-based end with first rate;
To rotate the described semiconductor-based end greater than second speed of described first rate;
Rotate the described semiconductor-based end with third speed less than described second speed;
Stop to spray first material;
To rotate the described semiconductor-based end greater than described third speed and less than the 4th speed of second speed.
Optionally, but first material layer is a spin-on material, and the step that forms first material layer comprises:
To described dielectric layer surface ejection first material, rotate the described semiconductor-based end, make described first material fill up described connecting hole at least;
Return and carve described first material, make first material surface in the described connecting hole be lower than described dielectric layer surface;
Spray first material once more, and rotate at the described semiconductor-based end, make described first material cover whole semiconductor-based basal surface.
Optionally, but second material layer is a spin-on material, and the step that forms second material layer comprises:
Spray second material to described first material surface, rotate the described semiconductor-based end with the 5th speed;
To rotate the described semiconductor-based end greater than the 6th speed of described the 5th speed;
To rotate the described semiconductor-based end less than the 7th speed of described the 6th speed;
Stop to spray second material;
To rotate the described semiconductor-based end greater than described the 7th speed and less than the 8th speed of the 6th speed.
Optionally, described first material layer and second material layer are the organic antireflecting material.
Optionally, described organic antireflecting material is DUO248.
Optionally, described second material layer is a low temperature oxide layer.
Optionally, the method that forms described low temperature oxide layer is chemical vapour deposition (CVD).
Optionally, this method further comprises: forming anti-reflecting layer before the spin coating photoresist on described second material layer.
Optionally, this method further comprises: fill metal material in described connecting hole and groove.
The present invention also provides a kind of double mosaic structure manufacture method, comprising:
The semiconductor-based end with dielectric layer, be provided, in described dielectric layer, have groove;
Form first material layer on described groove neutralization medium layer, described first material layer fills up described groove at least;
On described first material layer, form second material layer;
Form photoresist layer on described second material layer, and graphically this photoresist layer forms the connecting hole pattern, at least one connecting hole pattern is positioned at described groove top;
Described connecting hole design transfer in described dielectric layer, is formed connecting hole in described dielectric layer;
Remove described photoresist layer, second material layer and first material layer.
Optionally, but described first material layer is a spin-on material, and the step that forms first material layer is as follows:
To described dielectric layer surface ejection first material, rotate the described semiconductor-based end with first rate;
To rotate the described semiconductor-based end greater than second speed of described first rate;
Rotate the described semiconductor-based end with third speed less than described second speed;
Stop to spray first material;
To rotate the described semiconductor-based end greater than described third speed and less than the 4th speed of second speed.
Optionally, but described first material layer is a spin-on material, and the step that forms first material layer comprises:
To described dielectric layer surface ejection first material, rotate the described semiconductor-based end, make described first material fill up described groove at least;
Return and carve described first material, make first material surface in the described slot hole be lower than described dielectric layer surface;
Spray first material once more, and rotate at the described semiconductor-based end, make described first material cover whole semiconductor-based basal surface.
Optionally, but described second material layer is a spin-on material, and the step that forms second material layer comprises:
Spray second material to described first material surface, rotate the described semiconductor-based end with the 5th speed;
To rotate the described semiconductor-based end greater than the 6th speed of described the 5th speed;
To rotate the described semiconductor-based end less than the 7th speed of described the 6th speed;
Stop to spray second material;
To rotate the described semiconductor-based end greater than described the 7th speed and less than the 8th speed of the 6th speed.
Optionally, described first material layer and second material layer are the organic antireflecting material.
Optionally, described organic antireflecting material is DUO248.
Optionally, described second material layer is a low temperature oxide layer.
Optionally, the method that forms described low temperature oxide layer is chemical vapour deposition (CVD).
Optionally, this method further comprises: forming anti-reflecting layer before the spin coating photoresist on described second material layer.
Optionally, this method further comprises: fill metal material in described connecting hole and groove.
Compared with prior art, the present invention has the following advantages:
By on dielectric layer, forming first material layer and second material layer with first opening, can reduce since the density difference of first opening to the influence of the flatness on the surface of material layer; After the first material layer material is filled first opening, the surface of this first material layer is more smooth than the surface of dielectric layer, thereby, the flatness of this first material surface is littler to the flatness influence on the surface of second material layer on its upper strata, thereby, the flatness on the surface of second material layer that forms is higher, and promptly second material layer has reduced because the density difference of first opening in the dielectric layer to the influence of material layer, makes second material layer have higher flatness by forming; The surface flatness of second material layer is higher, make that the consistency of line width of second patterns of openings that forms by photoetching process (being connecting hole pattern in the preferential dual-damascene technics of channel patterns in the preferential dual-damascene technics of connecting hole or groove) is better on second material layer, can improve the process window that forms second patterns of openings, improve the stability of photoetching process and maintainable, and then can improve the stability of yield of the semiconductor device of formation;
Spin coating speed when forming first material layer and second material layer by adjusting also can further improve flatness.
Description of drawings
Fig. 1 to Fig. 5 forms the generalized section of each step corresponding structure of the method for dual damascene hole for the preferential mode of existing a kind of connecting hole;
Fig. 6 to 12 is the generalized section of each step corresponding structure of the embodiment of double mosaic structure manufacture method of the present invention.
Embodiment
Below in conjunction with accompanying drawing the specific embodiment of the present invention is described in detail.
When in the smooth dielectric layer of air spots, forming opening, for example, when in dielectric layer, forming second opening,, can influence the photoetching process that forms second opening because first opening causes the dielectric layer air spots smooth with first opening; Need on dielectric layer and in first opening, be formed for the material layer of planarization, but because the density degree difference of first opening diverse location in dielectric layer, this makes the surface flatness that forms material layer descend.
The invention provides a kind of method, at first form first material layer that fills up first opening at least, form second material layer then on first material layer, wherein said first material layer is the organic antireflecting material, and this first material layer forms by the method for spin coating; Second material layer is organic antireflection layer or low temperature oxide layer.By on the semiconductor-based end, forming first material layer and second material layer, can obtain comparatively smooth surface, form patterned photoresist layer on this surface then, can obtain consistency of line width second patterns of openings preferably; Further, this second patterns of openings is transferred in the described dielectric layer, can be obtained consistency of line width second opening preferably.
Below in conjunction with Fig. 6 to Figure 12 method of the present invention is described in detail, Fig. 6 to Figure 12 is the generalized section of each step corresponding structure of the embodiment of the preferential double mosaic structure manufacture method of this present invention's connecting hole, wherein, connecting hole is first opening, and groove is second opening.
Generalized section as shown in Figure 6 provides the semiconductor-based end 10, has semiconductor device (not shown) and dielectric layer 12 in the described semiconductor-based end 10, in described dielectric layer 12, have comparatively intensive connecting hole 14 and and isolated connecting hole 14a;
Wherein, described dielectric layer 12 is an advanced low-k materials, for example, described dielectric layer 12 can be fluorine silex glass, phosphorosilicate glass, Pyrex, boron-phosphorosilicate glass, black diamond (BlackDiamond, BD) a kind of in, the method that forms dielectric layer 12 can be a kind of in physical vapour deposition (PVD), chemical vapour deposition (CVD), the ald.
On described dielectric layer 12, cover layer 13 can be arranged, not be subjected to the damage of technologies such as etching, cleaning in order to the dielectric layer 12 of protection low-k; Described cover layer 13 can be a kind of in silicon nitride, carborundum, the silicon dioxide.
Have etching stop layer 11 12 times at described dielectric layer, described etching stop layer 11 is as the etching terminal detection layers when forming connecting hole 14 and 14a; The material of described etching stop layer 11 can be a kind of in silica, carbon nitrogen silicon compound, the silicon nitride, and wherein, the method that forms described etching stop layer 11 is a kind of in physical vapour deposition (PVD), chemical vapour deposition (CVD), the ald.
The live width of described connecting hole 14 and 14a is identical, is in the diverse location of dielectric layer 12; The degree of depth of described connecting hole 14 and 14a is identical with the thickness of dielectric layer 12, and the metal carbonyl conducting layer (not shown) at the semiconductor-based end 10 is exposed in the bottom of described connecting hole 14 and 14a;
Form described connecting hole 14 and 14a by photoetching and etching, wherein, the method for etching can be reactive ion etching (Reactive Ion Etch).
Described connecting hole 14 and 14a are used to form attachment plug, connect the metal carbonyl conducting layer at the semiconductor-based end 10 and the metal carbonyl conducting layer on upper strata; The filled conductive material can form attachment plug in described connecting hole 14 and 14a.
As shown in Figure 7, form first material layer 16 on described dielectric layer 12, among connecting hole 14 and the 14a, wherein, described first material layer 16 fills up described connecting hole 14 and 14a at least.
Among the embodiment therein, but described first material layer 16 is a spin-on material, for example is organic antireflecting material DUO248; But the step of first material layer 16 that forms this spin coating is as follows:
Step 1, to surface, the described semiconductor-based ends 10 (being dielectric layer 12 surfaces) ejection first material, rotate the described semiconductor-based end with first rate,
The described semiconductor-based end 10, placed on the support column of spin-coating equipment, and pass through the bottom at the described semiconductor-based end 10 of vacuum suction; The first material nozzle is moved to the middle upper part position at the described semiconductor-based end 10, and make the described semiconductor-based end of described nozzle distance have certain distance.
By motor driven, make described support column drive the semiconductor-based end 10 with slower first rate rotation, described nozzle is to the described semiconductor-based end 10 surface ejections first material simultaneously.By the centrifugal action of rotation, first material of ejection is filled among connecting hole 14 and the 14a, and is covered with whole dielectric layer 12 surfaces along dielectric layer 12 (or cover layer 13) surface outside the moving slowly at the described semiconductor-based end 10.
Step 2, continuation are to the described semiconductor-based ends 10 surface ejections first material, to rotate the described semiconductor-based end 10 greater than second speed of described first rate;
Because connecting hole 14 and 14a in the described dielectric layer 12 are inequality in the density degree of diverse location, cause the resistance difference of the diverse location of dielectric layer 12 to described first material, when rotating with slower first rate, first material is in different zone, dielectric layer 12 surfaces, the flow rate difference of position, and first material thickness everywhere that has caused being formed on the dielectric layer 12 is inequality;
For example, when rotating with first rate, may occur connecting hole 14 and 14a fill out discontented, and other smooth thicker phenomenon of spacious regional first material on dielectric layer 12 surfaces;
By the rotation of the second higher speed, make thicker first material in dielectric layer 12 surface portion zones to thin zone flows, perhaps be thrown out of at semiconductor-based the end 10; Continue the ejection antireflection material simultaneously and replenish, and make it to be filled among described connecting hole that does not fill up 14 and the 14a;
Because this second speed is bigger, thereby edge, the semiconductor-based ends 10 can assemble the first more material, and the middle body on dielectric layer 12 surfaces is less, and first material surface on whole dielectric layer 12 surfaces is spill.
Step 3, rotate the described semiconductor-based end 10 with third speed less than described second speed;
The speed of rotation that changes the described semiconductor-based end 10 is to third speed, and described third speed continues ejection first material simultaneously less than described second speed;
By reducing the speed of rotation, make first material reflow on described dielectric layer 12 surfaces; Continue ejection first material in addition and further fill sunk area.
The speed of rotation at the described semiconductor-based end 10 is dropped to lower third speed in the short period of time by the second higher speed, first material to described dielectric layer 12 surfaces refluxes, make first material part that is positioned at the edge move, can play planarization effect and further effect of filling connecting hole 14 and 14a to the center direction of described dielectric layer 12.
In addition, described nozzle continues to spray first material and make it slowly outwards mobile to the central authorities of dielectric layer 12, and both are in conjunction with the first material flatness that improves described dielectric layer 12 surfaces, and raising is to filling, the covering power of described connecting hole 14 and 14a.
Step 4, stop to spray first material;
Step 5, to rotate the described semiconductor-based end greater than described third speed and less than the 4th speed of second speed.
The first unnecessary material of dielectric layer 12 surfaces is got rid of in the rotation of the 4th speed by the long period.
First material is carried out baking process, strengthen the adhesion and the transpiring moisture of described antireflection material and dielectric layer, form first material layer 16.
Because the connecting hole density difference of diverse location in the dielectric layer 12, be subjected to the influence of the different connecting hole of density degree, make the degree of planarization on the surface that forms first material layer 16 relatively poor, the spin coating during by described a series of different rates can improve the flatness of described first material layer 16.
In a further embodiment, it is as follows to form the step of described first flatness layer 16:
At first,, rotate the described semiconductor-based end 10, make described first material fill up described connecting hole 14 and 14a at least to described dielectric layer 12 surface ejections first material;
Then, return to carve described first material, make first material surface among connecting hole 14 and the 14a be lower than described dielectric layer 12 surfaces, but be higher than described connecting hole 14 the degree of depth 2/3rds;
Spray first material to described dielectric layer 12 surfaces once more, and rotate at the described semiconductor-based end 10, make described first material cover dielectric layer 12 surfaces at the whole semiconductor-based end 10;
By filling part first material in connecting hole 14 and 14a at first, make when filling first material once more, the degree of depth of connecting hole 14 and 14a is less, with this influence of different surface flatnesses to first material layer 16 that reduces the density degree of connecting hole 14 and 14a, can improve flatness.
As shown in Figure 8, on described first material layer 16, form second material layer 18;
Among the embodiment therein, but described second material layer 18 is the organic antireflecting material of spin coating, for example can be DUO248.
The step of described second material layer 18 of spin coating is as follows:
To described first material layer, 16 surface ejections, second material, rotate the described semiconductor-based end 10 with the 5th speed;
To rotate the described semiconductor-based end 10 greater than the 6th speed of described the 5th speed;
To rotate the described semiconductor-based end 10 less than the 7th speed of described the 6th speed;
Stop to spray second material;
To rotate the described semiconductor-based end 10 greater than described the 7th speed and less than the 8th speed of the 6th speed.
Because the surface of the more described dielectric layer 12 in surface of described first material layer 16 is more smooth, thereby, the flatness on described first material layer 16 surfaces is littler to the flatness influence on second material layer, 18 surfaces on its upper strata, thereby, the flatness on the surface of second material layer 18 that forms is higher, and also promptly second material layer 18 has reduced because connecting hole 14 in the dielectric layer 12 and the different influences to material layer of density of 14a by forming;
Further, can on described second material layer 18, form the 3rd, the 4th ... material layer, further improve evenness;
In other embodiment, described second material layer 18 is a low temperature oxide layer, and the method that forms described low temperature oxide layer is chemical vapour deposition (CVD), for example can be plasma reinforced chemical vapour deposition, and the temperature of deposition is 100 to 250 degrees centigrade;
As shown in Figure 9, on described second material layer 18, form photoresist layer 20, and, in described photoresist layer 10, form channel patterns 22 by the graphical described photoresist layer 20 of exposure imaging technology, wherein, have at least a channel patterns 22 to be positioned at the top of one of them connecting hole 14 or 14a;
In other embodiments, before forming photoresist layer 20, can form anti-reflecting layer (figure does not show) on now described second material layer 18, and then on described anti-reflecting layer, form photoresist layer 20.
Because the surface flatness of second material layer 18 is higher, the different influences to this surface flatness of connecting hole 14 and 14a density degree are less, make that the consistency of live width of the channel patterns 22 that forms by photoetching process is better, thereby improved the process window that forms channel patterns 22;
Particularly for littler technology node, the photoetching process of the channel patterns in the technology node of 65nm for example, the depth of focus is less, make process window less, by improving the flatness on the surface under the photoresist layer 20, can increase process window, improve the stability of photoetching process and maintainable, and then can improve the stability of yield of the semiconductor device of formation.
As shown in figure 10, second planarization 18, first material layer 16 and the part dielectric layer 12 of the described channel patterns of etching 22 bottoms are transferred to described channel patterns 22 in the described dielectric layer 12, form groove 24 in described dielectric layer 12.
Then, remove photoresist layer 20, second material layer 18, first material layer 16 by plasma dry etching and wet-cleaned, as shown in figure 11.
Further, as shown in figure 12, fill metal material in described connecting hole 14,14a and groove 22, copper for example promptly forms the dual-damascene structure of copper.
In other embodiments, also can form groove earlier, the back forms connecting hole, other step with form connecting hole earlier after the step of formation trench process identical, repeat no more.
Though the present invention with preferred embodiment openly as above; but it is not to be used for limiting the present invention; any those skilled in the art without departing from the spirit and scope of the present invention; can make possible change and modification, so protection scope of the present invention should be as the criterion with the scope that claim of the present invention was defined.
Claims (30)
1, a kind of formation method of photoengraving pattern is characterized in that, comprising:
The semiconductor-based end with dielectric layer, be provided, in described dielectric layer, have first opening;
Form first material layer on the described first opening neutralization medium layer, described first material layer fills up described first opening at least;
On described first material layer, form second material layer;
Form photoresist layer on described second material layer, and graphically this photoresist layer forms second patterns of openings, at least one second patterns of openings is positioned at described first opening top.
2, the formation method of photoengraving pattern as claimed in claim 1 is characterized in that, but first material layer is a spin-on material, and the step that forms first material layer is as follows:
To described dielectric layer surface ejection first material, rotate the described semiconductor-based end with first rate;
To rotate the described semiconductor-based end greater than second speed of described first rate;
Rotate the described semiconductor-based end with third speed less than described second speed;
Stop to spray first material;
To rotate the described semiconductor-based end greater than described third speed and less than the 4th speed of second speed.
3, the formation method of photoengraving pattern as claimed in claim 1 is characterized in that, but first material layer is a spin-on material, and the step that forms first material layer comprises:
To described dielectric layer surface ejection first material, rotate the described semiconductor-based end, make described first material fill up described first opening at least;
Return and carve described first material, make first material surface in described first opening be lower than described dielectric layer surface;
Spray first material once more, and rotate at the described semiconductor-based end, make described first material cover whole semiconductor-based basal surface.
4, the formation method of photoengraving pattern as claimed in claim 1 is characterized in that, but second material layer is a spin-on material, and the step that forms second material layer comprises:
Spray second material to described first material surface, rotate the described semiconductor-based end with the 5th speed;
To rotate the described semiconductor-based end greater than the 6th speed of described the 5th speed;
To rotate the described semiconductor-based end less than the 7th speed of described the 6th speed;
Stop to spray second material;
To rotate the described semiconductor-based end greater than described the 7th speed and less than the 8th speed of the 6th speed.
5, as the formation method of the described photoengraving pattern of the arbitrary claim of claim 1 to 4, it is characterized in that: described first material layer and second material layer are the organic antireflecting material.
6, the formation method of photoengraving pattern as claimed in claim 5 is characterized in that: described organic antireflecting material is DUO248.
7, the formation method of photoengraving pattern as claimed in claim 1 is characterized in that: described second material layer is a low temperature oxide layer.
8, the formation method of photoengraving pattern as claimed in claim 7 is characterized in that: the method that forms described low temperature oxide layer is chemical vapour deposition (CVD).
9, the formation method of photoengraving pattern as claimed in claim 1 is characterized in that, this method further comprises: forming anti-reflecting layer before the spin coating photoresist on described second material layer.
10, the formation method of photoengraving pattern as claimed in claim 1 is characterized in that, this method further comprises:
Described second patterns of openings is transferred in the described dielectric layer, in described dielectric layer, formed second opening;
Remove described photoresist layer, second material layer and first material layer.
11, a kind of double mosaic structure manufacture method is characterized in that, comprising:
The semiconductor-based end with dielectric layer, be provided, in described dielectric layer, have connecting hole;
Form first material layer on described connecting hole neutralization medium layer, described first material layer fills up described connecting hole at least;
On described first material layer, form second material layer;
Form photoresist layer on described second material layer, and graphically this photoresist layer forms channel patterns, at least one channel patterns is positioned at described connecting hole top;
Described channel patterns is transferred in the described dielectric layer, in described dielectric layer, formed groove;
Remove described photoresist layer, second material layer and first material layer.
12, double mosaic structure manufacture method as claimed in claim 11 is characterized in that, but first material layer is a spin-on material, and the step that forms first material layer is as follows:
To described dielectric layer surface ejection first material, rotate the described semiconductor-based end with first rate;
To rotate the described semiconductor-based end greater than second speed of described first rate;
Rotate the described semiconductor-based end with third speed less than described second speed;
Stop to spray first material;
To rotate the described semiconductor-based end greater than described third speed and less than the 4th speed of second speed.
13, double mosaic structure manufacture method as claimed in claim 11 is characterized in that, but first material layer is a spin-on material, and the step that forms first material layer comprises:
To described dielectric layer surface ejection first material, rotate the described semiconductor-based end, make described first material fill up described connecting hole at least;
Return and carve described first material, make first material surface in the described connecting hole be lower than described dielectric layer surface;
Spray first material once more, and rotate at the described semiconductor-based end, make described first material cover whole semiconductor-based basal surface.
14, double mosaic structure manufacture method as claimed in claim 11 is characterized in that, but second material layer is a spin-on material, and the step that forms second material layer comprises:
Spray second material to described first material surface, rotate the described semiconductor-based end with the 5th speed;
To rotate the described semiconductor-based end greater than the 6th speed of described the 5th speed;
To rotate the described semiconductor-based end less than the 7th speed of described the 6th speed;
Stop to spray second material;
To rotate the described semiconductor-based end greater than described the 7th speed and less than the 8th speed of the 6th speed.
15, as the described double mosaic structure manufacture method of the arbitrary claim of claim 11 to 14, it is characterized in that: described first material layer and second material layer are the organic antireflecting material.
16, double mosaic structure manufacture method as claimed in claim 15 is characterized in that: described organic antireflecting material is DUO248.
17, double mosaic structure manufacture method as claimed in claim 11 is characterized in that: described second material layer is a low temperature oxide layer.
18, double mosaic structure manufacture method as claimed in claim 17 is characterized in that: the method that forms described low temperature oxide layer is chemical vapour deposition (CVD).
19, double mosaic structure manufacture method as claimed in claim 11 is characterized in that, this method further comprises: forming anti-reflecting layer before the spin coating photoresist on described second material layer.
20, double mosaic structure manufacture method as claimed in claim 11 is characterized in that, this method further comprises: fill metal material in described connecting hole and groove.
21, a kind of double mosaic structure manufacture method is characterized in that, comprising:
The semiconductor-based end with dielectric layer, be provided, in described dielectric layer, have groove;
Form first material layer on described groove neutralization medium layer, described first material layer fills up described groove at least;
On described first material layer, form second material layer;
Form photoresist layer on described second material layer, and graphically this photoresist layer forms the connecting hole pattern, at least one connecting hole pattern is positioned at described groove top;
Described connecting hole design transfer in described dielectric layer, is formed connecting hole in described dielectric layer;
Remove described photoresist layer, second material layer and first material layer.
22, double mosaic structure manufacture method as claimed in claim 21 is characterized in that, but described first material layer is a spin-on material, and the step that forms first material layer is as follows:
To described dielectric layer surface ejection first material, rotate the described semiconductor-based end with first rate;
To rotate the described semiconductor-based end greater than second speed of described first rate;
Rotate the described semiconductor-based end with third speed less than described second speed;
Stop to spray first material;
To rotate the described semiconductor-based end greater than described third speed and less than the 4th speed of second speed.
23, double mosaic structure manufacture method as claimed in claim 21 is characterized in that, but described first material layer is a spin-on material, and the step that forms first material layer comprises:
To described dielectric layer surface ejection first material, rotate the described semiconductor-based end, make described first material fill up described groove at least;
Return and carve described first material, make first material surface in the described slot hole be lower than described dielectric layer surface;
Spray first material once more, and rotate at the described semiconductor-based end, make described first material cover whole semiconductor-based basal surface.
24, double mosaic structure manufacture method as claimed in claim 21 is characterized in that, but described second material layer is a spin-on material, and the step that forms second material layer comprises:
Spray second material to described first material surface, rotate the described semiconductor-based end with the 5th speed;
To rotate the described semiconductor-based end greater than the 6th speed of described the 5th speed;
To rotate the described semiconductor-based end less than the 7th speed of described the 6th speed;
Stop to spray second material;
To rotate the described semiconductor-based end greater than described the 7th speed and less than the 8th speed of the 6th speed.
25, as the described double mosaic structure manufacture method of the arbitrary claim of claim 21 to 24, it is characterized in that: described first material layer and second material layer are the organic antireflecting material.
26, double mosaic structure manufacture method as claimed in claim 25 is characterized in that: described organic antireflecting material is DUO248.
27, double mosaic structure manufacture method as claimed in claim 21 is characterized in that: described second material layer is a low temperature oxide layer.
28, double mosaic structure manufacture method as claimed in claim 27 is characterized in that: the method that forms described low temperature oxide layer is chemical vapour deposition (CVD).
29, double mosaic structure manufacture method as claimed in claim 21 is characterized in that, this method further comprises: forming anti-reflecting layer before the spin coating photoresist on described second material layer.
30, double mosaic structure manufacture method as claimed in claim 21 is characterized in that, this method further comprises: fill metal material in described connecting hole and groove.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNA2007100443438A CN101355034A (en) | 2007-07-27 | 2007-07-27 | Method for forming photoetch pattern and method for manufacturing dual-damascene structure |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNA2007100443438A CN101355034A (en) | 2007-07-27 | 2007-07-27 | Method for forming photoetch pattern and method for manufacturing dual-damascene structure |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN101355034A true CN101355034A (en) | 2009-01-28 |
Family
ID=40307765
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CNA2007100443438A Pending CN101355034A (en) | 2007-07-27 | 2007-07-27 | Method for forming photoetch pattern and method for manufacturing dual-damascene structure |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN101355034A (en) |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102376631A (en) * | 2010-08-24 | 2012-03-14 | 中芯国际集成电路制造(上海)有限公司 | Method for producing dual damascene structure |
| CN104347479A (en) * | 2013-07-29 | 2015-02-11 | 中芯国际集成电路制造(上海)有限公司 | Etching method for two-damascus structure |
| CN116230507A (en) * | 2023-05-09 | 2023-06-06 | 粤芯半导体技术股份有限公司 | Method for preparing semiconductor structure |
-
2007
- 2007-07-27 CN CNA2007100443438A patent/CN101355034A/en active Pending
Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102376631A (en) * | 2010-08-24 | 2012-03-14 | 中芯国际集成电路制造(上海)有限公司 | Method for producing dual damascene structure |
| CN102376631B (en) * | 2010-08-24 | 2013-08-14 | 中芯国际集成电路制造(北京)有限公司 | Method for producing dual damascene structure |
| CN104347479A (en) * | 2013-07-29 | 2015-02-11 | 中芯国际集成电路制造(上海)有限公司 | Etching method for two-damascus structure |
| CN104347479B (en) * | 2013-07-29 | 2017-11-14 | 中芯国际集成电路制造(上海)有限公司 | Engraving method for double damask structure |
| CN116230507A (en) * | 2023-05-09 | 2023-06-06 | 粤芯半导体技术股份有限公司 | Method for preparing semiconductor structure |
| CN116230507B (en) * | 2023-05-09 | 2023-07-28 | 粤芯半导体技术股份有限公司 | Method for preparing semiconductor structure |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| KR100421055B1 (en) | Method for forming metal interconnection layer of semiconductor device | |
| CN100444329C (en) | Inlaid structure and its forming method | |
| CN100353542C (en) | Integrated circuit, its forming method, and electronic assembly | |
| US6888251B2 (en) | Metal spacer in single and dual damascene processing | |
| US7078814B2 (en) | Method of forming a semiconductor device having air gaps and the structure so formed | |
| CN100375249C (en) | Method of filling opening, dielectric layer opening and trench | |
| US5883014A (en) | Method for treating via sidewalls with hydrogen plasma | |
| CN100350592C (en) | Methods of fabricating semiconductor device having slope at lower sides of interconnection hole | |
| CN102683274A (en) | Air-gap process applied to copper interconnection | |
| US6146986A (en) | Lithographic method for creating damascene metallization layers | |
| US20100105202A1 (en) | Method of forming an interconnect structure | |
| US6960519B1 (en) | Interconnect structure improvements | |
| CN101207018A (en) | Method for forming anti-reflecting layer and method for manufacturing dual mosaic structure | |
| CN101355034A (en) | Method for forming photoetch pattern and method for manufacturing dual-damascene structure | |
| CN103050433A (en) | Semiconductor contact hole structure and manufacturing method thereof | |
| CN102087993B (en) | Groove forming method | |
| US7709965B2 (en) | Metal line of semiconductor device and method of manufacturing the same | |
| KR101402962B1 (en) | Method of forming air-gap on the metal interconnect of semiconductor | |
| CN101494191B (en) | Manufacturing method for dual damascene structure | |
| CN110648960B (en) | MRAM device and manufacturing method thereof | |
| CN103956333A (en) | TSV, M1 and CT metal layer one-time forming method based on via middle manufacturing method | |
| US7326632B2 (en) | Method for fabricating metal wirings of semiconductor device | |
| KR100395905B1 (en) | Deposition method for bitline and dielectric layer of semiconductor device | |
| KR100842670B1 (en) | Fabricating method semiconductor device | |
| KR100571404B1 (en) | Method for manufacturing metal plug of semiconductor device |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| C12 | Rejection of a patent application after its publication | ||
| RJ01 | Rejection of invention patent application after publication |
Open date: 20090128 |