CN101350709B - Method and device for synchronizing block and frame - Google Patents
Method and device for synchronizing block and frame Download PDFInfo
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- CN101350709B CN101350709B CN200710137821XA CN200710137821A CN101350709B CN 101350709 B CN101350709 B CN 101350709B CN 200710137821X A CN200710137821X A CN 200710137821XA CN 200710137821 A CN200710137821 A CN 200710137821A CN 101350709 B CN101350709 B CN 101350709B
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Abstract
The present invention relates to the field of communication, and discloses a block and frame synchronization method, and a device thereof. When the input error rate is relatively high, the synchronization can be completed more accurately. In the method, N bit groups are detected; the times of the appearance of bit segments with the same position as the block synchronization head in each bit group is summarized; if only the statistic value of one position is more than the first threshold, the position can be used for arranging the block synchronization head. The receiving sequences which consist of M block synchronization heads are displaced for times of M minus 1 in a circular way, so as to acquire various possible results of the circular displacement of the receiving sequence; the relevant calculation of the results of the circular displacement and the reference sequence is completed; the relevant values can be used for quantitative indication of the degree of proximity between the results of the circular displacement and the reference sequence; the relevant values of K bit groups corresponding to the times of the circular displacement are summarized, so as to reliably acquire the result of the circular displacement which is closest to the reference sequence, and further to accurately acquire the position of the frame.
Description
Technical field
The present invention relates to the communications field, particularly piece and frame synchronizing.
Background technology
Ethernet passive optical network (Ethernet Passive Optical Network is called for short " EPON ") access technology is a kind of reasonable access technology, and its major advantage is to safeguard simple, lower, higher transmission bandwidth and the high performance-price ratio of cost.
But,, in this network, do not use components and parts with amplification and relay function because EPON is a kind of technology that adopts the passive light transmission.Therefore the transmission range and the number of branches of EPON network depend on power budget and various loss.Along with the increase of transmission range or number of branches, the signal to noise ratio of transmission data (Signal Noise Ratio is called for short " SNR ") reduces gradually, and the error rate of the data of transmission increases gradually.In order to address this problem, in the EPON system, to have introduced forward error correction (ForwardError Correction is called for short " FEC ") technology and improved the antijamming capability of system, thereby increase the power budget of system.
Yet 64b/66b and 64b/65b are two kinds of line coding mechanism that code efficiency is higher, have used the scrambler mode that has non-scrambler synchronization character and control character.In EPON system physical coding sublayer (Physical Coding Sublayer is called for short " PCS "), used the line coding technology to improve the accuracy of transfer of data.
FEC information frame organization plan enters the process 64b/66b of the data elder generation line coding of PCS layer as shown in Figure 1 at present, and forming with 66 bits is the line coding piece of unit.The 64b/66b encoding mechanism is on the basis of 64 Bit data information, has increased the synchronous head of 2 bits.The synchronous head of this 2 bit has only " 01 " or " 10 " these two kinds possibilities.Wherein, synchronous head is that " 01 " expression 64 bits all are data message; Synchronous head is for comprising data message and control information in " 10 " expression 64 bit informations; Synchronous head then represents to have taken place in the transmission course mistake for " 00 " or " 11 ".At receiving terminal, need the synchronous head of dibit " 01 " in the 64b/66b line coding or " 10 " to realize 64b/66b line coding piece (blocksynchronization) synchronously, so that judge the type of data in the line coding piece according to synchronous head, realize information frame (frame synchronization) synchronously then, so that follow-up decoding to FEC.
The piece of prior art realization principle synchronous and FEC codeword information frame synchronization is as follows respectively:
The piece synchronization principles is: at receiving terminal, and the cache register that a length is set is 66 bits, before beginning synchronously, all positions in the cache register are carried out initialization and are set to " True (very) ".Then the Bit data imported and the Bit data of its front are compared,, then be changed to " false (vacation) " with regard to corresponding position in the cache register if this 2 Bit data is identical.Because 2 Bit datas of 64b/66b encoding block synchronous head only can be inequalities, then after the data of input some, the value of the position of certain of cache register is " True " always, this position just is defined as the initial position of synchronous head of 64b/66b encoding block so, thereby realizes that piece is synchronous.
And the synchronous principle of the mechanism of FEC information frame synchronizing process and piece is similar, and difference is to be increased to the length of cache register the length of a FEC information frame.Before carrying out synchronously, all positions of this cache register are changed to " True ", the Bit data of input and the Bit data of its front are compared, utilize the characteristic and the identical characteristic of check block synchronous head of 64b/66b encoding block synchronous head inequality, can determine numerical value in this cache register always for the position of " True " is the position of synchronous head, thereby realize that the FEC information frame is synchronous.
In addition, also has a kind of fairly simple FEC information frame method for synchronous, this method only scans the check information piece synchronous head in the fec frame, because 2 bit synchronous heads of check information piece are identical forever, value on the correspondence position of cache register can be true always, determine the starting position of check information piece like this,, realize that fec frame is synchronous from determining the original position of fec frame.
If the synchronous head of one of them 64b/66b line coding piece or FEC check information piece makes a mistake, the state of " True " may not can in the cache register appears, and it is synchronous or fec frame is synchronous that just can't finish piece this moment.Generally take again the cache register initialization is carried out simultaneous operation then again and solved.Yet the present inventor finds that when the interference in channel was strong, the error rate that receives data was higher, and the probability of synchronous head mistake is also very high like this, makes can't finish accurately synchronously even can't realize synchronous.In addition, during owing to the synchronous head mistake, can only will increase time delay like this, influence the performance of system by carrying out simultaneous operation after reinitializing.
Summary of the invention
The technical problem underlying that embodiment of the present invention will solve provides a kind of, frame synchornization method and device, makes in the input error rate when higher, can finish more accurately synchronously.
For solving the problems of the technologies described above, embodiments of the present invention provide a kind of block synchronization method, may further comprise the steps:
An initialization L counter, each counter are corresponding respectively to be a position in the bit group of L in length, and the piece synchronous head appears at one of L the pairing L of counter position, L＞1;
N bit group detected, each bit group length is L, if detect and one of the piece synchronous head of presetting identical bit fragment, then in L counter, select the counter of this bit fragment position correspondence, increase the count value of selected counter; N＞1;
If the count value of having only a counter in L counter is greater than first thresholding, then the pairing location determination of this counter is the position of piece synchronous head; Wherein the length of piece is the L bit.
Embodiments of the present invention also provide a kind of synchronizer, comprising:
L counter, each counter are corresponding respectively to be a position in the bit group of L in length, and the piece synchronous head appears at one of L the pairing L of counter position, L＞1;
Detection module, be used for N bit group detected, each bit group length is L, if detect and one of the piece synchronous head of presetting identical bit fragment, then in L counter, select the counter of this bit fragment position correspondence, indicate selected counter to increase count value;
Initialization module is used for before detection module detects L counter being carried out initialization;
Piece synchronization decisions device, be used for detection module finish detect judge whether L counter have only a counter in the back count value greater than first thresholding, if then the pairing position of this counter is defined as the position of piece synchronous head;
Wherein the length of piece is the L bit, N＞1.
Embodiments of the present invention also provide a kind of frame synchornization method, and each frame is made up of M piece, and M＞1 may further comprise the steps:
K bit group detected, each bit group comprises M piece, wherein, when each bit group is detected, reading the piece synchronous head composition receiving sequence of M piece in this bit group, is that unit carries out all possible cyclic shift to receiving sequence with the length of piece synchronous head, with this receiving sequence through cyclic shift the arrangement and the reference sequences that might obtain carry out related operation, write down the correlation of each related operation gained, K＞1;
With the correlation addition that corresponding same loop in K the bit group is moved number of times, obtain M relevant and;
If have only one relevant and greater than second thresholding, then according to should be relevant and pairing circulation move the position that number of times obtains frame head.
Embodiments of the present invention also provide a kind of frame-synchronizing device, comprising:
Detecting unit, be used for K bit group detected, each bit group comprises M piece, wherein, and when each bit group is detected, read the piece synchronous head of M piece in this bit group and form receiving sequence, length with the piece synchronous head is that unit carries out all possible cyclic shift to receiving sequence, with this receiving sequence through cyclic shift the arrangement and the reference sequences that might obtain carry out related operation, write down the correlation of each related operation gained, K＞1, M＞1;
Accumulator, K the correlation addition that the corresponding same loop of bit group is moved number of times that is used for detecting unit is obtained, obtain M relevant and;
M register, be respectively applied for that memory accumulator obtains M relevant and;
The frame synchronization determining device, be used for judging M register whether have only one relevant and greater than second thresholding, if, then according to should be relevant and pairing circulation move the position that number of times obtains frame head.
Embodiment of the present invention compared with prior art, the main distinction and effect thereof are:
Detect N bit group, the number of times that the bit fragment identical with the piece synchronous head each position in each bit group occurred is added up, if the statistical value that has only a position greater than first thresholding, then this position is the position of piece synchronous head.Just make the statistical value of each position comparatively approaching in the input error rate when higher, but the statistical value of piece synchronous head position obviously the probability greater than the statistical value of other position is still very big, therefore still can finish exactly synchronously.
Description of drawings
Fig. 1 is a FEC information frame structural representation in the prior art;
Fig. 2 is the block synchronization method flow chart according to first embodiment of the invention;
Fig. 3 is the piece synchronizer structural representation according to second embodiment of the invention;
Fig. 4 is the block synchronization method flow chart according to third embodiment of the invention;
Fig. 5 carries out the synchronous FEC information frame structural representation of piece according to third embodiment of the invention;
Fig. 6 is the block synchronization method flow chart according to third embodiment of the invention;
Fig. 7 is the piece synchronizer structural representation according to four embodiment of the invention;
Fig. 8 is the principle schematic according to the frame synchornization method of fifth embodiment of the invention;
Fig. 9 is the frame synchornization method flow chart according to fifth embodiment of the invention;
Figure 10 is the sync correlation principle of operation schematic diagram that carries out frame synchronization according to fifth embodiment of the invention;
Figure 11 is the frame-synchronizing device structural representation according to sixth embodiment of the invention.
Embodiment
For making the purpose, technical solutions and advantages of the present invention clearer, embodiments of the present invention are described in further detail below in conjunction with accompanying drawing.
First embodiment of the invention relates to a kind of block synchronization method, and the piece synchronous head of each piece is 2 bits in the data flow that is received, and default piece synchronous head is " 10 " or " 01 ".Wherein, the length of piece is the L bit, and for example, the length of piece is 66 bits (being L=66), and L counter correspondingly is set in system, and 66 counters also promptly are set.Carrying out piece when synchronous, be a bit group with the length L bit, the data flow of N bit group is detected, wherein, L counter corresponding respectively in a bit group a possible piece synchronous head position.The idiographic flow of this block synchronization method as shown in Figure 2.
In step 201, when beginning synchronously, the individual counter of initialization L (L=66), also be about to 66 counter Bff_cnt[a%L] all zero clearings, wherein, when making a=L, Bff_cnt[0] L counter of sensing, with block counter Block_cnt zero setting, the variable Block_lock value of representing synchronous regime being changed to " false " simultaneously, also is " Block_lock＜=false ".Wherein, a%L represents a to the L delivery, as a during smaller or equal to L, and a%L=a; As a during greater than L, then a%L equal L divided by a after the remainder of gained.
In step 202, each bit in N the bit group is scanned detection, in the present embodiment, default piece synchronous head is " 10 " or " 01 ", therefore only need to judge whether a bit different with the value of a+1 bit in the bit group that is scanned, promptly to each bit group execution if (input[a]!=input[a+1]) statement, wherein, function input[a] expression reads the data of a bit in the indicated bit group of Block_cnt in the data flow of input, therefore this statement data inequality whether of representing to judge the data of a bit in the bit group of current Block_cnt indication and a+1 bit, judge whether inequality of two Bit datas by simple, can judge apace whether two adjacent bit are one of piece synchronous head of presetting.If the value difference of two Bit datas being judged, then if (input[a]!=input[a+1]) value of statement is " true ", enters step 203, with the counter Bff_cnt[a%L of this bit fragment position correspondence] count value add 1, change step 204 then over to; Otherwise, if (input[a]!=input[a+1]) value of statement is " false ", counter Bff_cnt[a%L] do not do action, also be that count value is constant, directly change step 204 over to.
In step 204, judge whether a%L is 0, have only when a=L, the value of a%L is 0, if the value of a%L is 0, represents that then each bit in this bit group is respectively with comparing between its adjacent bit, enter step 205, block counter Block_cnt adds 1, makes can the data of next bit group be scanned, and enters step 206 then; If the value of a%L is not 0, represent that then each bit is adjacent more also not finishing between the bit in this bit group, block counter Block_cnt value is constant, will continue this bit group is scanned, and directly enter step 206.
In step 206, whether the Block_cnt value of decision block counter is more than or equal to N, if the Block_cnt value enters step 207 less than N, is " a+1 " with a value, changes step 202 then over to; If the Block_cnt value more than or equal to N, is then represented N bit group been scanned changed over to step 208.
In step 208, judge that the count value of whether having only a counter in L the counter is greater than piece threshold value (B_threshold), wherein, B_threshold=N-piece bias (B_offset), B_offset can determine according to the default error rate of piece, the default error rate is high more, and the B_offset value is big more.By being set flexibly, B_offset can adapt to the different input error rates.
If the count value of L counter all is less than or equal to B_threshold, perhaps the count value of at least two counters is arranged greater than B_threshold in L counter, be " false " according to the Block_lock value so, return step 201, carry out piece simultaneous operation again follow-up data stream is carried out synchronous detecting; If have only the count value of a counter greater than B_threshold in L the counter, then enter step 209, carry out " Block_lock＜=true " statement, variable Block_lock is changed to " true ", decision block is finished synchronously, and the pairing location determination of this counter is the position of piece synchronous head.Realize statistics owing in this process, utilize counter, just make the statistical value of each position comparatively approaching in the input error rate when higher, but the statistical value of the piece synchronous head position obviously probability greater than the statistical value of other position is still very big, therefore, still can finish exactly synchronously by present embodiment.
The detection of present embodiment and the detailed process of judgement are as follows:
The data of 66 bits of the 1st group to input are carried out check and analysis, concrete check and analysis process is: the numerical value of the 2nd bit will organizing compares with the numerical value of the 1st bit, if their value difference, be " 10 " or " 01 ", represent that then the bit fragment of being made up of the 1st group of the 1st bit and the 1st group of the 2nd bit is identical with default piece synchronous head, so, the 1st counter added 1; If their value is identical, be " 00 " or " 11 ", represent that then the bit fragment of being made up of the 1st group of the 1st bit and the 1st group of the 2nd bit is different with default piece synchronous head, so, keep the value of the 1st counter constant.Then, the numerical value of the 3rd bit will organizing successively compares with the numerical value of the 2nd bit, if their value difference, then the 2nd counter adds 1; If their value is identical, then the value of the 2nd counter is constant.And the like, the data of 66 bits in the 1st group are carried out check and analysis successively.
When a=66, a+1 then is 67, and the 66th bit and the 67th bit of receiving data compared, if their value difference, then the 66th counter adds 1 (during a=L, make Bff_cnt[a%L] be Bff_cnt[0] point to L counter); If their value is identical, then the value of the 66th counter is constant.Then, work as a=67, during a+1=68, the data of the 67th bit and the 68th bit compared, if their value difference, then Bff_cnt[a%L] value of the 1st counter pointed adds 1; If their value is identical, then the value of the 1st counter remains unchanged.Understand easily, as long as take above-mentioned method successively for the scanning analysis of 66 * N Bit data of N bit group.
Proof by experiment: when the value of N is 30, the value of B_offset is 4, is 10 in the bit error rate (Bit Error Rate is called for short " BER ") of chnnel coding
-3The time, adopting present embodiment can be 94.2% and adopt the probability of the accurate synchronization of prior art scheme so that the probability of accurate synchronization reaches 99.8%; When the value of N is 60, the value of B_offset is 5, and chnnel coding BER is 10
-3The time, the employing present embodiment can be so that the probability of accurate synchronization near 100%, be 88.7% and adopt the probability of the accurate synchronization of prior art scheme; When the value of N is 30, the value of B_offset is 4, and the BER of chnnel coding is 10
-2The time, adopting present embodiment can be 54.8% and adopt the probability of the accurate synchronization of prior art scheme so that the probability of accurate synchronization is 99.8%; When the value of N is 60, the value of B_offset is 5, and the BER of chnnel coding is 10
-2The time, adopting present embodiment can be 30.1% and adopt the probability of the accurate synchronization of prior art scheme so that the probability of accurate synchronization is 99.98%.Obviously, when interference ratio in the channel was big, the probability of prior art scheme accurate synchronization was very low, even can not be synchronous, and adopt embodiments of the present invention can keep higher accurate synchronization rate, can show the present invention program's superiority so that the performance of system improves widely.
Second embodiment of the invention relates to a kind of synchronizer, as shown in Figure 3, comprises L (for example, L=66) individual counter, detection module, initialization module and piece synchronization decisions device.Wherein, L is the length of piece, and unit is a bit.The piece synchronous head is 2 bits, and default piece synchronous head is " 10 " or " 01 ".
Specifically, 66 counters, each counter are corresponding respectively is possible piece synchronous head position in the bit group of 66 bits in length; Detection module is used for the individual bit group of N (N＞1) is detected, and each bit group length is 66, if detect and one of the piece synchronous head of presetting identical bit fragment, then indicates the counter of this bit fragment position correspondence to increase count value; Initialization module is used for before detection module detects 66 counters being carried out initialization; Piece synchronization decisions device, be used for detection module finish detect judge whether 66 counters have only a counter in the back count value greater than B_threshold, if then the pairing position of this counter is defined as the position of piece synchronous head.
The computational methods of synchronous head position are as follows: as and a counter x is only arranged (numerical value of x=1～N) is during greater than B_threshold, (n=0～N-1) individual bit is the beginning of the synchronous head of 64b/66b line coding piece in x+n * 66 of input data, this moment, piece synchronization decisions device declaration simultaneous operation was finished, piece synchronization decisions device starts zero-setting operation simultaneously, with 66 counter zero setting, be convenient to simultaneous operation next time.
If block synchronization decisions device judges that the count value of 66 counters all is less than or equal to B_threshold, perhaps the count value of at least two counters is arranged greater than B_threshold in 66 counters, then indicate initialization module that 66 counters are carried out initialization again, indicate detection module that new N bit group detected again.
In addition, detection module also comprises: shift register and comparator.
Wherein, shift register is used to preserve current two detected bits; Comparator is used for two bits of comparison shift register, if two bit differences, the pairing counter of the bit fragment of then indicating two bits to form increases count value.
Before this piece synchronizer carries out work, earlier 66 cycle counters all are changed to 0, then the 1st bit of the data that will receive and the 2nd bit are sent to the address 1 and the address 2 of the shift register of one 2 bit respectively, then register is sent to comparator with the data of being deposited, if the value difference of these 2 bits, then this comparator triggers the 1st counter and makes it to add 1, if these 2 bit value differences are not carried out trigger action.
Then, shift register is displaced to address 1 with the 2nd Bit data in the address 2, and the data of the 3rd bit that will receive again are sent to the address 2 of shift register.Same comparator compares the data of 2 bits in the shift register, makes it to add 1 if the value difference will trigger the 2nd counter, otherwise, do not carry out the flip-flop number operation.
And the like, deposit the 66th bit when shift register address 1 and receive data, when the 67th bit reception data were deposited in address 2, after comparator compared these two bits, whether decision carried out the flip-flop number operation to the 66th counter.Next, deposit the 67th bit when shift register address 1 and receive data, when the 68th bit reception data are deposited in address 2, after comparator compares these two bits, be recycled to the 1st counter, if the value difference of these two Bit datas, then comparator triggers the 1st counter and makes it to add 1, otherwise, do not carry out the flip-flop number operation.
Third embodiment of the invention relates to a kind of block synchronization method, similar with first embodiment of the invention, data to L bit in N the bit group detect successively and analyze, difference is, in the testing process of present embodiment, in the value that has compared a bit and a+1 bit and corresponding at every turn with counter Bff_cnt[a%L] (wherein, when making a=L, Bff_cnt[0] point to L counter) value add 1 or the operation of maintenance numerical value after, if judge and the count value of at least two counters arranged greater than B_threshold, then stop current detection immediately, again it is synchronous to carry out piece, can before having detected N bit group, finish impossible successful detection as early as possible like this, save detection time; In addition, the piece synchronous head of each piece is one of default piece synchronous head in the data flow that is received in first execution mode, and in the present embodiment, comprise piece synchronous head and the default different piece of piece synchronous head in the data flow that is received, thereby can make the present invention can be useful in the position of successfully finding the piece synchronous head in the frame of multiple coexistence.Correspondingly, the computational methods of B_threshold are also different.
Specifically, in the present embodiment, B_threshold=N-B_offset-P.Wherein, B_offset can determine that the default error rate is high more according to the default error rate of piece equally, and the B_offset value is big more, and the B_offset that can be provided with flexibly can adapt to the different input error rates; N is similarly the number of the bit group of being tested; And N-P is the number of piece synchronous head for the piece of default piece synchronous head; P does not then belong to the number of the piece of default piece synchronous head for the piece synchronous head.Judge the count value that in L the counter whether at least two counters is arranged greater than B_threshold according to B_threshold, if it is synchronous then to carry out piece again.
The FEC information frame as shown in Figure 5, each frame comprises 30 pieces, is respectively 27 line coding pieces and 3 check information pieces, per 27 continuous line coding piece back continued accesses 3 continuous check blocks, the mutual continued access of each frame.In addition, the length of the length of line coding piece and check information piece is the L=66 bit, wherein comprises the synchronous head of 2 bits, is specially: the synchronous head value of line coding piece is opposite, is " 01 " or " 10 "; And the synchronous head value of check block is identical, is " 00 " or " 11 ".
According to the B_threshold=N-B_offset-P computing formula, P is the number that the piece synchronous head does not belong to the piece of default piece synchronous head, and in the information frame as shown in Figure 5, the synchronous head of 3 check information pieces " 00 " and " 11 " do not belong to default piece synchronous head, that is to say P=3.Therefore, according to B_offset value that is provided with and known N=30, be easy to obtain the value of B_threshold.
The idiographic flow of present embodiment is as follows:
Step 401 is similar to step 203 with step 201 respectively to step 403, does not repeat them here.
In step 404, judge the count value that in L the counter whether at least 2 counters is arranged greater than B_threshold, if, then stop current detection immediately, and change over to and return step 401, again follow-up data is carried out the piece synchronous detecting; Otherwise the count value of representing in L the counter 1 or 0 counter to be arranged enters step 405 greater than B_threshold.
Step 405 is also similar to step 209 with step 204 respectively to step 410, does not give unnecessary details at this.
The flow chart of the block synchronization method of present embodiment can also adopt flow chart as shown in Figure 6 to represent, does not all depart from spirit of the present invention.Carry out piece synchronously before, the variable Block_lock of expression synchronous regime is changed to " false ", it is synchronous that expression begins to carry out piece.The while counter reset is with 66 counter Bff_cnt[66] all zero setting, simultaneously with block counter Block_cnt zero setting.Carry out the piece synchronism detection then, execution if (input[a]!=input[a+1]) statement, the last bit and the current bit that are about to import data compare.If this statement value is true, being legal conversion, counter Bff_cnt[a%66] value adds 1, and the value of a adds 1 (being a++), and whether adjudicate a%66 simultaneously is 0, and if be 0, block counter Block_cnt adds 1.If this statement is false, be illegal conversion, the value of a adds 1, counter Bff_cnt[66] and do not do action, have only block counter to count according to corresponding conditions.The piece number of supposing the block of information that test block is synchronously required is N, and reaching the synchronous required threshold value of piece is threshold.After testing the sequence of certain-length so, according to the situation of test, several different states can appear in piece synchronously:
(1) value of if block counter is less than N, and has only a counter greater than setting thresholding threshold in 66 counters, proceeds test so.
(2) value of if block counter is N, and all counters all are less than or equal to thresholding threshold in 66 counters, and perhaps a plurality of counters are announced piece simultaneous operation failure so greater than thresholding threshold, carry out again synchronously.
(3) value of if block counter is less than N, and all counters all are less than or equal to thresholding threshold in 66 counters, will proceed test so.
(4) value of if block counter is less than N, and a plurality of counters in 66 counters announce piece simultaneous operation failure greater than thresholding threshold, carries out the test of sliding.Be that this piece synchronism detection finishes immediately, begin to start piece synchronism detection next time from next test block.
(5) value of if block counter is N, and in 66 counters when and value that a counter is only arranged more than or equal to threshold value threshold, then announce the synchronism detection success, Block_lock is changed to " true " with the synchronous regime variable.
By the synchronous experiment test of piece, at the BER=10 of chnnel coding to the data flow that is similar to information frame as shown in Figure 5
-3, N=60, during B_offset=4, the employing present embodiment can be so that the probability of this information frame accurate synchronization near 100%, be 89.8% and adopt the probability of the accurate synchronization of prior art scheme; BER=10 in chnnel coding
-2, N is 60, during B_offset=4, adopting present embodiment can be 38.3% and adopt the probability of the accurate synchronization of prior art scheme so that the probability of this information frame accurate synchronization is 99.6%.Illustrated once more embodiments of the present invention at the BER of chnnel coding than under the condition with higher, still can keep the piece of high probability synchronous, thereby superiority of the present invention has been described.
Four embodiment of the invention relates to a kind of synchronizer, and this device is similar with the described device of second execution mode, comprises L counter, detection module, initialization module and piece synchronization decisions device equally.Wherein, detection module also comprises shift register and comparator.Difference is that in the present embodiment, this device also comprises to detect ends module, as shown in Figure 7.
This module is used in the testing process of detection module to N bit group, judge in L the counter and whether the count value of at least two counters is arranged greater than B_threshold, if, then indicate initialization module that L counter carried out initialization again, indicate detection module that new N bit group detected again.
Fifth embodiment of the invention relates to a kind of frame synchornization method, in that to finish piece synchronous, in the data flow of determining to receive behind the initial sum final position of circuit encoding block and check information piece, carry out information frame synchronously.For example, adopt the 3rd execution mode to carry out piece success synchronously to as shown in Figure 5 information frame after, the frame of this data flow is carried out frame synchronization as shown in Figure 8.
Each frame comprises the individual piece of M=30 (M＞1), is respectively 27 line coding pieces and 3 check information pieces, and per 27 continuous line coding piece back continued accesses 3 continuous check blocks, the mutual continued access of each frame.The length of the length of line coding piece and check information piece is the L=66 bit, wherein comprises the synchronous head of 2 bits, is specially: the synchronous head value of line coding piece is opposite, is " 01 " or " 10 "; And the synchronous head value of check block is identical, is " 00 " or " 11 ".Frame synchornization method as shown in Figure 9, its idiographic flow is as follows.
In step 901, K bit group detected, each bit group comprises M=30 piece, K＞1 wherein, when each bit group is detected, is read the piece synchronous head of M piece in this bit group and is formed receiving sequence.
For example as shown in figure 10, represent the 1st synchronous head of the 1st data block receiving with h11, h12 represents the 2nd synchronous head of the 1st data block receiving, and corresponding h301 and h302 represent the 1st and the 2nd synchronous head of the 30th data block receiving respectively.From some BOB(beginning of block)s, M=30 piece to the FEC information frame carries out synchronism detection continuously, comprises 27 line coding pieces and 3 check blocks in these 30 data blocks certainly.H11 and h12 are sent to preceding two positions of a circulating register, and then, 64 bits find h21 and h22 at interval, and h21 and h22 are sent into two positions subsequently of circulating register.And the like, up to h11 to h302 is deposited in the circulating register successively.
In step 902, sequence and the reference sequences that receives carried out related operation, obtain circulating and move the correlation of 0 bit, and write down this correlation.
Wherein, reference sequences is made up of line coding piece synchronous head and check information piece synchronous head two parts, the synchronous head of line coding piece can be set to any in " 01 " or " 10 ", and check information piece synchronous head then can be set to any in " 00 " or " 11 ".Therefore, the synchronous head part of the line coding piece of reference sequences all can be arranged to " 01 ", 3 check information piece synchronous heads are: 00,11,11.
The basic thought of sync correlation computing is to use a kind of operation method to come the degree of correlation of the synchronous head that receives synchronous head and reference sequences is weighed.Such as the reference synchronous head is " 00 ", if receiving synchronous head also is " 00 ", show that then both are relevant fully, if receiving synchronous head is " 11 ", it is uncorrelated to show both, or correlation is very poor, is " 01 " or " 10 " if receive synchronous head, shows that both have certain correlation.
A kind of sync correlation operation method is as shown in table 1, in this table, has enumerated the situation and the corresponding result thereof of 16 kinds of possible related operations, can obtain correlation by inquiring about this table.Specifically, the piece synchronous head of reception is " 00 ", with the reference sequences respective value be that the correlation of " 00 ", " 11 ", " 01 ", " 10 " is respectively 2,0,1,1; The piece synchronous head that receives is " 11 ", with the reference sequences respective value be that the correlation of " 00 ", " 11 ", " 01 ", " 10 " is respectively 0,2,1,1; The piece synchronous head that receives is " 01 ", with the reference sequences respective value be that the correlation of " 00 ", " 11 ", " 01 ", " 10 " is respectively 1,1,2,2; The piece synchronous head that receives is " 10 ", with the reference sequences respective value be that the correlation of " 00 ", " 11 ", " 01 ", " 10 " is respectively 1,1,2,2.
Table 1
| The piece synchronous head that receives | | Correlation | |
| 0?0 | 0?0 | 2 | |
| 0?0 | 1?1 | 0 | |
| 0?0 | 0?1/1?0 | 1 | |
| 1?1 | 0?0 | 0 | |
| 1?1 | 1?1 | 2 | |
| 1?1 | 0?1/1?0 | 1 | |
| 0?1/1?0 | 0?0 | 1 | |
| 0?1/1?0 | 1?1 | 1 | |
| 0?1/1?0 | 0?1/1?0 | 2 |
With the synchronous head sequence " 01 10 00 11 11 01 10 01 10 " in the circulating register, the synchronous head sequence " 01 01 01 01 01 01 00 11 11 " in the reference sequences is an example.
According to the sync correlation algorithm shown in the table 1, the correlation of the 1st pair of synchronous head " 01 " in the 1st pair of synchronous head " 01 " in the register and the reference sequences is 2, the correlation of the 1st pair of synchronous head " 01 " in the register in the 1st pair of synchronous head " 10 " and the reference sequences is 2, calculate successively, then each correlation addition being obtained the synchronizing sequence in the register and the correlation of reference sequences is 12.
Another kind of sync correlation operation method is calculated for adopting formula one:
Formula (1)
Wherein, γ is the correlation of receiving sequence and reference sequences, c
I1, c
I2Be respectively the 1st, 2 synchronous head of the data block of receiving sequence i, r
I1, r
I2Be respectively in the reference sequences data with the data block opposite position of receiving sequence i.Same with the synchronous head sequence " 01 10 00 11 11 01 1,001 10 " in the circulating register, synchronous head sequence " 01 01 01 01 01 01 00 11 11 " in the reference sequences is calculated for example, can find and coming to the same thing that employing table 1 operation method obtains.
In step 903, length 2 bits with the piece synchronous head are that unit carries out all possible cyclic shift to receiving sequence, this cyclic shift can be cyclic shift 2 bits to the left or to the right, after for example cyclic shift 2 was to the right as shown in figure 10, the synchronous head h301 of the 30th data block and h302 moved on to preceding 2 positions of register.
In step 904, judge whether cyclic shift finishes, if identical with the sequence of displacement 0 bit, also after i.e. the M time displacement, judge that then cyclic shift finishes, and enters step 905 through the sequence after step 903 displacement; If the cyclic shift number of times is less than M, cyclic shift does not finish, and then changes step 902 over to, and the sequence after the displacement is carried out related operation with reference sequences, obtains corresponding correlation and preserves this value.
Certainly, also can count, after the sequence after the M-1 time displacement is carried out related operation and preserved resulting correlation with reference sequences, just can finish shifting function, change step 905 equally over to this bit group to shift count.
In step 905, judge whether K bit group all to have been carried out reading the piece synchronous head respectively, to the displacement of sequence and the operation of related operation, obtained the correlation of corresponding each circulation position of sequence of K bit group, if then enter step 907; Otherwise, enter step 906, continue to read M synchronous head composition sequence of the next bit group in K the bit group, and enter step 902, this sequence is carried out related operation with reference sequences, so move in circles, up to K sequence, till all obtaining with M correlation of reference sequences on each circulation position K bit group correspondence.
In step 907, obtain K sequence of K bit group correspondence, on each circulation position with the correlation of reference sequences after, the K that circulation position is an identical correlation addition, obtain M relevant and.
For example, detect 3 bit groups (being K=3), the piece that comprises in each bit group is counted M=6, and cyclic shift 6 bits of the 1st, 2,3 frame correspondence and the correlation of reference sequences are respectively 54,48,32, then corresponding cyclic shift 6 bits of this information frame relevant and be 54+48+32=134.
In step 908, judge resulting M relevant and in, whether have only one relevant and greater than frame threshold value (F-threshold), F-threshold=2M * K-frame bias (F_offset).Wherein, the F_offset value determines that according to the error rate default in the frame the default error rate is high more, and this F_offset is big more, can adapt to the different input error rates by F_offset is set flexibly.
If have only one relevant and greater than F-threshold, then enter step 909, relevant and pairing circulation moves the position that number of times obtains this frame head according to this, finishes frame synchronization.For example, if having only the relevant of cyclic shift y bit correspondence to the right and, then can determine M-y/2 the original position that data block is an information frame in K the bit group greater than F-threshold; If have only the relevant of cyclic shift y bit correspondence left and, then can determine y/2 the original position that data block is an information frame in K the bit group greater than F-threshold.
If all relevant and all be less than or equal to F-threshold, perhaps have at least two relevant and greater than F-threshold, then return step 901, carry out frame synchronization again.
The receiving sequence of being made up of M piece synchronous head is carried out cyclic shift M-1 time, can obtain the various possible cyclic shift results of receiving sequence, these cyclic shifts result and reference sequences are carried out related operation, can indicate various cyclic shift results and the approaching degree of reference sequences quantitatively with correlation, by the correlation addition that corresponding same loop in K the bit group is moved number of times, in the input error rate when higher, still can know reliably that any cyclic shift result and reference sequences are the most approaching, thereby accurately know the position of frame head.
Sixth embodiment of the invention relates to a kind of frame-synchronizing device, as shown in figure 11, comprises detecting unit, accumulator, a M register and frame synchronization determining device.
Wherein, detecting unit is used for K bit group detected, and each bit group comprises M piece, wherein, when each bit group is detected, reading the piece synchronous head composition receiving sequence of M piece in this bit group, is that unit carries out all possible cyclic shift to receiving sequence with the length of piece synchronous head, with this receiving sequence through cyclic shift the arrangement and the reference sequences that might obtain carry out related operation, write down the correlation of each related operation gained, K＞1, M＞1;
Accumulator, K the correlation addition that the corresponding same loop of bit group is moved number of times that is used for detecting unit is obtained, obtain M relevant and;
M register, be respectively applied for that memory accumulator obtains M relevant and;
The frame synchronization determining device, be used for judging M register whether have only one relevant and greater than F-threshold, wherein, F-threshold=2M * K-F_offset, if, then according to should be relevant and pairing circulation move the position that number of times obtains frame head.
If it is all relevant and all be less than or equal to F-threshold that the frame synchronization determining device is judged in M the register, perhaps there are at least two to be correlated with and, then to indicate detecting unit that new K bit group detected greater than F-threshold.
In addition, detecting unit also comprises circulating register, reference sequences memory and related operation device.
Specifically, circulating register is made up of 2M bit, is used to preserve the receiving sequence that the piece synchronous head of M piece in the bit group is formed, two bits of the each cyclic shift of this circulating register; The reference sequences memory is used to preserve the reference sequences of being made up of 2M bit; The related operation device is used for circulating register and reference sequences memory are carried out the step-by-step related operation, obtains correlation.
Indicate various cyclic shift results and the approaching degree of reference sequences quantitatively with correlation, by the correlation addition that corresponding same loop in K the bit group is moved number of times, in the input error rate when higher, still can know reliably that any cyclic shift result and reference sequences are the most approaching, thereby accurately know the position of frame head.
Test for structure information frame as shown in Figure 5, is worked as K=3, F_offset=5, BER=10 by experiment
-3The time, adopt present embodiment carries out frame synchronization to the data of 3 information frames the probability of correct frame synchronization near 100%, be 78.7% and adopt the probability of the correct frame synchronization of prior art; Work as K=3, F_offset=5, BER=10
-2The time, adopting the probability of the correct frame synchronization of present embodiment is 96.7%, only is 9.1% and adopt the probability of the correct frame synchronization of prior art.From test result design of the present invention as can be seen compared with prior art, when higher, can keep higher accurate synchronization rate at BER.
In sum, in embodiments of the present invention, detect N bit group, the number of times that the bit fragment identical with the piece synchronous head each position in each bit group occurred is added up, if the statistical value that has only a position is greater than first thresholding, then this position is the position of piece synchronous head.Just make the statistical value of each position comparatively approaching in the input error rate when higher, but the statistical value of piece synchronous head position obviously the probability greater than the statistical value of other position is still very big, therefore still can finish exactly synchronously.
In testing process, synchronous if the count value that at least two counters are arranged, is then carried out piece again greater than first thresholding, can finish as early as possible before having detected N bit group like this can not successful detection, saving detection time.
First thresholding can be arranged to N-piece bias, can adapt to the different input error rates by the piece bias is set flexibly.
First thresholding also can be arranged to N-piece bias-P, has the piece synchronous head of P piece not belong to one of default piece synchronous head in N piece, thereby can successfully find the position of piece synchronous head in the frame that multiple coexistence arranged.
By the inequality whether of two adjacent bit relatively, can have only two bits at the piece synchronous head, and default piece synchronous head judges apace whether two adjacent bit are one of piece synchronous head of presetting when being " 10 " or " 01 ".
The receiving sequence of being made up of M piece synchronous head is carried out cyclic shift M-1 time, can obtain the various possible cyclic shift results of receiving sequence, these cyclic shifts result and reference sequences are carried out related operation, can indicate various cyclic shift results and the approaching degree of reference sequences quantitatively with correlation, by the correlation addition that corresponding same loop in K the bit group is moved number of times, in the input error rate when higher, still can know reliably that any cyclic shift result and reference sequences are the most approaching, thereby accurately know the position of frame head.
Though pass through with reference to some of the preferred embodiment of the invention, the present invention is illustrated and describes, but those of ordinary skill in the art should be understood that and can do various changes to it in the form and details, and without departing from the spirit and scope of the present invention.
Claims (12)
1. a block synchronization method is characterized in that, may further comprise the steps:
An initialization L counter, each counter are corresponding respectively to be a position in the bit group of L in length, and the piece synchronous head appears at one of the pairing L of described L counter position, L＞1;
N bit group detected, each bit group length is L, if detect and one of the piece synchronous head of presetting identical bit fragment, then in a described L counter, select the counter of this bit fragment position correspondence, increase the count value of selected counter; N＞1;
If the count value of having only a counter in the described L counter is greater than first thresholding, then the pairing location determination of this counter is the position of piece synchronous head; Wherein said length is the L bit.
2. block synchronization method according to claim 1 is characterized in that, described synchronous head is 2 bits, and described default piece synchronous head is " 10 " or " 01 ".
3. block synchronization method according to claim 2 is characterized in that, the described step that N bit group detected comprises following substep:
Each bit in each bit group is scanned, if X bit is different with the value of X+1 bit in the bit group that is scanned, then be judged to be and detect and the identical bit fragment of one of default piece synchronous head, detected bit fragment is made up of described X bit and X+1 bit;
The step that the counter of described bit fragment position correspondence increases count value comprises following substep:
The count value of X described counter is added 1.
4. block synchronization method according to claim 1 is characterized in that, and is after the described step that N bit group detected, further comprising the steps of:
If the count value of a described L counter all is less than or equal to described first thresholding, the count value that at least two counters are arranged in perhaps described L the counter is greater than described first thresholding, and it is synchronous then to carry out piece again.
5. block synchronization method according to claim 1 is characterized in that, in the described step that N bit group detected, also comprises following substep:
One by one described bit group is detected, before the detection of finishing described N bit group, if the count value that at least two counters are arranged in the described L counter then stops current detection immediately greater than described first thresholding, it is synchronous to carry out piece again.
6. according to each described block synchronization method in the claim 1 to 5, it is characterized in that described N is the number of piece in each frame;
The piece synchronous head of each piece is one of described default piece synchronous head in the described frame, described first thresholding=N-piece bias;
Perhaps,
The piece synchronous head of N-P piece is one of described default piece synchronous head in described frame, and the piece synchronous head of P piece does not belong to one of described default piece synchronous head, described first thresholding=N-piece bias-P.
7. block synchronization method according to claim 6 is characterized in that, described bias determined according to the default error rate in described.
8. a piece synchronizer is characterized in that, comprising:
L counter, each counter are corresponding respectively to be a position in the bit group of L in length, and the piece synchronous head appears at one of the pairing L of described L counter position, L＞1;
Detection module, be used for N bit group detected, each bit group length is L, if detect and one of the piece synchronous head of presetting identical bit fragment, then in a described L counter, select the counter of this bit fragment position correspondence, indicate selected counter to increase count value;
Initialization module is used for before described detection module detects a described L counter being carried out initialization;
Piece synchronization decisions device, be used for described detection module finish detect judge whether a described L counter have only a counter in the back count value greater than first thresholding, if then the pairing position of this counter is defined as the position of piece synchronous head;
Wherein said length is the L bit, N＞1.
9. a synchronizer according to claim 8 is characterized in that, described synchronous head is 2 bits, and described default piece synchronous head is " 10 " or " 01 ".
10. a synchronizer according to claim 9 is characterized in that, described detection module comprises:
Shift register is used to preserve current two detected bits;
Comparator is used for two bits of more described shift register, if described two bit differences, the pairing counter of the bit fragment of then indicating described two bits to form increases count value.
11. each described synchronizer in 10 according to Claim 8, it is characterized in that, described synchronization decisions device judges that the count value of a described L counter all is less than or equal to described first thresholding, the count value that at least two counters are arranged in perhaps described L the counter is greater than described first thresholding, then indicate described initialization module that a described L counter is carried out initialization again, indicate described detection module that new N bit group detected again.
12. each described synchronizer in 10 is characterized in that according to Claim 8, also comprises:
Detect and end module, be used in the testing process of described detection module N bit group, judge that the count value whether at least two counters are arranged in the described L counter is greater than described first thresholding, if, then indicate described initialization module that a described L counter is carried out initialization again, indicate described detection module that new N bit group detected again.
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| CN1210423A (en) * | 1997-04-04 | 1999-03-10 | 哈里公司 | Circuits and systems for generating and communicating advanced television signals |
| EP1515457A2 (en) * | 2003-09-10 | 2005-03-16 | Nec Corporation | Synchronization judging circuit capable of operating moderately |
| CN1859047A (en) * | 2006-01-24 | 2006-11-08 | 华为技术有限公司 | Frame synchronous processing device and method |
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| CN1210423A (en) * | 1997-04-04 | 1999-03-10 | 哈里公司 | Circuits and systems for generating and communicating advanced television signals |
| EP1515457A2 (en) * | 2003-09-10 | 2005-03-16 | Nec Corporation | Synchronization judging circuit capable of operating moderately |
| CN1859047A (en) * | 2006-01-24 | 2006-11-08 | 华为技术有限公司 | Frame synchronous processing device and method |
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