CN101350309A - Plane double diffusion metal oxide semiconductor device and preparation method - Google Patents
Plane double diffusion metal oxide semiconductor device and preparation method Download PDFInfo
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- CN101350309A CN101350309A CNA2008101194884A CN200810119488A CN101350309A CN 101350309 A CN101350309 A CN 101350309A CN A2008101194884 A CNA2008101194884 A CN A2008101194884A CN 200810119488 A CN200810119488 A CN 200810119488A CN 101350309 A CN101350309 A CN 101350309A
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- wafer
- foreign atom
- oxide semiconductor
- metal oxide
- semiconductor device
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 23
- 229910044991 metal oxide Inorganic materials 0.000 title claims abstract description 20
- 150000004706 metal oxides Chemical class 0.000 title claims description 17
- 238000009792 diffusion process Methods 0.000 title claims description 16
- 238000002360 preparation method Methods 0.000 title abstract description 6
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims abstract description 21
- 238000000034 method Methods 0.000 claims abstract description 21
- 229910052710 silicon Inorganic materials 0.000 claims abstract description 21
- 239000010703 silicon Substances 0.000 claims abstract description 21
- 239000002184 metal Substances 0.000 claims abstract description 13
- 229910052751 metal Inorganic materials 0.000 claims abstract description 13
- 125000004429 atom Chemical group 0.000 claims description 48
- 238000005260 corrosion Methods 0.000 claims description 19
- 230000007797 corrosion Effects 0.000 claims description 19
- 238000004519 manufacturing process Methods 0.000 claims description 11
- 125000004437 phosphorous atom Chemical group 0.000 claims description 6
- 230000004913 activation Effects 0.000 claims description 5
- 230000008569 process Effects 0.000 abstract description 5
- 238000004140 cleaning Methods 0.000 abstract description 4
- 230000003213 activating effect Effects 0.000 abstract 1
- 230000003628 erosive effect Effects 0.000 abstract 1
- 238000001704 evaporation Methods 0.000 abstract 1
- 150000002739 metals Chemical class 0.000 abstract 1
- 238000005516 engineering process Methods 0.000 description 6
- 238000010586 diagram Methods 0.000 description 3
- 230000004048 modification Effects 0.000 description 3
- 238000012986 modification Methods 0.000 description 3
- 230000005669 field effect Effects 0.000 description 2
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 2
- 239000010931 gold Substances 0.000 description 2
- 229910052737 gold Inorganic materials 0.000 description 2
- WATWJIUSRGPENY-UHFFFAOYSA-N antimony atom Chemical group [Sb] WATWJIUSRGPENY-UHFFFAOYSA-N 0.000 description 1
- 230000005684 electric field Effects 0.000 description 1
- 230000007115 recruitment Effects 0.000 description 1
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- Insulated Gate Type Field-Effect Transistor (AREA)
- Electrodes Of Semiconductors (AREA)
Abstract
The invention discloses a flat double-diffused metallic oxide semiconductor device and the process for preparation, which is used for reducing the contact resistance of an existing flat double-diffused metallic oxide semiconductor and improving the performances of the flat double-diffused metallic oxide semiconductor device. The method comprises: after carrying out the silicon erosion to the backside of a wafer, injecting a second doping atom which is different from a first doping atom existed in the wafer into the backside of the wafer, activating the doping atom which is injected into the backside of the wafer, and cleaning the wafer, and evaporating metals on the backside of the wafer.
Description
Technical field
The present invention relates to technology of semiconductor chips field, relate in particular to a kind of manufacturing technology of plane double diffusion metal oxide semiconductor device.
Background technology
Double-diffused transistor (Double diffused MOS, DMOS) be a kind of mos field effect transistor (Metal Oxide Semiconductor Field Effect Transistor, MOSFET), utilize diffusion to form its transistor area.Double-diffused transistor is used under the requirement of low forward pressure drop, provide higher per unit area electric current as the power transistor that is used for high-tension power integrated circuit usually.
One type of double-diffused transistor is Planar DMOS (Planar Double-diffused MetalOxide Semiconductor; plane double diffusion metal oxide semiconductor); the technology of traditional fabrication Planar DMOS device is after the front of the wafer that completes (wafer); carry out the pad pasting protection of wafer frontside; the attenuate of wafer rear; the silicon corrosion of wafer rear; remove the pad pasting and the cleaning wafer of wafer frontside; form the metal of wafer rear at wafer rear evaporated metal (Back metal); flow processs such as test finally obtain Planar DMOS.
Wherein, as shown in Figure 1, contact resistance (Rc, contact resistance) between back of the body gold and the wafer is an important electrical parameter, for Planar DMOS device, contact resistance is more little, source leakage diode forward conducting voltage (Vfsd, Drain-Source diode forward voltage) is just more little, and the performance of Planar DMOS device is just good more, therefore, little contact resistance is to make the target that the technology of Planar DMOS device is pursued.
Summary of the invention
The invention provides a kind of plane double diffusion metal oxide semiconductor device and preparation method thereof,, improve the performance of plane double diffusion metal oxide semiconductor in order to reduce the contact resistance of plane double diffusion metal oxide semiconductor.
The embodiment of the invention provides a kind of manufacture method of plane double diffusion metal oxide semiconductor device, comprising:
Wafer rear is carried out injecting and existing first foreign atom of described wafer second foreign atom inequality to described wafer rear after the silicon corrosion;
Activation is cleaned described wafer to the described foreign atom that wafer rear injects;
At the wafer rear evaporated metal.
The embodiment of the invention also proposes a kind of plane double diffusion metal oxide semiconductor device, comprise wafer through silicon corrosion and back side evaporated metal, comprise in the top layer through the face of silicon corrosion of described wafer with described wafer in inequality and second foreign atom that be activated of existing first foreign atom.
The embodiment of the invention also proposes a kind of wafer through silicon corrosion, comprise in the top layer through the face of silicon corrosion of described wafer with described wafer in inequality and second foreign atom that be activated of existing first foreign atom.
The embodiment of the invention provides a kind of plane double diffusion metal oxide semiconductor Planar DMOS and preparation method thereof.Planar DMOS manufacture method of the present invention, in existing P lanar DMOS manufacture method, two steps have been increased, promptly being increased in the wafer rear top layer after silicon corrosion wafer rear injects foreign atom and activates these two steps of foreign atom, make the wafer rear top layer form heavy doping, thereby the electronics or the hole on wafer rear top layer have been increased, form electrical active region, make the metal of wafer rear and the contact resistance between the wafer reduce, the source is leaked the diode forward conducting voltage and is reduced, and finally makes the performance of PlanarDMOS improve.
Description of drawings
Fig. 1 is the schematic diagram of plane double diffusion metal oxide semiconductor;
Fig. 2 is the flow chart of Planar DMOS device manufacture method in the embodiment of the invention;
Fig. 3 is the method schematic diagram that injects foreign atom in the embodiment of the invention to the wafer rear top layer;
Fig. 4 is the method schematic diagram that activates foreign atom in the embodiment of the invention.
Embodiment
The embodiment of the invention provides a kind of Planar DMOS device and preparation method thereof.Planar DMOS device manufacture method of the present invention, in existing P lanar DMOS device manufacture method, two steps have been increased, promptly being increased in the wafer rear top layer after silicon corrosion wafer rear injects foreign atom and activates these two steps of foreign atom, make the wafer rear top layer form heavy doping, thereby the electronics or the hole on wafer rear top layer have been increased, form electrical active region, make the metal of wafer rear and the contact resistance between the wafer reduce, the source is leaked the diode forward conducting voltage and is reduced, and finally makes the performance of Planar DMOS device improve.
Consult shown in Figure 2ly, the manufacture method of Planar DMOS device comprises following flow process:
The front of S201, making wafer, and carry out the pad pasting protection of wafer frontside, the attenuate of wafer rear, the silicon corrosion of wafer rear.
Wherein, wafer can be a Silicon Wafer, also can be the wafer made from other semi-conducting material.
Make the front of wafer among the step S201, and it is identical with corresponding prior art to carry out the silicon corrosion of attenuate, wafer rear of pad pasting protection, the wafer rear of wafer frontside, here detailed description no longer.
S202, inject foreign atom, existing foreign atom (as shown in Figure 3) inequality in this foreign atom and the wafer to the wafer rear top layer.
Usually be doped with antimony atoms in the wafer, should be inequality to the foreign atom that the wafer rear top layer is injected with the existing foreign atom of wafer, such as being phosphorus atoms.
Method from foreign atom to the wafer rear top layer that inject comprises: wafer is placed on an end of ion implantor, doped source is placed on the other end of ion implantor.At doped source one end, foreign atom is added to ultrahigh speed by ionization (having certain electric charge) by electric field, enters the wafer rear top layer.
Purpose from foreign atom to the wafer rear top layer that inject is to make the wafer rear top layer form heavy doping, increase the electronics or the hole on wafer rear top layer, form electrical active region, reduce to carry on the back the contact resistance between gold and the wafer, leak the diode forward conducting voltage thereby reduce the source, finally improve the performance of Planar DMOS device.
The energy that adopts when foreign atom is injected on the wafer rear top layer, the dosage that injects foreign atom can be adjusted (such as the energy that adopts can be 80KeV, and dosage can be 3E15) as required.Usually, the energy of employing is big more, and it is just dark more to inject the degree of depth, and the decrease of contact resistance is just big more, and the performance of Planar DMOS device is just good more; The dosage that injects foreign atom is big more, and the electronics on wafer rear top layer or the recruitment in hole are just big more, and the decrease of contact resistance is just big more, and the performance of Planar DMOS device is just good more.
S203, the pad pasting that removes wafer frontside and cleaning wafer.
The foreign atom (as shown in Figure 4) that S204, activation are injected to the wafer rear top layer.
The method that activates foreign atom is for taking off fire.
Since when foreign atom is injected on the wafer rear top layer, the doping un-activation, and the purpose that takes off fire makes exactly to mix and activates, and makes foreign atom and semiconductor atom form covalent bond.
The temperature that takes off fire can be adjusted as required, such as temperature being controlled at 450 degrees centigrade.
S205, cleaning wafer, and at the back side of wafer evaporated metal.
Each performance parameter of S206, test Planar DMOS device.
The Planar DMOS device manufacture method that the embodiment of the invention provides has reduced the metal of wafer rear and the contact resistance between the wafer, and then has reduced source leakage diode forward conducting voltage, has finally improved the performance of Planar DMOS device.
In addition, the embodiment of the invention also provides a kind of wafer through the silicon corrosion, comprises the foreign atom of activation in the top layer of the face of the process silicon corrosion of this wafer, and existing foreign atom is inequality in this foreign atom and the wafer.Wherein, foreign atom can be a phosphorus atoms.
The embodiment of the invention also provides a kind of plane double diffusion metal oxide semiconductor device, comprise wafer through silicon corrosion and back side evaporated metal, comprise the foreign atom of activation in the top layer of the face of the process silicon corrosion of this wafer, existing foreign atom is inequality in this foreign atom and the wafer.Foreign atom can be a phosphorus atoms.
Obviously, those skilled in the art can carry out various changes and modification to the present invention and not break away from the spirit and scope of the present invention.Like this, if of the present invention these are revised and modification belongs within the scope of claim of the present invention and equivalent technologies thereof, then the present invention also is intended to comprise these changes and modification interior.
Claims (7)
1, a kind of manufacture method of plane double diffusion metal oxide semiconductor device is characterized in that, comprising:
Wafer rear is carried out injecting and existing first foreign atom of described wafer second foreign atom inequality to described wafer rear after the silicon corrosion;
Activation is cleaned described wafer to the described foreign atom that wafer rear injects;
At the wafer rear evaporated metal.
2, the method for claim 1 is characterized in that, described second foreign atom comprises phosphorus atoms.
3, method as claimed in claim 1 or 2 is characterized in that, activates described foreign atom by taking off fire.
4, a kind of plane double diffusion metal oxide semiconductor device, comprise wafer through silicon corrosion and back side evaporated metal, it is characterized in that, comprise in the top layer through the face of silicon corrosion of described wafer with described wafer in inequality and second foreign atom that be activated of existing first foreign atom.
5, plane double diffusion metal oxide semiconductor device as claimed in claim 4 is characterized in that, described second foreign atom comprises phosphorus atoms.
6, a kind of wafer through silicon corrosion is characterized in that, comprise in the top layer through the face of silicon corrosion of described wafer with described wafer in inequality and second foreign atom that be activated of existing first foreign atom.
7, wafer as claimed in claim 6 is characterized in that, described second foreign atom comprises phosphorus atoms.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN2008101194884A CN101350309B (en) | 2008-09-01 | 2008-09-01 | Plane double diffusion metal oxide semiconductor device and preparation method |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN2008101194884A CN101350309B (en) | 2008-09-01 | 2008-09-01 | Plane double diffusion metal oxide semiconductor device and preparation method |
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| Publication Number | Publication Date |
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| CN101350309A true CN101350309A (en) | 2009-01-21 |
| CN101350309B CN101350309B (en) | 2011-04-20 |
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| CN2008101194884A Expired - Fee Related CN101350309B (en) | 2008-09-01 | 2008-09-01 | Plane double diffusion metal oxide semiconductor device and preparation method |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104766799A (en) * | 2014-01-07 | 2015-07-08 | 北大方正集团有限公司 | Field effect transistor manufacturing method and corresponding field effect transistor |
-
2008
- 2008-09-01 CN CN2008101194884A patent/CN101350309B/en not_active Expired - Fee Related
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104766799A (en) * | 2014-01-07 | 2015-07-08 | 北大方正集团有限公司 | Field effect transistor manufacturing method and corresponding field effect transistor |
| CN104766799B (en) * | 2014-01-07 | 2018-07-06 | 北大方正集团有限公司 | A kind of preparation method of field-effect transistor and corresponding field-effect transistor |
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| Publication number | Publication date |
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| CN101350309B (en) | 2011-04-20 |
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Effective date of registration: 20120725 Address after: 518116 Shenzhen city Longgang District Baolong Baolong Industrial City Seven Road No. five, founder Microelectronics Industrial Park Patentee after: SHENZHEN FOUNDER MICROELECTRONICS Co.,Ltd. Address before: 100871, Haidian District Fangzheng Road, Beijing, Zhongguancun Fangzheng building, 298, 513 Co-patentee before: SHENZHEN FOUNDER MICROELECTRONICS Co.,Ltd. Patentee before: PEKING UNIVERSITY FOUNDER GROUP Co.,Ltd. |
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