CN101335306A - Silicone oxide non-volatile memory unit ultra-high in silicone and manufacturing method therefor - Google Patents
Silicone oxide non-volatile memory unit ultra-high in silicone and manufacturing method therefor Download PDFInfo
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- CN101335306A CN101335306A CNA2007101126859A CN200710112685A CN101335306A CN 101335306 A CN101335306 A CN 101335306A CN A2007101126859 A CNA2007101126859 A CN A2007101126859A CN 200710112685 A CN200710112685 A CN 200710112685A CN 101335306 A CN101335306 A CN 101335306A
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Abstract
The invention relates to a nonvolatile memory cell of silicon oxide super-rich in silicon and a manufacturing method thereof. The nonvolatile memory cell comprises a grid conducting layer positioned on an underlay, source electrode/drain electrode areas positioned in the underlay on two sides of the grid conducting layer, a tunneling oxide layer between the grid conducting layer and the underlay, a silicon oxide layer super-rich in silicon positioned between the grid conducting layer and the tunneling oxide layer and served as a charge trapping layer and an upper dielectric layer positioned between the grid conducting layer and the silicon oxide layer super-rich in silicon.
Description
Technical field
The present invention is about a kind of memory cell and preparation method thereof, especially about a kind of non-volatile memory cells and preparation method thereof.
Background technology
Along with increase,, all need to use read-only memory (Read-Only Memory as digital camera, MP3 player, laptop computer and PDA(Personal Digital Assistant) etc. to the consumption electronic product demand; ROM) with the storage great mass of data.Because memory that read-only memory deposited in or data can not disappear because of the interruption of power supply supply, therefore be called nonvolatile memory (Non-Volatile Memory) again.In read-only memory, the most frequently used electricallyerasable ROM (EEROM) (the Electrically Erasable Programmable Read-Only Memory that surely belongs to; EEPROM), electricallyerasable ROM (EEROM) also has the function that can repeatedly deposit in, take out and remove except having the most basic function of reading and writing.
Typical electricallyerasable ROM (EEROM) is as control grid (Control Gate) and floating grid (Floating Gate) with the polysilicon that mixes, when it carried out sequencing (program), the polysilicon that the electronics that flows into floating grid can be uniformly distributed in whole doping was floated among the grid layer.The tunneling oxide layer defectiveness of grid layer below exists if the polysilicon that mixes is floated, and then causes the leakage current of element easily, and then influences the reliability of element.
A kind of element that can improve the electricallyerasable ROM (EEROM) leakage problem is arranged at present.This element is to adopt the polysilicon of the electric charge capture layer substitute doping grid layer of floating.Because the material of electric charge capture layer has the characteristic of catching electronics, therefore, the electronics that flows in the electric charge capture layer can't be uniformly distributed in the whole electric charge capture layer, but concentrates on the regional area of electric charge capture layer in the mode of Gaussian Profile.Only concentrate on local zone owing to flow into the electronics of electric charge capture layer, therefore less for the susceptibility of its defective of tunneling oxide layer, the phenomenon of element leakage current is difficult for taking place.The material of typical electric charge capture layer is a silicon nitride.Usually on aforementioned silicon nitride electric charge capture layer, one deck silica is respectively arranged down with it, and forming a kind of silicon oxide/silicon nitride/silicon oxide (ONO) composite dielectric layer that comprises at interior stacking-type (Stacked) grid structure, the EEPROM with this stacked gate structure is commonly referred to as silicon nitride ROM (NROM).But the silicon nitride electric charge capture layer is performed poor on charge-trapping amount and charge-trapping speed.
Summary of the invention
Embodiment of the invention purpose provides a kind of non-volatile memory cells and manufacture method thereof, passes through the embodiment of the invention:
1) can promote the seizure quantity of electric charge of electric charge capture layer;
2) can promote the seizure electric charge speed of electric charge capture layer;
3) the seizure quantity of electric charge that can overcome electric charge capture layer is crossed the low slow excessively problem of seizure electric charge speed that reaches electric charge capture layer.
The embodiment of the invention provides a kind of silicone oxide non-volatile memory unit ultra-high in silicone, comprising: substrate, grid conducting layer, source/drain regions, tunneling oxide layer, super silicon oxidation silicon layer and the upper dielectric layer of being rich in.Grid conducting layer is positioned on the substrate.Source/drain regions is arranged in the substrate of grid conducting layer both sides.Tunneling oxide layer is between grid conducting layer and substrate.Surpass and be rich in the silicon oxidation silicon layer, as electric charge capture layer, between grid conducting layer and tunneling oxide layer.
Described according to the embodiment of the invention, the super refractive index that is rich in silicon oxidation silicon is greater than 1.7 and less than 2.0 when 248 micron wave lengths.
Described according to the embodiment of the invention, the super refractive index that is rich in silicon oxidation silicon is 1.7.
Described according to the embodiment of the invention, super to be rich in the silicon oxidation silicon layer thickness be 80 dust to 120 dusts.Upper dielectric layer thickness is 70 dust to 110 dusts.Tunneling oxide layer thickness is 40 dust to 50 dusts.
The present invention also proposes a kind of aggregate non-volatile memory cells, comprising: substrate, grid conducting layer, source/drain regions, tunneling oxide layer, electric charge capture layer and upper dielectric layer.Grid conducting layer is positioned on the substrate.Source/drain regions is arranged in the substrate of grid conducting layer both sides.Tunneling oxide layer is between grid conducting layer and substrate.Electric charge capture layer is between grid conducting layer and tunneling oxide layer.Electric charge capture layer is that an insulating barrier and most aggregates are arranged in insulating barrier.Upper dielectric layer is between grid conducting layer and electric charge capture layer.
Described according to the embodiment of the invention, the material of insulating barrier is a silica, and aggregate is made of silicon atom.
Described according to the embodiment of the invention, the refractive index of electric charge capture layer is greater than 1.7 and less than 2.0 when 248 micron wave lengths.
Described according to the embodiment of the invention, the refractive index of electric charge capture layer is 1.7.
Described according to the embodiment of the invention, the material of upper dielectric layer is a silica.
Described according to the embodiment of the invention, the charge-trapping layer thickness is 80 dust to 120 dusts.Upper dielectric layer thickness is 70 dust to 110 dusts.Tunneling oxide layer thickness is 40 dust to 50 dusts.
The present invention also provides a kind of manufacture method of silicone oxide non-volatile memory unit ultra-high in silicone, at first in a substrate, form source, and on substrate, form tunneling oxide layer, on tunneling oxide layer, form to surpass afterwards and be rich in the silicon oxidation silicon layer as electric charge capture layer, form upper dielectric layer super being rich on the silicon oxidation silicon layer then, on upper dielectric layer, form grid conducting layer at last.
Described according to the embodiment of the invention, forming the super method that is rich in the silicon oxidation silicon layer is to form silicon oxide layer on tunneling oxide layer, and forms most silicon atom aggregates simultaneously in silicon oxide layer.
Described according to the embodiment of the invention, forming the super method that is rich in the silicon oxidation silicon layer is ion growth form chemical vapor deposition method.
Described according to the embodiment of the invention, ion growth form chemical vapor deposition method feeds a reacting gas, and it comprises that flow ratio is 0.5 to 1 N
2O and SiH
4
Described according to the embodiment of the invention, implement the N that ion growth form chemical vapor deposition method is fed
2The O flow is 80sccm to 100sccm or the SiH that fed
4Flow is 160sccm to 180sccm.
Described according to the embodiment of the invention, the operating condition of implementing ion growth form chemical vapor deposition method satisfies one of following condition at least: temperature is 350 ℃ to 450 ℃, and pressure is 2.5 Bristol to 8.5 Bristols, and high frequency power is 110 watts to 130 watts.
Described according to the embodiment of the invention, the super thickness that is rich in the silicon oxidation silicon layer is 80 dust to 120 dusts.
Described according to the embodiment of the invention, the super refractive index that is rich in the silicon oxidation silicon layer is between 1.7 to 2.0 when 248 micron wave lengths.
The beneficial effect of the embodiment of the invention is: the material of upper dielectric layer is a silica, the present invention adopts the oxide layer with aggregate as the super next electric charge capture layer as non-volatile memory cells of silicon oxidation silicon layer that is rich in, it can promote the seizure quantity of electric charge of the electric charge capture layer of non-volatile memory cells, and can promote the seizure electric charge speed of non-volatile memory cells moral electric charge capture layer.
Description of drawings
Fig. 1 is the generalized section of the silicone oxide non-volatile memory unit ultra-high in silicone of one embodiment of the invention;
Fig. 2 is the super local enlarged diagram that is rich in the silicon oxidation silicon layer of Fig. 1;
Fig. 3 A to Fig. 3 E is the manufacturing process generalized section of the silicone oxide non-volatile memory unit ultra-high in silicone of the embodiment of the invention;
Fig. 4 experiment gained super time (PGM Time) and corresponding start voltage variable quantity (Δ V that silicon oxidation silicon cell and known silicon nitride element carry out sequencing that be rich in of the present invention that serve as reasons
T) relation curve;
Fig. 5 serves as reasons, and the experiment gained is of the present invention super be rich in the silicon oxidation silicon cell and be rich in the silicon oxidation silicon cell and carry out the time of sequencing and the relation curve of corresponding start voltage variable quantity.
The primary clustering symbol description:
100: substrate
102: source/drain regions
104: tunneling oxide layer
106: the super silicon oxidation silicon layer that is rich in
108: upper dielectric layer
110: grid conducting layer
200: silicon oxide layer
202: the silicon atom aggregate
400,402,500,502: curve
Embodiment
Please refer to Fig. 1, Fig. 1 is the profile of the silicone oxide non-volatile memory unit ultra-high in silicone of the embodiment of the invention.
This non-volatile memory cells comprise substrate 100, doped region 102, tunneling oxide layer 104, super silicon rich silicon oxide layer 106, upper dielectric layer 108 with grid conducting layer 110.The material of substrate 100 for example is a silicon substrate.Have doping in the substrate 100, the kind of doping comprises N type or P type.Doped region 102 is as source, and its dopant species can be divided into N type or P type.In one embodiment, the P type that is doped to of substrate 100, the N type that is doped to of doped region 102.In another embodiment, the N type that is doped to of substrate 100, the P type that is doped to of doped region 102.
Upper dielectric layer 108 is arranged at super being rich on the silicon oxidation silicon layer 106.In one embodiment, the material of upper dielectric layer 108 is that silica and its thickness are 70 dust to 110 dusts.Grid conducting layer 110 is arranged on the upper dielectric layer 108.In one embodiment, the material of grid conducting layer 110 is a doped polysilicon layer.In another embodiment, grid conducting layer 110 is made of a doped polysilicon layer and metal silicide layer.
Fig. 3 A to Fig. 3 E is the manufacturing process generalized section of the silicone oxide non-volatile memory unit ultra-high in silicone of the embodiment of the invention.
At first, please refer to Fig. 3 A, a substrate 100 is provided, for example is silicon substrate.Have doping in the silicon substrate, the kind of doping comprises N type or P type.On substrate 100, form two doped regions 102, with as source/drain regions.The method that forms doped region 102 for example is thermal diffusion method (Diffusion) or ionic-implantation (IonImplantation).The dopant species of doped region 102 can be divided into N type or P type.In one embodiment, the P type that is doped to of substrate 100, the N type that is doped to of doped region 102.In another embodiment, the N type that is doped to of substrate 100, the P type that is doped to of doped region 102.
Then, on substrate 100, form a tunneling oxide layer 104.The material of tunneling oxide layer 104 for example is a silica, and the method for its formation for example is a thermal oxidation method.In one embodiment, the thickness of tunneling oxide layer 104 is 40 dust to 50 dusts.
Subsequently, please refer to Fig. 3 B, on above-mentioned tunneling oxide layer 104, form one to surpass and be rich in silicon oxidation silicon layer (Super-Silicon-Rich Oxide, SSRO) 106.The super local enlarged diagram that is rich in silicon oxidation silicon layer 106 as shown in Figure 2.Please refer to Fig. 2, super be rich in silicon oxidation silicon layer 106 and comprise oxide layer 200 and in oxide layer 200, have a plurality of silicon atom aggregates (cluster) 202.When memory cell was carried out programming operations, electric charge can be stored among the silicon atom aggregate 202.In one embodiment, the super refractive index that is rich in silicon oxidation silicon layer 106 is 1.7 to 2.0 when 248 micron wave lengths.In one embodiment, the super refractive index that is rich in silicon oxidation silicon layer 106 is 1.7.In one embodiment, the super thickness that is rich in silicon oxidation silicon layer 106 is 80 dust to 120 dusts.The super formation method that is rich in silicon oxidation silicon layer 106 for example is to adopt ion growth form chemical vapor deposition process to form silicon oxide layer 200 and while a plurality of silicon atom aggregates 202 of formation in silicon oxide layer 200.In one embodiment, the super silicon oxidation silicon layer 106 that is rich in adopts ion growth form chemical vapor deposition process to form, and be to be that 350 ℃ to 450 ℃, pressure are that 2.5 Bristol to 8.5 Bristols, high frequency power are to deposit ion growth form chemical vapor deposition method under 110 watts to 130 watts the condition in temperature, the gas that is fed comprises N
2O and SiH
4, N
2O flow and SiH
4Flow ratio is 0.5 to 1.For example, the N that is fed
2The O flow is 80sccm to 100sccm; The SiH that is fed
4Flow is 160sccm to 170sccm.In a concrete example, ion growth form chemical vapor deposition method is that 400 ℃, pressure are 5.5 Bristols, N in temperature
2O flow and SiH
4The N that flow ratio is 0.57, feeds
2O flow and SiH
4Flow is respectively 90sccm and 168sccm and high frequency power and deposits under 120 watts the condition.
Afterwards, please refer to Fig. 3 C, form a upper dielectric layer 108 on the silicon oxidation silicon layer 106 super being rich in.The material of upper dielectric layer 108 is silica for example.The method that forms upper dielectric layer 108 comprises Low Pressure Chemical Vapor Deposition.In one embodiment, the thickness of upper dielectric layer 108 is 70 dust to 110 dusts.
Then, please refer to Fig. 3 D, on upper dielectric layer 108, form a grid conducting layer 110.In one embodiment, grid conducting layer 110 is a doped polysilicon layer, and the method for formation is for example carried out chemical vapor deposition method in the mode of mix when participating in the cintest (In-Situ).In another embodiment, grid conducting layer 110 is constituted by a doped polysilicon layer and metal silicide layer, the method that forms is for example carried out chemical vapor deposition method to form doped polysilicon layer in the mode of mixing when participating in the cintest, forms metal silicide layer with chemical vapor deposition method again.
Afterwards; please refer to Fig. 3 E; carry out the technology of patterning; on grid conducting layer 110, form patterning photoresist layer (not marking among the figure); and serve as the cover curtain with the photoresist layer of patterning; remove grid conducting layer 110 partly, upper dielectric layer 108, surpass and be rich in silicon oxidation silicon layer 106 and tunneling oxide layer 104, the zone that photoresist layer is protected exposes the surface of substrate 100, photoresist layer is removed at last again.Removing grid conducting layer 110 partly, upper dielectric layer 108, surpassing the method that is rich in silicon oxidation silicon layer 106 and tunneling oxide layer 104 for example is the dry-etching method.The method that removes photoresist layer for example is as with H with damp process
2SO
4Solution divests photoresist layer.
In above embodiment, be to form grid structure again with the doped region that forms source/drain regions earlier it is described.Yet the present invention is not limited to this, and the doped region of source/drain regions also can form it again after grid structure forms.
Fig. 4 is rich in time (PGM Time) and corresponding start voltage variable quantity (the Δ V that silicon oxidation silicon cell and known silicon nitride element carry out sequencing for of the present invention to super
T) relation curve.
Shown by the result of Fig. 4: element 1 carries out with element 2-during the FN sequencing, greater than 10
-6Second and less than 10
-2During second, the measured start voltage changing value of element 1 is obviously greater than the start voltage changing value of element 2.In addition, as can be seen from Figure 4: when element 1 and element 2 carry out-during the FN sequencing, when reaching identical start voltage variable quantity (greater than 2 volts and less than 4 volts), the 1 required time of element is starkly lower than the required time of element 2.Therefore, adopt the super seizure electric charge speed that silicon oxidation silicon can promote the seizure quantity of electric charge of electric charge capture layer as the material of electric charge capture layer and can promote electric charge capture layer that is rich in of the present invention.
Fig. 5 super be rich in silicon oxidation silicon (SSRO) element and be rich in silicon oxidation silicon (SRO) element and carry out the time of sequencing and the relation curve of corresponding start voltage variable quantity for the experiment gained is of the present invention.
Shown by the result of Fig. 5: element 3 carries out with element 4-during the FN sequencing, and the measured start voltage changing value of element 3 is obviously greater than the start voltage changing value of element 4.In addition, as can be seen from Figure 5: when element 3 and element 4 carry out-during the FN sequencing, when reaching identical start voltage variable quantity, the 3 required times of element are starkly lower than the required time of element 4.
In sum, the present invention adopts to surpass is rich in the electric charge capture layer of silicon oxidation silicon as non-volatile memory cells, and it can promote the seizure quantity of electric charge of electric charge capture layer, and can promote the seizure electric charge speed of electric charge capture layer.
Institute is understood that; the above is preferred embodiment of the present invention, and is not intended to limit the scope of the invention, and is within the spirit and principles in the present invention all; any modification of being made, be equal to replacement, improvement etc., all should be included within the protection range of the present utility model.
Claims (17)
1. a silicone oxide non-volatile memory unit ultra-high in silicone is characterized in that, comprising:
One grid conducting layer, it is positioned at substrate top;
Source, it is arranged in the described substrate of described grid conducting layer both sides;
One tunneling oxide layer, it is between described grid conducting layer and described substrate;
One surpass and be rich in the silicon oxidation silicon layer, it is as an electric charge capture layer, between described grid conducting layer and described tunneling oxide layer; And
One upper dielectric layer, it is described grid conducting layer and described super being rich between the silicon oxidation silicon layer.
2. silicone oxide non-volatile memory unit ultra-high in silicone as claimed in claim 1 is characterized in that, the described super refractive index that is rich in silicon oxide layer is between 1.7 to 2.0 when 248 micron wave lengths.
3. silicone oxide non-volatile memory unit ultra-high in silicone as claimed in claim 2 is characterized in that, the wherein said super refractive index that is rich in the silicon oxidation silicon layer is 1.7.
4. silicone oxide non-volatile memory unit ultra-high in silicone as claimed in claim 1 is characterized in that, the wherein said super thickness that is rich in the silicon oxidation silicon layer is 80 dust to 120 dusts; The thickness of described upper dielectric layer is that the thickness of 70 dust to 110 dusts and described tunneling oxide layer is 40 dust to 50 dusts.
5. an aggregate non-volatile memory cells is characterized in that, comprising:
One grid conducting layer, it is positioned at substrate top;
Source, it is arranged in the described substrate of described grid conducting layer both sides;
One tunneling oxide layer, it is between described grid conducting layer and described substrate;
One electric charge capture layer, it is between described grid conducting layer and described tunneling oxide layer, and this electric charge capture layer comprises that an insulating barrier and most aggregates are arranged in described insulating barrier; And
One upper dielectric layer is between described grid conducting layer and described electric charge capture layer.
6. aggregate non-volatile memory cells as claimed in claim 5 is characterized in that described aggregate is to be made of silicon atom.
7. aggregate non-volatile memory cells as claimed in claim 5 is characterized in that, the refractive index of wherein said electric charge capture layer is between 1.7 to 2.0 when 248 micron wave lengths.
8. aggregate non-volatile memory cells as claimed in claim 7 is characterized in that, the refractive index of wherein said electric charge capture layer is 1.7.
9. aggregate non-volatile memory cells as claimed in claim 5 is characterized in that, the thickness of wherein said electric charge capture layer is 80 dust to 120 dusts; The thickness of described upper dielectric layer is that the thickness of 70 dust to 110 dusts and described tunneling oxide layer is 40 dust to 50 dusts.
10. the manufacture method of a silicone oxide non-volatile memory unit ultra-high in silicone is characterized in that, comprising:
In a substrate, form source;
On described substrate, form a tunneling oxide layer;
On described tunneling oxide layer, form one to surpass and be rich in the silicon oxidation silicon layer, as an electric charge capture layer;
Form a upper dielectric layer on the silicon oxide layer described super being rich in; And
On described upper dielectric layer, form a grid conducting layer.
11. the manufacture method of silicone oxide non-volatile memory unit ultra-high in silicone as claimed in claim 10 is characterized in that, wherein forms the described super method that is rich in the silicon oxidation silicon layer and comprises:
On described tunneling oxide layer, form one silica layer, and in described silicon oxide layer, form most silicon atom aggregates simultaneously.
12. the manufacture method of silicone oxide non-volatile memory unit ultra-high in silicone as claimed in claim 10 is characterized in that, wherein forms the described super method that is rich in silicon oxide layer and comprises ion growth form chemical vapor deposition process.
13. the manufacture method of silicone oxide non-volatile memory unit ultra-high in silicone as claimed in claim 12 is characterized in that, feeds a reacting gas in the wherein said ion growth form chemical vapour phase deposition process, it comprises that flow ratio is 0.5 to 1 N
2O and SiH
4
14. the super manufacture method that is rich in the silicon oxide layer non-volatile memory cells as claimed in claim 13 is characterized in that, wherein implements the N that described ion growth form chemical vapor deposition process is fed
2The O flow is 80sccm to 100sccm or the SiH that fed
4Flow is 160sccm to 180sccm.
15. the super manufacture method that is rich in the silicon oxide layer non-volatile memory cells as claimed in claim 12, it is characterized in that, the operating condition of wherein implementing described ion growth form chemical vapor deposition process satisfies one of following condition at least, temperature is 350 ℃ to 450 ℃, pressure is 2.5 Bristol to 8.5 Bristols, or high frequency power is 110 watts to 130 watts.
16. the super manufacture method that is rich in the silicon oxide layer non-volatile memory cells as claimed in claim 10 is characterized in that, the wherein said super thickness that is rich in silicon oxide layer is 80 dust to 120 dusts.
17. the super manufacture method that is rich in the silicon oxide layer non-volatile memory cells as claimed in claim 10 is characterized in that, the wherein said super refractive index that is rich in the silicon oxidation silicon layer is between 1.7 to 2.0 when 248 micron wave lengths.
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|---|---|---|---|
| CN2007101126859A CN101335306B (en) | 2007-06-27 | 2007-06-27 | Silicone oxide non-volatile memory unit ultra-high in silicone and manufacturing method therefor |
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|---|---|---|---|
| CN2007101126859A CN101335306B (en) | 2007-06-27 | 2007-06-27 | Silicone oxide non-volatile memory unit ultra-high in silicone and manufacturing method therefor |
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| CN101335306B CN101335306B (en) | 2011-04-13 |
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102468305A (en) * | 2010-11-19 | 2012-05-23 | 旺宏电子股份有限公司 | Non-volatile memory and method for manufacturing same |
| CN102709165A (en) * | 2012-01-12 | 2012-10-03 | 上海华力微电子有限公司 | Dibit silicon nitride read-only memory and manufacturing method thereof |
Family Cites Families (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6140676A (en) * | 1998-05-20 | 2000-10-31 | Cypress Semiconductor Corporation | Semiconductor non-volatile memory device having an improved write speed |
| US6395644B1 (en) * | 2000-01-18 | 2002-05-28 | Advanced Micro Devices, Inc. | Process for fabricating a semiconductor device using a silicon-rich silicon nitride ARC |
| US6812517B2 (en) * | 2002-08-29 | 2004-11-02 | Freescale Semiconductor, Inc. | Dielectric storage memory cell having high permittivity top dielectric and method therefor |
-
2007
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Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102468305A (en) * | 2010-11-19 | 2012-05-23 | 旺宏电子股份有限公司 | Non-volatile memory and method for manufacturing same |
| CN102468305B (en) * | 2010-11-19 | 2015-04-01 | 旺宏电子股份有限公司 | Non-volatile memory and method for manufacturing same |
| CN102709165A (en) * | 2012-01-12 | 2012-10-03 | 上海华力微电子有限公司 | Dibit silicon nitride read-only memory and manufacturing method thereof |
| CN102709165B (en) * | 2012-01-12 | 2015-05-20 | 上海华力微电子有限公司 | Dibit silicon nitride read-only memory and manufacturing method thereof |
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