CN101330061A - Method for preparing pixel structure - Google Patents
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- CN101330061A CN101330061A CNA2008101343060A CN200810134306A CN101330061A CN 101330061 A CN101330061 A CN 101330061A CN A2008101343060 A CNA2008101343060 A CN A2008101343060A CN 200810134306 A CN200810134306 A CN 200810134306A CN 101330061 A CN101330061 A CN 101330061A
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Abstract
The invention provides a method for manufacturing a pixel structure. The method comprises the following steps: firstly, a grid is formed on a base plate. Then a grid insulation layer is formed on a base plate so as to cover the grid; in addition, a channel layer, a source electrode and a drain electrode are formed on the grid insulation layer on the grid simultaneously, wherein, the grid, the channel layer, the source electrode and the drain electrode compose a thin film transistor. A protection layer is formed on the thin film transistor and the grid insulation layer; a black matrix is formed on the protection layer, wherein, the black matrix is provided with a contact opening above the drain electrode and a color filtering layer holding opening. Then a color filtering layer is formed in the color filtering layer holding opening by an ink-jet printing process; a dielectric layer is formed on the black matrix and the color filtering layer. Then the dielectric layer and the protection layer are patterned so as to expose the drain electrode. Then a pixel electrode electrically connected with the drain electrode is formed.
Description
Technical field
The invention relates to a kind of production method of pixel structure, and particularly (photolithography and etching process PEP) makes the production method of pixel structure with chromatic filter layer relevant for the less photoetching of a kind of use and etching process.
Background technology
Advantages such as LCD has that high image quality, volume are little, in light weight, low voltage drive, low consumpting power and applied range, (Cathode Ray Tube CRT) becomes the main flow of display of new generation therefore to have replaced cathode ray tube.Traditional display panels is made of colored optical filtering substrates, a thin-film transistor array base-plate (TFT Array Substrate) and the liquid crystal layer that is disposed between this two substrates with chromatic filter layer.For resolution and the aperture ratio of pixels that promotes panel, and the bit errors when avoiding colored optical filtering substrates to engage with thin-film transistor array base-plate, more proposed now chromatic filter layer directly is integrated in thin-film transistor array base-plate (Color Filter on Array, the COA) technology on.
Figure 1A～Fig. 1 G known a kind ofly is made in making schematic flow sheet on the thin film transistor (TFT) array with chromatic filter layer, and wherein Figure 1A～Fig. 1 H is to be the masterpiece explanation with three dot structures.At first, please refer to Figure 1A, substrate 10 is provided, and on substrate 10, form grid 20 by the first road photoetching and etching process (first PEP).Then, please refer to Figure 1B, on substrate 10, form gate insulation layer 30, and on gate insulation layer 30, form channel layer 40 and the ohmic contact layer 42 that is positioned at grid 20 tops by the second road photoetching and etching process (second PEP) with cover gate 20.Afterwards, please refer to Fig. 1 C, on the subregion of the subregion of channel layer 40 and gate insulation layer 30, form source electrode 50 and drain 60 by the 3rd road photoetching and etching process (third PEP).Generally speaking, the material of channel layer 40 is amorphous silicon (amorphoussilicon), and the material of ohmic contact layer 42 mostly is the heavily doped amorphous silicon of N type (N typeheavily-doped a-Si), in order to reduce between channel layer 40 and the source electrode 50 and channel layer 40 and the contact impedance that drains between 60, its formation method normally utilizes the mode of ion doping (ion doping) to carry out the doping of N type in the surface of amorphous silicon.
Please continue the C with reference to Fig. 1, source electrode 50 is extended on the gate insulation layer 30 by the both sides of channel layer 40 respectively with drain electrode 60, and the subregion of channel layer 40 is exposed, and wherein grid 20, channel layer 40, source electrode 50 constitute thin-film transistor T with drain electrode 60.Then, please refer to Fig. 1 D, go up covering dielectric layer 70 in thin-film transistor T, and form red filter pattern 82 in part thin-film transistor T top by the 4th road photoetching and etching process, wherein red filter pattern 82 has contact openings H1, and wherein contact openings H1 is positioned at the top of the drain electrode 60 of 82 corresponding thin-film transistor T of red filter pattern.
Afterwards, please refer to Fig. 1 E, form green filter pattern 84 by the 5th road photoetching and etching process in part thin-film transistor T top, and in green filter pattern 84, form contact openings H2, wherein contact openings H2 is positioned at the top of the drain electrode 60 of 84 corresponding thin-film transistor T of green filter pattern.Then, please refer to Fig. 1 F, form blue filter pattern 86 by the 6th road photoetching and etching process in remaining thin-film transistor T top, and in blue filter pattern 86, form contact openings H3, wherein contact openings H3 is positioned at the top of the drain electrode 60 of 86 corresponding thin-film transistor T of blue filter pattern.By Fig. 1 D～Fig. 1 F as can be known, the chromatic filter layer 80 that constituted of above-mentioned red filter pattern 82, green filter pattern 84 and blue filter pattern 86 is to make via three road photoetching and etching process.
Then, please refer to Fig. 1 G, remove the dielectric layer 70 that contact openings H1, H2, H3 are exposed via an etching technics, afterwards, on chromatic filter layer 80, form pixel electrode 90 by the 7th road photoetching and etching process again, by Fig. 1 G as can be known, the pixel electrode 90 of each dot structure can see through contact openings H1, H2, H3 and corresponding drain electrode 60 electrical connections respectively.So far, the technology that chromatic filter layer 80 directly is integrated in thin-film transistor array base-plate is roughly finished.
Hold above-mentionedly, the known manufacture method that chromatic filter layer is made on the thin film transistor (TFT) array needs to make by seven road photoetching and etching process at least, and step is complicated and need the higher production cost of cost.In addition, the dot structure that above-mentioned needs at least seven road photoetching and etching process are made need adopt a plurality of masks (mask) with different pattern, because the cost of mask is very expensive, so the manufacturing cost of dot structure can't reduce.
Summary of the invention
The invention provides a kind of production method of pixel structure, it is suitable for reducing cost of manufacture.
The present invention proposes a kind of production method of pixel structure, and it is prior to forming grid on the substrate.Then, on substrate, form gate insulation layer with cover gate, and on the gate insulation layer of grid top, form channel layer, source electrode and drain electrode simultaneously, wherein source electrode is positioned on the subregion of channel layer with drain electrode, and grid, channel layer, source electrode and drain electrode constitute thin-film transistor.Continue it; on thin-film transistor and gate insulation layer, form protective layer; and on protective layer, forming black matrix, wherein black matrix has the contact openings and the chromatic filter layer that are positioned at the drain electrode top and holds opening, and contact openings and chromatic filter layer hold the subregion that opening exposes protective layer.Afterwards, in chromatic filter layer holds opening, form chromatic filter layer, and on black matrix and chromatic filter layer, form dielectric layer by ink-jet printing process.Then, pattern dielectric layer and protective layer are so that drain electrode exposes.Then, form the pixel electrode that is electrically connected with drain electrode.
In pixel structure preparation method of the present invention, the method that forms channel layer, source electrode and drain electrode simultaneously for example comprises and then, to form conductive layer on semiconductor layer prior to forming semiconductor layer on the gate insulation layer.Afterwards, on the conductive layer of grid top, form photoresist layer, the photoresist layer second photoresist block that comprises the first photoresist block and be positioned at the first photoresist block both sides wherein, and the thickness of the first photoresist block is less than the thickness of the second photoresist block.Continuing it, is that photomask carries out first etching technics to conductive layer with the photoresist layer.Then, reduce the thickness of photoresist layer, removed fully up to the first photoresist block, the first photoresist block be removed during, the semiconductor layer that is covered by the second photoresist block can not be removed.Afterwards, be that photomask carries out second etching technics to conductive layer with the remaining second photoresist block, so that remaining conductive layer constitutes source electrode and drain electrode, and remaining semiconductor layer constitutes channel layer.Wherein, first etching technics and two etching technics for example are that wet method is paid etching technique.In addition, the method for above-mentioned minimizing photoresist layer thickness is for example carried out dry etch process, and dry etch process for example is a cineration technics.
In pixel structure preparation method of the present invention, the method that forms channel layer, source electrode and drain electrode comprises for example being prior to forming semiconductor layer on the gate insulation layer, then, forming ohmic contact layer on semiconductor layer.Afterwards, on ohmic contact layer, form conductive layer.Then, on the conductive layer of grid top, form photoresist layer, the photoresist layer second photoresist block that comprises the first photoresist block and be positioned at the first photoresist block both sides wherein, and the thickness of the first photoresist block is less than the thickness of the second photoresist block.Continue it, with the photoresist layer is that photomask carries out first etching technics to conductive layer, and reduce the thickness of photoresist layer, removed fully up to the first photoresist block, the first photoresist block be removed during, semiconductor layer and the ohmic contact layer that is covered by the second photoresist block can not be removed.Afterwards, with the remaining second photoresist block is that photomask carries out second etching technics to conductive layer, so that remaining conductive layer constitutes source electrode and drain electrode, and remaining semiconductor layer constitutes channel layer, and with the remaining second photoresist block is that photomask is to ohmic contact layer the 3rd etching technics, to remove the ohmic contact layer that is not covered by the second photoresist block.Wherein, first etching technics and two etching technics for example are that wet method is paid etching technique.In addition, the method for above-mentioned minimizing photoresist layer thickness is for example carried out dry etch process, and dry etch process for example is a cineration technics.
In pixel structure preparation method of the present invention, the method for pattern dielectric layer and protective layer for example is prior to forming photoresist layer on the dielectric layer.Afterwards, be photomask with the photoresist layer, remove the dielectric layer of part and the protective layer of part, with respectively at formation first opening and second opening in dielectric layer and the protective layer, wherein first opening and second opening are corresponding to contact openings.
In pixel structure preparation method of the present invention, the method that forms pixel electrode for example forms electrode material layer earlier in patterning protective layer, black matrix and on draining, again the patterned electrodes material layer.
In pixel structure preparation method of the present invention, when forming grid, also comprise forming first capacitance electrode, and when forming channel layer, source electrode and drain electrode, also comprise forming the semiconductor pattern and second capacitance electrode, first capacitance electrode and second capacitance electrode constitute holding capacitor.
In pixel structure preparation method of the present invention, when forming grid, comprise also forming first capacitance electrode that wherein first capacitance electrode and pixel electrode constitute holding capacitor.
In pixel structure preparation method of the present invention, when forming channel layer, source electrode and drain electrode, comprise also forming the semiconductor pattern and second capacitance electrode that wherein second capacitance electrode and pixel electrode constitute holding capacitor.
In pixel structure preparation method of the present invention, dielectric layer is the two side that covers the black matrix of corresponding contact openings.
In pixel structure preparation method of the present invention, dielectric layer is the two side that does not cover the black matrix of corresponding contact openings.
The present invention is integrated in channel layer, source electrode and the drain electrode of thin-film transistor with photoetching and etching process, and carry out the making of chromatic filter layer in the thin-film transistor top in conjunction with ink-jet printing technology, therefore compared to known pixel structure preparation method, can simplify processing step and reduce the cost of manufacture of mask.In addition, when utilizing ink-jet printing technology to make chromatic filter layer, the material use amount that can effectively save chromatic filter layer can further reduce manufacturing cost.
Description of drawings
Figure 1A～Fig. 1 G known a kind ofly is made in making schematic flow sheet on the thin film transistor (TFT) array with chromatic filter layer.
Fig. 2 A～Fig. 2 G is the making schematic flow sheet of a kind of dot structure of the present invention.
Fig. 2 H and Fig. 2 I enumerate two kinds of dot structures with storage capacitance of different kenels.
Fig. 3 A～Fig. 3 E is a kind of making schematic flow sheet that forms channel layer, source electrode and drain electrode simultaneously.
Fig. 4 A～Fig. 4 D is the another kind of making schematic flow sheet that forms channel layer, source electrode and drain electrode simultaneously.
Drawing reference numeral:
10,202: substrate
20,212: grid
30,220: gate insulation layer
40,232: channel layer
42,236: ohmic contact layer
50,242: source electrode
60,244: drain electrode
70: dielectric layer
82: red filter pattern
84: green filter pattern
80,270: chromatic filter layer
90,290: pixel electrode
200: dot structure
214: the first capacitance electrodes
234: semiconductor pattern
246: the second capacitance electrodes
250: protective layer
250H: second opening
260: black matrix
262: contact openings
264: chromatic filter layer holds opening
280: dielectric layer
280H: first opening
310: photoresist layer
310A: the first photoresist block
310B: the second photoresist block
C: holding capacitor
H, H1, H2, H3: contact openings
T, T ': thin-film transistor
Embodiment
For above-mentioned feature and advantage of the present invention can be become apparent, preferred embodiment cited below particularly, and cooperate appended graphicly, be described in detail below.
Fig. 2 A～Fig. 2 G is the schematic flow sheet of a kind of production method of pixel structure of the present invention.Please refer to Fig. 2 A, a substrate 202 at first is provided, the material of substrate 202 for example is hard or soft materials such as glass, plastic cement.Then, form grid 212 on substrate 202, the method that wherein forms grid 212 can be prior to forming conductive layer (not illustrating) comprehensively on the substrate 202, and the method that comprehensively forms conductive layer for example is by sputter (sputtering), evaporation (evaporation) or other film deposition techniques.Afterwards, this conductive layer of patterning (not illustrating) is to form grid 212.Above-mentioned patterned conductive layer for example is to be undertaken by chemical wet etching technology.In addition, present embodiment can optionally form first capacitance electrode 214 when forming grid 212.
Then, please refer to Fig. 2 B, on substrate 202, form the gate insulation layer 220 of the cover gate 212 and first capacitance electrode 214, wherein gate insulation layer 220 for example is by chemical vapour deposition technique (chemicalvapor deposition, CVD) or other suitable film deposition techniques form, and the material of gate insulation layer 220 for example is dielectric materials such as silica, silicon nitride or silicon oxynitride.Then, shown in Fig. 2 B, form channel layer 232 and source electrode 242 and drain electrode 244 simultaneously on the gate insulation layer 220 of grid 212 tops, wherein the material of channel layer 232 for example is amorphous silicon (amorphous silicon) or other semi-conducting materials.In addition, source electrode 242 and 244 the material of draining for example are copper (Cu), aluminium (Al), molybdenum (Mo), titanium (Ti), neodymium (Nd), above-mentioned nitride such as molybdenum nitride (MoN), titanium nitride (TiN), its lamination, above-mentioned alloy or other electric conducting materials.It should be noted that be different from known, channel layer 232 of the present invention, source electrode 242 and drain 244 for patterning simultaneously forms, it is conformal that its pattern is roughly, and can reduce one photoetching and etching process, and reduce the complexity of technology.
Please continue the B with reference to Fig. 2, source electrode 242 is positioned on the subregion of channel layer 232 with drain electrode 244, and grid 212, channel layer 232, source electrode 242 and the 244 formation thin-film transistor T that drain.In the present embodiment, when forming channel layer 232, source electrode 242 and drain electrode 244, optionally form the semiconductor pattern 234 and second capacitance electrode 246, wherein first capacitance electrode 214 and second capacitance electrode 246 constitute a holding capacitor C.What deserves to be mentioned is, in order to promote the element characteristic of thin-film transistor T, present embodiment can be in forming ohmic contact layer 236 between channel layer 232 and the source electrode 242 and between channel layer 232 and the drain electrode 244, reducing between channel layer 232 and the source electrode 242 and channel layer 232 and the contact impedance between 244 of draining, but the present invention is not as limit.The material of above-mentioned ohmic contact layer 236 for example is the heavily doped amorphous silicon of N type.In addition, above-mentionedly form channel layer 232, source electrode 242 simultaneously and 244 the method for draining will be in Fig. 3 A～Fig. 3 D illustrated.
Then; please refer to Fig. 2 C; in the protective layer 250 that forms on the substrate 202 on cover film transistor T and the gate insulation layer 220; wherein the material of protective layer 250 can be that organic dielectric materials such as acrylic resin, photoresist are formed, and protective layer 250 also can be that Inorganic Dielectric Materials such as silica, silicon nitride or silicon oxynitride are formed.In more detail; when protective layer 250 is selected organic dielectric materials for use; the method of its formation is normally made by method of spin coating; when protective layer 250 was selected Inorganic Dielectric Material for use, the method for its formation can utilize physical vaporous deposition or chemical vapour deposition technique to be deposited on the substrate 202 usually comprehensively.
Then, please refer to Fig. 2 D, and form black matrix 260 on protective layer 250, wherein the material of black matrix 260 for example is a black resin.Shown in Fig. 2 D, black matrix 260 has the contact openings H and the chromatic filter layer that are positioned at drain electrode 244 tops and holds opening 264, and contact openings H and chromatic filter layer hold the subregion that opening 264 exposes protective layer 250.More specifically; the formation method of black matrix 260 is for example prior to forming a material layer on the protective layer 250; this material layer of patterning again; wherein the formation method of this material layer for example is with method of spin coating, nozzle/method of spin coating (slit/spin coating) or non-rotating rubbing method (spin-less coating) material layer to be coated on the protective layer 250, and the step of this material layer of patterning comprises this material layer is carried out soft roasting, exposure, develops and hard roasting.In addition, in the present embodiment, black matrix 260 has an opening 266 that exposes second capacitance electrode 246.
Afterwards, please refer to Fig. 2 E, form chromatic filter layer 270 by ink-jet printing process in chromatic filter layer holds opening 264, wherein the material of chromatic filter layer 270 for example is acrylic resin (acrylicresin).On the practice, chromatic filter layer directly is being integrated in the technology of thin-film transistor array base-plate, each dot structure has the chromatic filter layer 270 that is positioned at thin-film transistor T top, and chromatic filter layer 270 can comprise red filter pattern, green filter pattern and blue filter pattern, so that display panels reaches the display effect of full-colorization.
In more detail, in the present embodiment, chromatic filter layer 270 can be red filter pattern, green filter pattern and blue filter pattern.In addition, above-mentioned ink-jetting process for example is earlier substrate 202 to be carried out process of surface treatment, afterwards, form red, green or blue chromatic filter layer holds in the opening 264 and sprays into color inks with nozzle that redness (R), green (G) or blue (B) ink are housed in predetermined again.Then toast again, so that color inks is solidified to form chromatic filter layer 270.It should be noted that, can in liquid crystal display panel pixel structure, form red filter pattern, green filter pattern and blue filter pattern simultaneously in the present embodiment, and do not need to use any photoetching and etching process (PEP), saving for manufacturing cost has significantly help, and allow the complexity of technology reduce, improve yield.Certainly, the present invention does not limit color, quantity and the configuration mode of filter pattern, and it can be different with the practical design demand.
Then, please refer to Fig. 2 F, form dielectric layer 280 on black matrix 260 and chromatic filter layer 270, wherein the material of dielectric layer 280 can be that organic dielectric materials such as acrylic resin, photoresist are formed, and the method for formation dielectric layer 280 can be utilized method of spin coating.Dielectric layer can also be formed by Inorganic Dielectric Material; for example be by chemical vapour deposition technique (chemical vapor deposition; CVD) or other suitable film deposition techniques form; material for example is dielectric materials such as silica, silicon nitride or silicon oxynitride; shown in Fig. 2 F; pattern dielectric layer 280 and protective layer 250, so that 244 exposures that drain, wherein pattern dielectric layer 280 for example is prior to forming photoresist layer (not illustrating) on the dielectric layer 280 with the method for protective layer 250.Afterwards; with photoresist layer (not illustrating) is photomask; remove the dielectric layer 280 of part and the protective layer 250 of part, to form the first opening 280H and the second opening 250H respectively in dielectric layer 280 and the protective layer 250, wherein the first opening 280H and the second opening 250H are corresponding to contact openings H.
Shown in Fig. 2 F, the second opening 250H of protective layer 250 is positioned at the covering scope of the first opening 280H of dielectric layer 280, and particularly, in the present embodiment, dielectric layer 280 does not cover the two side of contact openings H.In another embodiment; the layout of dielectric layer 280 and protective layer 250 also can be shown in Fig. 2 F '; dielectric layer 280 can extend in the part scope of contact openings H; shown in the oblique line part A among the figure; in other words; dielectric layer 280 can cover the two side of contact openings H, and the present invention does not limit the dielectric layer 280 of contact openings H place correspondence and the opening kenel of protective layer 250.
Afterwards, please refer to Fig. 2 G, in forming and drain electrode 244 pixel electrodes that are electrically connected 290, in the present embodiment, the opening 266 that pixel electrode 290 can see through black matrix 260 is electrically connected with second capacitance electrode 246, makes the capacitance electrode 214 of winning, gate insulation layer 220, second capacitance electrode 246 and pixel electrode 290 constitute a kind of holding capacitor.
In addition; the method of above-mentioned formation pixel electrode 290 for example forms electrode material layer (not illustrating) earlier in patterning protective layer 250, black matrix 260 and drain electrode 244; patterned electrodes material layer (not illustrating) again, the method that wherein forms electrode material layer for example is to form an indium tin oxide layer or an indium-zinc oxide layer by sputter.Step via above-mentioned Fig. 2 A～Fig. 2 G, can make dot structure 200, it should be noted that, be different from known seven road photoetching and the etching process of needing at least and carry out the making of pixel electrode 290, the present invention only needs to use four road photoetching and etching process and ink-jet printing process, chromatic filter layer 270 directly can be integrated on the thin-film transistor T array base palte 202, compared to known, the present invention not only can reduce multiple tracks photoetching and etching process, reduce the complexity of technology, and can effectively save the material use amount of chromatic filter layer 270, reduce the consumptive material expense.
What deserves to be mentioned is that the holding capacitor C of the foregoing description is a kind of metal layer/insulator layer/metal layer (Metal/Insulator/Metal, MIM) storage capacitance of kenel.Certainly, the storage capacitance in the dot structure can also be other kinds kenel, and for example (the present invention is not as limit for Metal/Insulator/ITO, MII) kenel for metal layer/insulator layer/indium tin oxide.For example, Fig. 2 H and Fig. 2 I enumerate two kinds of dot structures with storage capacitance of different kenels, and are simplified illustration, no longer those members identical with Fig. 2 G are explained.Shown in Fig. 2 H; holding capacitor C is made of first capacitance electrode 214, gate insulation layer 220, protective layer 250 and pixel electrode 290, or is made of first capacitance electrode 214, gate insulation layer 220, protective layer 250, dielectric layer 280 and pixel electrode 290.Shown in Fig. 2 I, storage capacitance C mainly is that second capacitance electrode 246, protective layer 250 and pixel electrode 290 constitute, and certainly, the dielectric layer between second capacitance electrode 246 and the pixel electrode 290 also can be made up of protective layer 250 and dielectric layer 280.On the practice, second capacitance electrode 246 can provide a current potential by an external power supply device, makes to form a holding capacitor C between second capacitance electrode 246 and the pixel electrode 290.
Fig. 3 A～Fig. 3 D is a kind of making schematic flow sheet that forms channel layer, source electrode and drain electrode simultaneously.As shown in Figure 3A, after forming gate insulation layer 220, on gate insulation layer 220, form semiconductor layer 230 in regular turn, ohmic contact layer 236 and conductive layer 240, and on the conductive layer 240 of grid 212 tops, form photoresist layer 310, the photoresist layer 310 second photoresist block 310B that comprises the first photoresist block 310A and be positioned at the first photoresist block 310A both sides wherein, and the thickness of the first photoresist block 310A is less than the thickness of the second photoresist block 310B, in the present embodiment, the method that forms the first photoresist block 310A and the second photoresist block 310B for example is via half mode photoetching and etching process or a grey mode photoetching and an etching process.Continuing it, please refer to Fig. 3 B, is that photomask carries out first etching technics to conductive layer 240 with photoresist layer 310, makes the conductive layer 240 that is not covered by photoresist layer 310 be removed, and wherein first etching technics for example is that wet method is paid etching technique.
Then, please refer to Fig. 3 C, reduce the thickness of photoresist layer 310, removed fully up to the first photoresist block 310A, the method that wherein reduces photoresist layer 310 thickness can be to carry out as dry etch process such as cineration technicss.What deserves to be mentioned is, the first photoresist block 310A be removed during, the semiconductor layer 230 that is covered by the second photoresist block 310B can not utilize dry etch process to be removed in the lump with ohmic contact layer 236 yet.
Afterwards, please refer to Fig. 3 D, with the remaining second photoresist block 310B is that photomask carries out second etching technics to conductive layer 240, so that remaining conductive layer 240 (being illustrated in Fig. 3 C) constitutes source electrode 242 and drains 244, and remaining semiconductor layer 230 constitutes channel layer 232, and wherein second etching technics is for example paid etching technique for wet method.Then, please refer to Fig. 3 E, with the remaining second photoresist block 310B be photomask to ohmic contact layer 236 the 3rd etching technics, to remove not the ohmic contact layer 236 that is covered by the second photoresist block 310B, wherein the 3rd etching technics is for example paid etching technique for wet method.
Fig. 4 A～Fig. 4 D illustrates and another kind of forms channel layer 232, source electrode 242 simultaneously and 244 the making schematic flow sheet of draining, the production method of Fig. 4 A～Fig. 4 D and Fig. 3 A～Fig. 3 E are similar, and the two main difference part is: present embodiment has omitted the making of ohmic contact layer 236; In other words, thin-film transistor T ' does not have ohmic contact layer 236.
Based on above-mentioned, the present invention not only makes channel layer, source electrode and drain electrode simultaneously, and utilizes ink-jet printing process chromatic filter layer to be integrated on the substrate of thin film transistor (TFT) array, therefore compared to known advantage with minimizing processing step.In addition, production method of pixel structure proposed by the invention has following advantage at least:
1. the production method of pixel structure that proposes of the present invention, its chromatic filter layer need not use photoetching process, thus compared to employed high accuracy photoetching of photoetching process and etching process, can reduce the cost of manufacture of mask, and the reduction process complexity.
2. because to make the step of dot structure less, can reduce tediously long photoetching and etching process (divest as photoresist coating, soft roasting, hard roasting, exposure, development, etching, the photoresist etc.) defective that produces when making dot structure.
3. chromatic filter layer of the present invention uses ink-jet printing process, so compared to photoetching process, can effectively reduce Master Cost, reduces cost.
Though the present invention discloses as above with preferred embodiment; right its is not in order to limit the present invention; any this area person skilled; without departing from the spirit and scope of the present invention; when can doing a little change and retouching, so protection scope of the present invention is as the criterion when the scope that look appending claims.
Claims (14)
1, a kind of production method of pixel structure is characterized in that, described method comprises:
On a substrate, form a grid;
On described substrate, form a gate insulation layer to cover described grid;
On the described gate insulation layer of described grid top, form a channel layer, one source pole and a drain electrode simultaneously, wherein said source electrode and described drain electrode are positioned on the subregion of described channel layer, and described grid, described channel layer, described source electrode and described drain electrode constitute a thin-film transistor;
On described thin-film transistor and described gate insulation layer, form a protective layer;
On described protective layer, form a black matrix, described black matrix has a contact openings and a chromatic filter layer that is positioned at described drain electrode top and holds opening, and described contact openings and described chromatic filter layer hold the subregion that opening exposes described protective layer;
Hold formation one chromatic filter layer in the opening by ink-jet printing process in described chromatic filter layer;
On described black matrix and described chromatic filter layer, form a dielectric layer;
Described dielectric layer of patterning and described protective layer are so that described drain electrode exposes; And
Form a pixel electrode that is electrically connected with described drain electrode.
2, production method of pixel structure as claimed in claim 1 is characterized in that, the method that forms described channel layer, described source electrode and described drain electrode simultaneously comprises:
On described gate insulation layer, form semi-conductor layer;
On described semiconductor layer, form a conductive layer;
On the described conductive layer of described grid top, form a photoresist layer, the one second photoresist block that wherein said photoresist layer comprises one first photoresist block and is positioned at the described first photoresist block both sides, and the thickness of the described first photoresist block is less than the thickness of the described second photoresist block;
With described photoresist layer is that photomask carries out one first etching technics to described conductive layer;
Reduce the thickness of described photoresist layer, removed fully up to the described first photoresist block, the first photoresist block be removed during, the described semiconductor layer that is covered by the described second photoresist block can not be removed; And
With the remaining described second photoresist block is that photomask carries out one second etching technics to described conductive layer, so that remaining described conductive layer constitutes described source electrode and described drain electrode, and described remaining described semiconductor layer constitutes described channel layer.
3, production method of pixel structure as claimed in claim 2 is characterized in that, described first etching technics and described second etching technics comprise that wet method pays etching technique.
4, production method of pixel structure as claimed in claim 2 is characterized in that, the method that reduces described photoresist layer thickness comprises carries out a dry etch process.
5, production method of pixel structure as claimed in claim 1 is characterized in that, the method that forms described channel layer, described source electrode and described drain electrode comprises:
On described gate insulation layer, form semi-conductor layer;
On described semiconductor layer, form an ohmic contact layer;
On described ohmic contact layer, form a conductive layer;
On the described conductive layer of described grid top, form a photoresist layer, the one second photoresist block that wherein said photoresist layer comprises one first photoresist block and is positioned at the described first photoresist block both sides, and the thickness of the described first photoresist block is less than the thickness of the described second photoresist block;
With described photoresist layer is that photomask carries out one first etching technics to described conductive layer;
Reduce the thickness of described photoresist layer, removed fully up to the described first photoresist block, the first photoresist block be removed during, described semiconductor layer and the described ohmic contact layer that is covered by the described second photoresist block can not be removed;
With the remaining described second photoresist block is that photomask carries out one second etching technics to described conductive layer, so that remaining described conductive layer constitutes described source electrode and described drain electrode, and described remaining described semiconductor layer constitutes described channel layer; And
With the remaining described second photoresist block is that photomask is to described ohmic contact layer 1 the 3rd etching technics, to remove the described ohmic contact layer that is not covered by the described second photoresist block.
6, production method of pixel structure as claimed in claim 5 is characterized in that, described first etching technics and described second etching technics comprise that wet method pays etching technique.
7, production method of pixel structure as claimed in claim 5 is characterized in that, the method that reduces described photoresist layer thickness comprises carries out a dry etch process.
8, production method of pixel structure as claimed in claim 1 is characterized in that, the method for described dielectric layer of patterning and described protective layer comprises:
On described dielectric layer, form a photoresist layer; And
With described photoresist layer is photomask; remove the described dielectric layer of part and the described protective layer of part; with respectively at forming one first opening and one second opening in described dielectric layer and the described protective layer, wherein said first opening and described second opening are corresponding to described contact openings.
9, production method of pixel structure as claimed in claim 1 is characterized in that, the method that forms described pixel electrode comprises:
Form an electrode material layer in described patterning protective layer, described black matrix and described drain electrode; And
The described electrode material layer of patterning.
10, production method of pixel structure as claimed in claim 1, it is characterized in that, when forming grid, also comprise and form one first capacitance electrode, and when forming described channel layer, described source electrode and described drain electrode, also comprise forming semiconductor pattern and one second capacitance electrode, described first capacitance electrode and described second capacitance electrode constitute a holding capacitor.
11, production method of pixel structure as claimed in claim 1 is characterized in that, described dielectric layer is the two side that covers the described black matrix of corresponding described contact openings.
12, production method of pixel structure as claimed in claim 1 is characterized in that, described dielectric layer is the two side that does not cover the described black matrix of corresponding described contact openings.
13, production method of pixel structure as claimed in claim 1 is characterized in that, when forming grid, comprises also forming one first capacitance electrode that wherein said first capacitance electrode and described pixel electrode constitute a holding capacitor.
14, production method of pixel structure as claimed in claim 1, it is characterized in that, when forming described channel layer, described source electrode and described drain electrode, also comprise forming semiconductor pattern and one second capacitance electrode, wherein said second capacitance electrode and described pixel electrode constitute a holding capacitor.
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Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104166261A (en) * | 2014-08-08 | 2014-11-26 | 深圳市华星光电技术有限公司 | Array substrate and manufacturing method thereof |
| CN102012592B (en) * | 2009-09-04 | 2016-04-20 | 上海天马微电子有限公司 | Liquid crystal display device and method for manufacturing the same |
| CN109343266A (en) * | 2018-11-16 | 2019-02-15 | 惠州市华星光电技术有限公司 | Display panel and display device |
Family Cites Families (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR101100674B1 (en) * | 2004-06-30 | 2012-01-03 | 엘지디스플레이 주식회사 | Method of fabricating of an array substrate for LCD with color-filter on TFT |
| CN101197332A (en) * | 2007-12-26 | 2008-06-11 | 友达光电股份有限公司 | Pixel structure manufacturing method |
-
2008
- 2008-07-22 CN CN2008101343060A patent/CN101330061B/en active Active
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102012592B (en) * | 2009-09-04 | 2016-04-20 | 上海天马微电子有限公司 | Liquid crystal display device and method for manufacturing the same |
| CN104166261A (en) * | 2014-08-08 | 2014-11-26 | 深圳市华星光电技术有限公司 | Array substrate and manufacturing method thereof |
| WO2016019606A1 (en) * | 2014-08-08 | 2016-02-11 | 深圳市华星光电技术有限公司 | Array substrate and manufacturing method therefor |
| CN104166261B (en) * | 2014-08-08 | 2017-05-17 | 深圳市华星光电技术有限公司 | Array substrate and manufacturing method thereof |
| CN109343266A (en) * | 2018-11-16 | 2019-02-15 | 惠州市华星光电技术有限公司 | Display panel and display device |
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| CN101330061B (en) | 2010-12-08 |
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