CN101330022A - Method and platform for making high-tension film - Google Patents
Method and platform for making high-tension film Download PDFInfo
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- CN101330022A CN101330022A CNA200710111873XA CN200710111873A CN101330022A CN 101330022 A CN101330022 A CN 101330022A CN A200710111873X A CNA200710111873X A CN A200710111873XA CN 200710111873 A CN200710111873 A CN 200710111873A CN 101330022 A CN101330022 A CN 101330022A
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Abstract
The invention discloses a method for producing a polysilicon stress layer, a method for producing an etch stop layer of a contact hole and a method for producing a high tension film. The invention also discloses ultra violate rapid thermal process equipment. The method for producing the high tension film comprises the steps as follows: a substrate provided with at least one transistor formed on the surface thereof is provided, the polysilicon stress layer is formed on the surface of the substrate and an ultra violate rapid thermal process (UVRTP) is carried out to harden the polysilicon stress layer and the stress of the polysilicon stress layer is adjusted as the high tension film. A film with high tensile stress can be formed within a relatively short technical time or at relatively low temperature as the tensile stress state of the high tension film is adjusted by combining the energy of photon and heat energy.
Description
Technical field
The present invention relates to a kind of manufacture method of high-tension film, relate in particular to a kind of method that forms high-tension film that goes up in a strain silicon metal oxide semiconductor transistor (strained-silicon metal-oxide-semiconductor transistor).
Background technology
Along with the semiconductor technology live width is contracted to below 65 nanometers (nm), and the development of element microminiaturization, how to improve element efficiency, promote the carrier mobility and the drive current of metal-oxide semiconductor (MOS) (MOS) transistor unit, become the big problem of one in the semiconductor industry.And for reaching the MOS transistor speed that promotes, industry is to have developed " strained silicon (strained-silicon) technology " at present, and it is considered as improving the main path of transistor speed.The cardinal principle of strained silicon technology is to make grid below, that is the silicon crystal lattice of channel region (channel region) produces strain, and suffered resistance when reducing electronics and moving increases electric charge locomotivity when the grid groove by this strain.
Strained silicon technology is roughly to be divided into two classes, first kind is to utilize one heavily stressed (high stress) film to be covered on the MOS transistor and to reach, for example polysilicon stressor layers (poly stressor) or contact hole etching stopping layer (contact etch stop layer is hereinafter to be referred as CESL) etc.; Another kind then is directly to utilize the strained silicon wafer as substrate or in conjunction with selective epitaxial growth (selective epitaxial growth, SEG) making of element that technology is carried out.Wherein, utilize stress film to promote the method for transistor drive current, can be divided into the different of PMOS transistor characteristic demand according to nmos pass transistor again: utilize a high tensile stress film (high tensile stress film) that a stretching stress is provided, and then widen the intrabasement lattice arrangement of semiconductor of nmos pass transistor below, method in the hope of the drive current (drive current) that improves the NMOS element, and utilize a high pressure stress film (high compressive stress film) that a compression stress is provided, and then the intrabasement lattice arrangement of semiconductor of extruding PMOS transistor below, in the hope of the method for the usefulness of improving the PMOS element.
See also Fig. 1, Fig. 1 is known in the schematic diagram that the nmos pass transistor surface makes a high tensile stress film.As shown in Figure 1, the semiconductor-based end 10, be provided with a nmos pass transistor 12, and it includes a grid structure, and grid structure includes a grid oxic horizon 14, with a grid 16 that is positioned on the grid oxic horizon 14.Grid 16 tops are to be formed with a cover layer (cap layer) 18; The sidewall of grid structure then includes monoxide-nitride-oxide off normal clearance wall (ONO offset spacer) 20.In addition, nmos pass transistor 12 includes source territory 22 in addition; Be provided with a shallow isolating trough 24 and be surrounded at the semiconductor-based end 10 of nmos pass transistor 12.Please continue to consult Fig. 1, the surface of nmos pass transistor 12 utilizes the plasma enhanced chemical vapor deposition method, and (plasma-enhancedchemical vapor deposition PECVD) forms a high tensile stress film 26 of being made up of silicon nitride or silica.
Generally speaking, present 65 nanometer technologies require 1.5GPa at least for the stretching stress state of high tensile stress film 26, and when entering into 45 nanometer technologies, and the requirement of its stretching stress state is then arrived more than the 1.8GPa.Yet only can obtain 1.5GPa with the resulting high tensile stress film 26 of present plasma enhanced chemical vapor deposition method.Therefore industry is to carry out a quick thermal treatment process (Rapid Thermal Processing is hereinafter to be referred as RTP) after forming high tensile stress film 26 at present, utilizes a high temperature that is higher than 1000 ℃ to adjust the stretching stress state of high tensile stress film 26.It should be noted that because CESL technology is to have finished in transistorized grid and source/drain surface to make at the semiconductor-based end that metal silicified layer makes, need the low heat budget demand of consideration metal silicified layer.For avoiding metal silicified layer to damage, need to reduce the temperature of quick thermal treatment process, make high tensile stress film 26 adjusted stretching stress states be lower than desired value.That is to say that though RTP is one easy and can effectively reach the method for target stretching stress state, and can obtain the higher stress value after putting on high tensile stress film 26, this method is to be subject to CESL technology.
In addition, known technology also provides another UV cured technology, in order to adjust high-tension film 26 stretching stress, this method is to utilize ultraviolet light source irradiation high-tension film 26, utilizes photon to interrupt (Si-H) key of silicon-hydrogen in the high-tension film 26 and silicon nitride-hydrogen (SiN-H) key.That is to say, against the hydrogen that removes in the high tensile stress film 26, UV cured technology is to make high tensile stress film 26 produce an irreversible stretching stress, widen the lattice arrangement at the semiconductor-based end 10 of nmos pass transistor 12 belows, and the hydrogen amount of removing is many more, and the stretching stress of high tensile stress film 26 is also high more.Yet UV cured technology required time is longer, and its efficient and effect are the thickness that is subject to high tensile stress film 26.
Summary of the invention
Therefore, the present invention provides a kind of method and board of making high-tension film in this, refers to a kind of method and board that forms high-tension film on a strain silicon metal oxide semiconductor transistor especially.
According to the present invention, the method of a kind of making polysilicon stressor layers (poly stressor) is provided, this method includes provides a surface to be formed with at least one transistorized substrate, to form a polysilicon stressor layers and carry out a ultraviolet ray and quick thermal treatment process (ultra violate rapid thermalprocess in this substrate surface, UVRTP), and adjust a stretching stress of this polysilicon stressor layers with this polysilicon stressor layers of hardening.
According to the present invention, other provides a kind of making contact hole etching stopping layer (contact etch stop layer, CESL) method, including provides a surface to include at least one grid, the substrate at least one clearance wall and source territory, in this substrate, form a metal level, carry out a rapid thermal anneal process, make those metal levels respectively at forming a transition metal silicide layer (intergraded salicide layer) on the drain/source zone and on this grid, form a contact hole etching stopping layer in this substrate surface, and carry out a ultraviolet ray and quick thermal treatment process, and adjust a stretching stress of this contact hole etching stopping layer with this contact hole etching stopping layer that hardens.
According to the present invention, a kind of method of making high-tension film more is provided, this method the substrate that provides a surface to include at least one grid structure, at least one clearance wall and source territory is provided, forms one first high-tension film, carries out one first ultraviolet ray and quick thermal treatment process (UVRTP) with this first high-tension film that hardens in this substrate surface, adjusts a stretching stress of this first high-tension film simultaneously.Wait to remove this first high-tension film, in this substrate, form a metal level, and carry out a rapid thermal anneal process, make on those metal levels difference drain/source zones and formation one transition metal silicide layer on this grid.Next form one second high-tension film in this substrate surface, carry out one second ultraviolet ray and quick thermal treatment process, and adjust a stretching stress of this second high-tension film with this second high-tension film that hardens.
In addition, according to the present invention, a kind of ultraviolet ray and fast bench heat treater more are provided, it includes a reaction chamber (chamber), be located in this reaction chamber in order to hold at least one semiconductor wafer,, include the ultraviolet light source and the heater of a ultraviolet light source and a thermal source in order to the load bearing seat (holder) and that carries this semiconductor wafer.
Because the method for making high-tension film provided by the present invention is to utilize a ultraviolet ray and quick thermal treatment process adjustment and this rete that hardens after forming high-tension film, polysilicon stressor layers or contact hole etching stopping layer, the stretching stress state that while is adjusted high-tension film in conjunction with the energy and the heat energy of photon, so can be in the relatively short process time or form the film of the high stretching stress of tool under the lower temperature, therefore more be applicable to processes with strained silicon with to the more sensitive hole etch stop layer process that contacts of temperature.In addition, when making contact hole etching stopping layer, ultraviolet ray and quick thermal treatment process more can directly replace the quick thermal treatment process second time in the known metal silicide process, so the present invention has more the effect of simplifying technology.
Description of drawings
Fig. 1 is known in the schematic diagram that the nmos pass transistor surface makes a high-tension film.
Fig. 2 to Fig. 4 is one first a preferred embodiment schematic diagram of the method for making high-tension film provided by the present invention.
Fig. 5 to Fig. 7 is the second preferred embodiment schematic diagram of the method for making high-tension film provided by the present invention.
Fig. 8 is the schematic diagram of the preferred embodiment of a kind of ultraviolet ray provided by the invention and fast bench heat treater.
Fig. 9 to Figure 10 is the schematic diagram of the preferred embodiment of a ultraviolet light source and heater.
The main element symbol description
10,30,50 substrates, 12,32,52 transistors
14,34,54 grid oxic horizons, 16,36,56 grids
18,38 cover layers, 20,40,60 clearance walls
22,42,62 source/drains, 24,44,64 shallow isolating trough
26 high-tension films, 46 polysilicon stressor layers
66 metal levels, 68 transition metal silicide layers
70 contact hole etching stopping layer 72 metal silicide layers
100 ultraviolet rays and fast bench heat treater
102 reaction chambers, 104 wafers
106 load bearing seats, 108 ultraviolet light sources and heater
110 shutter elements, 112 temperature detecting devices
114 gas inlets, 116 gas discharge outlets
120 thermals source, 122 ultraviolet light sources
Embodiment
See also Fig. 2 to Fig. 4, Fig. 2 to Fig. 4 is the method for making high-tension film provided by the present invention, for example makes one first preferred embodiment schematic diagram of a polysilicon membrane.As shown in Figure 2, at first provide a substrate 30, for example a silicon wafer or a silicon-coated insulated substrate comprise at least one transistor in the substrate 30, as the grid structure 32 of a nmos pass transistor.And grid structure 32 includes a gate dielectric 34, and a grid 36 that is positioned on the gate dielectric 34.Grid 36 tops are to be formed with a cover layer (cap layer) 38; The sidewall of grid structure 32 then is formed with monoxide-nitride-oxide off normal clearance wall (ONO offset spacer) 40.Gate dielectric 34 can be one and utilizes formed silica of technology such as thermal oxidation or deposition or nitrogen silicon compound to constitute; Cover layer 38 then can be made of a silicon nitride layer in order to protection grid 36.In addition, be surrounded at the semiconductor-based end 30 of grid structure 32 and be provided with a shallow isolating trough 44, in order to other elements of electrical isolation transistor AND gate.
See also Fig. 3.Carry out an ion subsequently and inject (ion implantation) technology, in the substrate 30 around the grid structure 32, to form source territory 42.Next carry out a rapid thermal annealing (rapid thermal annealing is designated hereinafter simply as RTA) technology, utilize the doping in 900 ℃ to 1050 ℃ the high-temperature activation regions and source 42; In RTA technology, repair simultaneously substrate lattice structure impaired in ion implantation technology.In addition, also visual product demand and functional considering, and between regions and source 42 and grid structure 32, form a lightly doped drain (lightly dopeddrain respectively, LDD) or source/drain extend (source/drain extension), more than know usually that with tool the knowledgeable is known, so do not add to give unnecessary details in this by known this skill person.
See also Fig. 4.Carry out a depositing operation, as a plasma enhanced chemical vapor deposition technology (PECVD), the high tensile stress film that formation one is made up of silicon nitride, silica or silicon oxynitride, as a polysilicon stressor layers 46, and the stretching stress state of the first plated film of polysilicon stressor layers 46 is about below the 1.5GPa.Next carry out a ultraviolet ray and quick thermal treatment process (Ultra Violet RapidThermal Process is designated hereinafter simply as UVRTP), when being used to harden polysilicon stressor layers 46, adjust the stress state of polysilicon stressor layers 46.In addition, because when carrying out UVRTP technology, polysilicon stressor layers 46 is to accept a large amount of heat energy in a short period, this thermal shock (thermal shock) makes polysilicon stressor layers 46 have more a cumulative stress (accumulated stress), and makes the stretching stress of polysilicon stressor layers 46 be worth to reach 0.5～3.0GPa.Polysilicon stressor layers 46 with this stretching stress can and then widen the substrate 30 of grid structure 32 belows, i.e. the lattice arrangement of channel region reaches the purpose of the drive current of the electron mobility that promotes channel region and nmos pass transistor.
According to a first advantageous embodiment of the invention, the temperature of this ultraviolet ray and quick thermal treatment process is between 150～800 ℃, its enforcement time then is within 60 minutes, and ultraviolet wavelength is between 100～400 nanometers (nm), and the pressure of technology is between 3～500 millitorrs (mTorr).In addition, also comprise the step that feeds nitrogen or inert gas in this ultraviolet ray and the quick thermal treatment process.
The manufacture method of high-tension film provided by the present invention is to utilize a ultraviolet ray and quick thermal treatment process to adjust its stress in the time of the high tensile stress film of sclerosis.In other words, method provided by the present invention is a stretching stress state of adjusting high-tension film in conjunction with the energy and the heat energy of photon simultaneously, so can form the film of the high stretching stress of tool in the relatively short process time.In addition, because the influence of thermal shock in ultraviolet ray and the quick thermal treatment process, high tensile stress film 46 resulting stress values can be promoted to 0.5～3.0GPa, and more satisfied technology now is to the requirement of tensile stress value.
See also Fig. 5 to Fig. 7, Fig. 5 to Fig. 7 is making high-tension film provided by the present invention, as makes one second preferred embodiment schematic diagram of the method for a contact hole etching stopping layer (contact etch stop layer is designated hereinafter simply as CESL).See also Fig. 5, a substrate 50 at first is provided, substrate 50 surfaces include at least one transistor, as the grid structure 52 of a nmos pass transistor.Grid structure 52 includes a gate dielectric 54, that utilizes formed silica of technology such as thermal oxidation or deposition or nitrogen silicon compound to be constituted and is positioned at grid 56 and monoxide-nitride-oxide off normal clearance wall (ONO offset spacer) 60 on the gate dielectric 54.In addition, be surrounded at the semiconductor-based end 50 of transistor 52 and be provided with a shallow isolating trough 64, in order to other elements of electrical isolation transistor AND gate.
Please continue to consult Fig. 5, carry out an ion implantation technology subsequently, in the substrate 50 around the grid structure 52, to form source territory 62.In addition, also visual product demand and functional considering, and between regions and source 62 and grid structure 52, form a lightly doped drain (LDD) or source/drain extension respectively, more than know usually that with tool the knowledgeable is known, so do not add to give unnecessary details in this by known this skill person.
See also Fig. 5 and Fig. 6.Form a metal level 66 subsequently in substrate 50, metal level 66 can include the alloy of cobalt (Co), titanium (Ti), nickel (Ni), tungsten (W), platinum (Pt), palladium (Pd), molybdenum (Mo) or above-mentioned metal.And carry out a RTA technology, under 400～600 ℃ temperature environment, make metal level 66 aim at reaction voluntarily with drain/source zone 62 and grid 56 contact portions respectively and form a transition metal silicide layer (intergraded salicide layer) 68.Utilize a selectivity Wet-type etching to remove the metal level 66 that unreacted becomes transition metal silicide afterwards again.
See also Fig. 7.Next pass through a depositing operation in substrate 50 surfaces, as plasma enhanced chemical vapor deposition (PECVD) technology, form a CESL 70, it can comprise materials such as silicon nitride, silica or silicon oxynitride, and the stretching stress state of its first plated film is below the 1.5GPa.Carry out a ultraviolet ray and quick thermal treatment process subsequently and to CESL 70, in the time of sclerosis CESL 70, adjust the stretching stress state of CESL 70, to widen the substrate 50 of grid structure 52 belows, be the lattice arrangement of channel region, reach the purpose of the drive current of the electron mobility that promotes channel region and nmos pass transistor.
Please continue to consult Fig. 7.Making that it should be noted that the common metal silicide layer is to need twice RTA technology, and RTA technology is the metal silicide that resistance value is higher in order to formation crystal grain is less for the first time, promptly aforesaid transition metal silicide layer; RTA technology is then utilized a higher temperature that transition metal silicide layer generation one changed mutually and is reduced its resistance value for the second time, and forms a metal silicide layer.According to method provided by the present invention, can utilize the ultraviolet ray implemented at CESL 70 and quick thermal treatment process in adjusting and sclerosis CESL 70, make transition metal disilicide layer 68 be transformed into a metal silicide layer 72 mutually simultaneously.Therefore the manufacture method of high-tension film provided by the present invention can be omitted aforesaid second time of RTA technology; Ultraviolet ray provided by the present invention in other words and quick thermal treatment process can directly replace the RTA technology second time in the known metal disilicide layer technology.In addition, the phase change that transition metal silicide layer 68 is produced in ultraviolet ray and quick thermal treatment process, transfer to form the metal silicide layer 72 except that making it, metal silicide layer 72 also make metal silicide layer 72 produce a tensile stress, so can reach 0.5～3.0GPa with the stretching stress value that CESL 70 integral body are produced because of phase change.
The temperature of this ultraviolet ray and quick thermal treatment process is between 150～800 ℃, and its enforcement time then is within 60 minutes, and ultraviolet wavelength is between 100～400 nanometers (nm), and the pressure of technology is between 3～500 millitorrs (mTorr).In addition, comprise also in ultraviolet ray and the quick thermal treatment process that one feeds the step of nitrogen or inert gas; And should in order to the quick thermal treatment process that forms metal silicide layer 68 and this ultraviolet ray and quick thermal treatment process be can original position (in-situ) mode or ex situ (non in-situ) mode carry out.
Because the manufacture method of CESL 70 provided by the present invention is to utilize a ultraviolet ray and quick thermal treatment process to adjust its stress in the time of sclerosis CESL 70.That is to say that method provided by the present invention is a stretching stress state of simultaneously adjusting CESL 70 in conjunction with energy and the heat energy of photon, thus can be in relatively short process time and lower heat budget the film of the high stretching stress of formation tool.In addition, because ultraviolet ray in CESL 70 technologies and quick thermal treatment process more can be in order to replace the RTA technology second time in the known metal silicide layer technology, therefore method provided by the present invention can be when simplifying CESL and metal silicide technology, promote whole tensile stress state to 0.5～3.0GPa, more satisfied technology now is to the requirement of tensile stress value.
In first preferred embodiment, the polysilicon stressor layers can be used as one first high-tension film, produces an irreversible stretching stress by ultraviolet ray and quick thermal treatment process, and stretching stress widens the substrate of transistor below, the i.e. lattice arrangement of channel region thus.Therefore removable this first high-tension film after carrying out ultraviolet ray and quick thermal treatment process, and carry out the described metal silicide technology of aforementioned second preferred embodiment.As previously mentioned, after forming this transition metal silicide layer, can in substrate, form one second high-tension film, utilize in addition once ultraviolet ray and quick thermal treatment process in sclerosis and when adjusting the stretching stress of this second high-tension film, the transition metal silicide layer is changed mutually and become metal silicide layer, changing mutually by this simultaneously provides a stretching stress; And this second high-tension film can be used as a CESL.In other words, implement the method that this first preferred embodiment and second preferred embodiment are instructed in succession, can make the lattice arrangement of substrate channel region obtain two to three times stress adjustment, thus more can satisfy now technology to the requirement of stretching stress value, and then more improve the drive current of NMOS element.
In addition, see also Fig. 8, Fig. 8 is the schematic diagram of the preferred embodiment of a kind of ultraviolet ray that provides in addition of the present invention and fast bench heat treater.As shown in Figure 8, ultraviolet ray that present embodiment provided and fast bench heat treater 100 include a reaction chamber (chamber) 102, in order to hold the load bearing seat (holder) 106 that at least one wafer 104, has heating function, be located in the reaction chamber 102, in order to bearing wafer 104 and a ultraviolet light source and heater 108.Ultraviolet ray provided by the present invention and fast bench heat treater 100 comprise a shutter elements 110 in addition, in order to control ultraviolet passing through; And a temperature detecting device 112, in order to the temperature of detecting wafer 104.In addition, as shown in Figure 8, ultraviolet ray and fast bench heat treater 100 more can comprise a gas inlet 114 and a gas discharge outlet 116, and it can feed and discharge nitrogen, inert gas or other reacting gass according to wafer 104 required process conditions.
See also Fig. 9 and Figure 10, Fig. 9 and Figure 10 are the schematic diagram of the preferred embodiment of ultraviolet light source and heater 108.The ultraviolet light source of ultraviolet ray provided by the present invention and fast bench heat treater and heater 108 include at least one thermal source 120 and at least one ultraviolet light source 122.Thermal source 120 can be halogen lamp tube or laser etc.; Ultraviolet light source 122 then can provide the ultraviolet ray of a wavelength between 100～400 nanometers (nm).In addition, the set-up mode of thermal source 120 and ultraviolet light source 122 can be staggered arrangement mode setting as shown in Figure 9; Or be provided with in the honeycomb arrangement mode as shown in figure 10.Certainly, thermal source 120 also can be modes such as a matrix is staggered with ultraviolet light source 122 and be provided with, and is not limited to Fig. 9 and shown in Figure 10.
According to ultraviolet ray provided by the present invention and fast bench heat treater, can carry out a UV treatment or rapid thermal treatment separately, also can when being provided, UV treatment utilize halogen lamp tube or laser to carry out a rapid thermal treatment.That is to say, according to ultraviolet ray provided by the present invention and fast bench heat treater, can be simultaneously in conjunction with the energy of photon and heat energy in a required technology.
Because the manufacture method of high-tension film provided by the present invention is to utilize a ultraviolet ray and quick thermal treatment process adjustment and this rete that hardens after forming high-tension film, polysilicon stressor layers or CESL, so the stretching stress state that can adjust high-tension film in conjunction with the energy and the heat energy of photon simultaneously, and provide than short processing time even lower heat budget.That is to say that the method for making high-tension film provided by the present invention can be in the relatively short time or formed the film of the high stretching stress of tool under the lower temperature, therefore more be applicable to processes with strained silicon with to the more sensitive CESL technology of temperature.In addition, the manufacture method of CESL provided by the present invention is the RTA technology second time in the substituted metal silicide process more directly, so more can simplify integrated artistic.And ultraviolet ray provided by the present invention and fast bench heat treater can satisfy the required of above-mentioned high-tension film manufacture method, what is more, because this ultraviolet ray and fast bench heat treater are that ultraviolet ray and heat energy are provided simultaneously, so the step that more can be used for needing UV treatment, rapid thermal treatment in the semiconductor technology or need two kinds of processing simultaneously.
The above only is the preferred embodiments of the present invention, and all equalizations of doing according to claim of the present invention change and modify, and all should belong to covering scope of the present invention.
Claims (51)
1. method of making the polysilicon stressor layers includes:
Provide substrate, and this substrate surface is formed with at least one transistor;
Form the polysilicon stressor layers in this substrate surface; And
Carry out ultraviolet ray and quick thermal treatment process with this polysilicon stressor layers of hardening, and adjust the stretching stress of this polysilicon stressor layers.
2. the method for claim 1, wherein this polysilicon stressor layers comprises silicon nitride, silica or silicon oxynitride.
3. the method for claim 1, wherein the stretching stress state of the first plated film of this polysilicon stressor layers is below the 1.5GPa.
4. the method for claim 1, wherein should ultraviolet ray and the temperature of quick thermal treatment process between 150～800 ℃.
5. the method for claim 1, wherein should ultraviolet ray and enforcement time of quick thermal treatment process be within 60 minutes.
6. the method for claim 1, wherein should ultraviolet ray and the pressure of quick thermal treatment process be between 3～500 millitorrs.
7. the method for claim 1, wherein should ultraviolet ray and the ultraviolet wavelength of quick thermal treatment process between 100～400 nanometers.
8. the method for claim 1, wherein should ultraviolet ray and quick thermal treatment process also comprise the step that feeds nitrogen.
9. the method for claim 1, wherein should ultraviolet ray and quick thermal treatment process also comprise the step that feeds inert gas.
10. the method for claim 1, wherein this polysilicon stressor layers of this sclerosis and the step of adjusting the stretching stress of this polysilicon stressor layers are to finish simultaneously in this ultraviolet ray and quick thermal treatment process.
11. the method for claim 1, wherein carry out this ultraviolet ray and quick thermal treatment process after, the adjusted stretching stress state of this polysilicon stressor layers is between 0.5～3.0GPa.
12. the method for claim 1, wherein this transistor comprises nmos pass transistor.
13. the method for claim 1, wherein this transistorized formation also includes following steps:
Form grid structure in this substrate surface;
Sidewall in this grid structure forms clearance wall; And
In this substrate around this clearance wall, form regions and source.
14. method as claimed in claim 13, the step that wherein forms this polysilicon stressor layers are to form after this regions and source.
15. the method for claim 1 also comprises the step that removes this polysilicon stressor layers, be carried out at this ultraviolet ray and quick thermal treatment process after.
16. a method of making contact hole etching stopping layer includes:
Provide substrate, and this substrate surface includes at least one grid structure, at least one clearance wall and regions and source;
In this substrate, form metal level;
Carry out rapid thermal anneal process, make those metal levels respectively at forming the transition metal silicide layer on the drain/source zone and on this grid;
Form contact hole etching stopping layer in this substrate surface; And
Carry out ultraviolet ray and quick thermal treatment process with this contact hole etching stopping layer that hardens, and adjust the stretching stress of this contact hole etching stopping layer.
17. method as claimed in claim 16, wherein this metal level includes the alloy of cobalt, titanium, nickel, tungsten, platinum, palladium, molybdenum or above-mentioned metal.
18. method as claimed in claim 16, wherein the temperature of this rapid thermal anneal process is between 400～600 ℃.
19. method as claimed in claim 16, wherein this contact hole etching stopping layer comprises silicon nitride, silica or silicon oxynitride.
20. method as claimed in claim 16, wherein the stretching stress state of the first plated film of this contact hole etching stopping layer is below the 1.5GPa.
21. method as claimed in claim 16, wherein should ultraviolet ray and the temperature of quick thermal treatment process between 150～800 ℃.
22. method as claimed in claim 16, wherein should ultraviolet ray and enforcement time of quick thermal treatment process be within 60 minutes.
23. method as claimed in claim 16, wherein should ultraviolet ray and the pressure of quick thermal treatment process between 3～500 millitorrs.
24. method as claimed in claim 16, wherein should ultraviolet ray and the ultraviolet wavelength of quick thermal treatment process between 100～400 nanometers.
25. method as claimed in claim 16, wherein should ultraviolet ray and quick thermal treatment process also comprise the step that feeds nitrogen.
26. method as claimed in claim 16, wherein should ultraviolet ray and quick thermal treatment process also comprise the step that feeds inert gas.
27. method as claimed in claim 16, wherein carry out this ultraviolet ray and quick thermal treatment process after, this contact hole etching stopping layer adjusted stretching stress state is between 0.5～3.0GPa.
28. method as claimed in claim 16, wherein this quick thermal treatment process and this ultraviolet ray and quick thermal treatment process are to carry out with original position mode or ex situ mode.
29. method as claimed in claim 16, wherein should ultraviolet ray and quick thermal treatment process be in order to this transition metal silicide layer is transformed into metal silicide layer.
30. a method of making high-tension film includes:
Provide substrate, and this substrate surface includes at least one grid structure, at least one clearance wall and regions and source;
Form first high-tension film in this substrate surface;
Carry out first ultraviolet ray and quick thermal treatment process with this first high-tension film that hardens, adjust the stretching stress of this first high-tension film simultaneously;
Remove this first high-tension film;
In this substrate, form metal level;
Carry out rapid thermal anneal process, make those metal levels respectively at forming the transition metal silicide layer on the drain/source zone and on this grid;
Form second high-tension film in this substrate surface; And
Carry out second ultraviolet ray and quick thermal treatment process with this second high-tension film that hardens, adjust the stretching stress of this second high-tension film simultaneously.
31. method as claimed in claim 30, wherein this first high-tension film and this second high-tension film comprise silicon nitride, silica or silicon oxynitride.
32. method as claimed in claim 30, wherein the stretching stress state of the first plated film of this first high-tension film and this second high-tension film is below the 1.5GPa.
33. method as claimed in claim 30, wherein the temperature of this first ultraviolet ray and quick thermal treatment process and this second ultraviolet ray and quick thermal treatment process is between 150～800 ℃.
34. method as claimed in claim 30, wherein the enforcement time of this first ultraviolet ray and quick thermal treatment process and this second ultraviolet ray and quick thermal treatment process is within 60 minutes.
35. method as claimed in claim 30, wherein the pressure of this first ultraviolet ray and quick thermal treatment process and this second ultraviolet ray and quick thermal treatment process is between 3～500 millitorrs.
36. method as claimed in claim 30, wherein the ultraviolet wavelength of this first ultraviolet ray and quick thermal treatment process and this second ultraviolet ray and quick thermal treatment process is between 100～400 nanometers.
37. method as claimed in claim 30, wherein this first ultraviolet ray and quick thermal treatment process also comprise the step that feeds nitrogen or inert gas with this second ultraviolet ray and quick thermal treatment process.
38. method as claimed in claim 30, wherein carry out this first ultraviolet ray and quick thermal treatment process after, the adjusted stretching stress state of this first high-tension film is between 0.5～3.0GPa.
39. method as claimed in claim 30, wherein this metal level includes the alloy of cobalt, titanium, nickel, tungsten, platinum, palladium, molybdenum or above-mentioned metal.
40. method as claimed in claim 30, wherein the temperature of this rapid thermal anneal process is between 400～600 ℃.
41. method as claimed in claim 30, wherein carry out this second ultraviolet ray and quick thermal treatment process after, the adjusted stretching stress state of this second high-tension film is between 0.5～3.0GPa.
42. method as claimed in claim 30, wherein this second high-tension film is in order to conduct contact hole etching stopping layer.
43. method as claimed in claim 30, wherein this first ultraviolet ray and quick thermal treatment process, this rapid thermal anneal process, with this second ultraviolet ray and quick thermal treatment process be to carry out with original position mode or ex situ mode.
44. method as claimed in claim 30, wherein this second ultraviolet ray and quick thermal treatment process are in order to this transition metal silicide layer is transformed into metal silicide layer.
45. method as claimed in claim 30, wherein this transistor comprises nmos pass transistor.
46. ultraviolet ray and fast bench heat treater include:
Reaction chamber is in order to hold at least one wafer;
Load bearing seat is located in this reaction chamber, in order to carry this wafer; And
Ultraviolet light source and heater, this ultraviolet light source and heater include ultraviolet light source and thermal source.
47. ultraviolet ray as claimed in claim 46 and fast bench heat treater, wherein this ultraviolet light source is in order to provide ultraviolet ray, and its wavelength is between 100～400 nanometers.
48. ultraviolet ray as claimed in claim 47 and fast bench heat treater also comprise shutter elements, in order to this ultraviolet passing through of control.
49. ultraviolet ray as claimed in claim 46 and fast bench heat treater, wherein this thermal source includes Halogen lamp LED or LASER Light Source.
50. ultraviolet ray as claimed in claim 46 and fast bench heat treater also comprise the temperature detecting device, in order to detect the temperature of this wafer.
51. ultraviolet ray as claimed in claim 46 and fast bench heat treater, wherein this load bearing seat also includes heating function.
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| CN200710111873XA CN101330022B (en) | 2007-06-20 | 2007-06-20 | Method and platform for making high-tension film |
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| CN200710111873XA CN101330022B (en) | 2007-06-20 | 2007-06-20 | Method and platform for making high-tension film |
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| CN101330022A true CN101330022A (en) | 2008-12-24 |
| CN101330022B CN101330022B (en) | 2012-01-11 |
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Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2013044427A1 (en) * | 2011-09-29 | 2013-04-04 | 中国科学院微电子研究所 | Semiconductor device and method for fabricating same |
| US8652893B2 (en) | 2011-09-29 | 2014-02-18 | Institute of Microelectronics, Chinese Academy of Sciences | Semiconductor device and manufacturing method thereof |
| CN108335973A (en) * | 2018-01-15 | 2018-07-27 | 西安交通大学 | A kind of method that sigmatron prepares strained silicon |
| CN109841687A (en) * | 2017-11-29 | 2019-06-04 | 乐金显示有限公司 | Thin film transistor (TFT) and its manufacturing method and display equipment including the thin film transistor (TFT) |
| CN111199932A (en) * | 2018-11-20 | 2020-05-26 | 南亚科技股份有限公司 | Through silicon via structure and manufacturing method thereof |
Family Cites Families (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5863327A (en) * | 1997-02-10 | 1999-01-26 | Micron Technology, Inc. | Apparatus for forming materials |
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2007
- 2007-06-20 CN CN200710111873XA patent/CN101330022B/en active Active
Cited By (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2013044427A1 (en) * | 2011-09-29 | 2013-04-04 | 中国科学院微电子研究所 | Semiconductor device and method for fabricating same |
| CN103035524A (en) * | 2011-09-29 | 2013-04-10 | 中国科学院微电子研究所 | Semiconductor device and production method thereof |
| US8652893B2 (en) | 2011-09-29 | 2014-02-18 | Institute of Microelectronics, Chinese Academy of Sciences | Semiconductor device and manufacturing method thereof |
| CN103035524B (en) * | 2011-09-29 | 2015-08-05 | 中国科学院微电子研究所 | Semiconductor device and manufacture method thereof |
| CN109841687A (en) * | 2017-11-29 | 2019-06-04 | 乐金显示有限公司 | Thin film transistor (TFT) and its manufacturing method and display equipment including the thin film transistor (TFT) |
| CN108335973A (en) * | 2018-01-15 | 2018-07-27 | 西安交通大学 | A kind of method that sigmatron prepares strained silicon |
| CN111199932A (en) * | 2018-11-20 | 2020-05-26 | 南亚科技股份有限公司 | Through silicon via structure and manufacturing method thereof |
| CN111199932B (en) * | 2018-11-20 | 2022-03-01 | 南亚科技股份有限公司 | Through silicon via structure and manufacturing method thereof |
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| Publication number | Publication date |
|---|---|
| CN101330022B (en) | 2012-01-11 |
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