CN101320970B - Programmable integer/fractional number frequency divider - Google Patents
Programmable integer/fractional number frequency divider Download PDFInfo
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- CN101320970B CN101320970B CN2007101088965A CN200710108896A CN101320970B CN 101320970 B CN101320970 B CN 101320970B CN 2007101088965 A CN2007101088965 A CN 2007101088965A CN 200710108896 A CN200710108896 A CN 200710108896A CN 101320970 B CN101320970 B CN 101320970B
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Abstract
The invention provides a programmable integer/fraction frequency divider, comprising a programmable integer frequency divider and a programmable fraction frequency divider, wherein the divisor of the programmable integer frequency divider can be set as at least a first and a second integer according to a divisor switching signal. The programmable fraction frequency divider computes the pulse number of the output signal of the programmable integer frequency divider, when the pulse number of the output signal is equal to an established pulse number, the divisor switching signal is generated to switch the divisor of the programmable integer frequency divider. The established pulse number is determined by the fraction part of the divisor according to the programmable integer/fraction frequency divider. The fraction frequency divider receives at least one fraction divisor to change the established pulse number, further changing the fraction part.
Description
Technical field
The present invention relates to a kind of programmable frequency divider (Programmable Frequency Divider), and be particularly related to a kind of programmable integer/fractional divider.
Background technology
Tradition is used for being used for the direct frequency division of a high incoming frequency is become an output frequency of desiring for instrument that high-frequency signal carries out frequency division is known as programmable frequency divider or direct programmable frequency divider (Direct Programmable Frequency divider).
Programmable frequency divider adopts two kinds of structures to reach mostly at present.First kind is the frequency divider with pulse/inhibition counter (Pulse/Swallow Counter), be to adopt a bimodulus frequency divider (Dual-modulus divider), a pulse counter and to suppress counter, reach the function of the programmable frequency divider of integer.Its advantage is to design according to the actual divisor scope of using, its shortcoming is only can provide integral frequency divisioil, and central dual-mode frequency divider uses among multimode (Multi-mode) or multiband (Multi-band), can consume a large amount of power, and can't under fixing pattern, do preferable power division three circuit.
Second kind is to adopt a multimode fractional divider (for example being to remove 2 or 2.5 or 3 or 3.5) serial connection one chain type (zipper) frequency divider to reach.This multi-modulus frequency divider uses phase place machine (State Machine) control phase to switch designing employed divisor, and this chain type frequency divider comprises 2 or 3 the bimodulus frequency unit of removing of a plurality of serial connections.The advantage of this structure is fraction division can be provided, yet because multi-modulus frequency divider uses the phase place machine, therefore design and the IPization to high-frequency circuit is quite difficult.In addition, phase place machine in the multi-modulus frequency divider and remaining circuit must be according to employed marks and pre-designed, thereby the selection of mark is little.Person more is because the minimum of the divisor of chain type (zipper) frequency divider is 2
N(N is the number of bimodulus frequency unit), but and cause the divisor of whole program divider limited.The result often must design more multistage bimodulus frequency unit, however the actual divisor scope of using and few.
Summary of the invention
In view of this, the invention provides a kind of programmable frequency divider of arbitrary integer/mark, its divisor minimum is not subject to 2 curtain time and has a more suitable scope, and do not need to consider that earlier its employed mark divisor comes design circuit, only need design earlier to remove the circuit of integer and mark can be adjusted when using, and use in-line memory and be easy to IPization.
The invention provides a kind of integer/fractional divider able to programme, produce an output signal in order to the frequency with an input signal divided by one first divisor, wherein, this first divisor is an integer or mark.This integer/fractional divider able to programme comprises a programmable integer modulus frequency divider and a mark switch.This programmable integer modulus frequency divider produces this output signal with the frequency of this input signal divided by one second divisor, and wherein, this second divisor can be set at first and second integer at least according to a divisor switching signal.In the operation of programmable integer modulus frequency divider, this mark switch synchronously calculates the umber of pulse of this output signal, and when the umber of pulse of this output signal equals a set umber of pulse, produces this divisor switching signal to switch this second divisor.This set umber of pulse determines according to a fractional part of this first divisor.This mark switch is accepted the control of at least one mark divisor control signal with this set umber of pulse of change, and then the fractional part of this first divisor is changed.
In one embodiment, this programmable integer modulus frequency divider (as Fig. 3) comprises a chain type frequency divider and a multi-modulus frequency divider (its initial divisor N
D2).This chain type frequency divider comprises more than one the bimodulus frequency unit of polyphone, and wherein, the divisor of each bimodulus frequency unit can receive other divisor control signal and a mode signal respectively and be set at the 3rd and the 4th integer (as Fig. 2).The divisor switching signal that the mark switch is produced is used as the mode signal of this last bimodulus frequency unit.As if the 3rd integer is N1, then can obtain divisor Z and be
Wherein, N is the number of this bimodulus frequency unit, and N1 is that the 3rd integer, M are integers, DZ
0To DZ
N-1Be respectively 0 or 1.Then with divisor control signal S_CTRL_ (k) level of each bimodulus frequency unit according to DZ
kBe that 1 and 0 to be set at first and second level and to make this set umber of pulse be 2
M/ X can obtain divisor Z, wherein, X be this divisor switching signal make the pulse length of this switching signal equal this output signal pulse length X doubly.
Description of drawings
Fig. 1 is the square construction drawing that shows of the present invention one integer/fractional divider 100 able to programme;
Fig. 2 is the embodiment of structure chart of the programmable integer modulus frequency divider of displayed map 1;
Fig. 3 is another embodiment of structure chart of the programmable integer modulus frequency divider of displayed map 1;
Fig. 4 is the embodiment of structure chart of the programmable integer modulus frequency divider of displayed map 3;
Fig. 5 is another embodiment of structure chart of the programmable integer modulus frequency divider of displayed map 1;
Fig. 6 a-6c is another embodiment of structure chart of the programmable integer modulus frequency divider of displayed map 1; And
Fig. 7 is an embodiment who shows the divisor switch.
The reference numeral explanation
100-integer/fractional divider able to programme
110-programmable integer modulus frequency divider
120-mark switch
The 130-switch
The 320-integer frequency divider
The 421-integer frequency divider
The 422-phase switcher
The 423-memory
The 424-logical circuit
The 530-integer frequency divider
The 610a-c-dual-mode frequency divider
620a-c-mark switch
630a-c-suppresses counter
The 640a-c-pulse counter
The 710-counter
The 720-phase regulator
210 (0) to 210 (2)-bimodulus frequency units
CLK (0) is to CLK (3)-clock signal
CP (0) is to CP (2)-input end of clock
DIN (0) is to DIN (2)-divisor control end
OC (0) is to OC (2)-pattern input
Q (0) is to Q (2)-output terminal of clock
S_CTRL (0, N-1)-the divisor control signal
S_CTRL_2 (0, P-1)-second divisor control signal
S_CTRL_3 (0, Q-1)-the three-divisor control signal
S_CTRL_D-decimal divisor control signal
S_DS-divisor switching signal
The S_IN-input signal
S_MOD and S_MOD (0) are to S_MOD (2)-mode signal
The S_OUT-output signal
So1-first output signal
So2-second output signal
Embodiment
Fig. 1 shows the square construction drawing of of the present invention one integer/fractional divider 100 able to programme, in order to an incoming frequency f
INDivided by a divisor Z, and produce an output frequency f
OUT=f
IN/ Z, wherein, divisor Z is integer or mark arbitrarily.
The typical case, the minimum value of the mark of frequency divider is to provide this incoming frequency f according to one
INThe structure of front stage circuits (not shown) decide.For example, when comprising a frequency divider, this front stage circuits is scheduled to divisor N divided by one with the incoming frequency that another is higher
PAnd produce this incoming frequency f
INThe time, then the minimum value of this mark is chosen as 1/N
P, in order to reduce the influence of phase noise.Such as N
PBe respectively 2 and at 4 o'clock, then the minimum value of mark is respectively 0.5 and 0.25.And in the application scenario of most frequency divider, output frequency f
OUTBe given, so the value of Integer N is according to incoming frequency f
INDecide, the side is so that f
IN/ Z=f
OUT
As shown in this figure, integer/fractional divider 100 able to programme comprises a programmable integer modulus frequency divider 110, one switches 130, and a mark switch 120 is coupled to this programmable integer modulus frequency divider 110.Programmable integer modulus frequency divider 110 is coupled to switch 130.
The divisor N of this programmable integer modulus frequency divider 110
DCan be set at least the first Integer N
S1And second Integer N
S2One of, and in the middle of being preset as.It is this incoming frequency f that this programmable integer modulus frequency divider 110 receives a frequency
INInput signal S_IN, it is also with this incoming frequency f
INDivided by its divisor N
D, and via | it is f that clock signal output terminal OUT_CLK exports a frequency
OUT=f
IN/ N
DOutput signal S_OUT.When carrying out division arithmetic, programmable integer modulus frequency divider 110 receives at least one divisor switching signal from this mark switch 120 simultaneously, be the divisor switching signal S_DS of this figure for example, and whether change its divisor N with decision according to this divisor switching signal S_DS
DIn one embodiment, when this divisor switching signal S_DS was respectively first level and second level, this first programmable integer modulus frequency divider 110 was with its divisor N
DBe set at this Integer N respectively
S1And N
S2
Must note, in one embodiment, the divisor N of programmable integer modulus frequency divider 110
DOnly decide according to a divisor switching signal S_DS from mark switch 120.
Being connected of switch 130 control programmable integer modulus frequency dividers 110 and mark switch 120 makes that switch 130 switches to signal S_OUT when using refining formula structure, and when using pulse/inhibition to count structure, switch 130 switches to signal S_MOD.
This divisor Z and this divisor switching signal S_DS are maintained the time (being the pulse duration of divisor switching signal S_DS) of second level according to set umber of pulse N
PAnd Integer N
S1And N
S2And determine.Now use divisor N
DBe preset as N
S1And the pulse duration that the pulse duration of divisor switching signal S_DS equals output signal S_OUT illustrates.In order to make integer/fractional divider 100 able to programme produce N
PIndividual pulse is this output signal S_OUT, and then input signal S_IN is necessary for N
PZ pulse.Producing this N
PDuring Z the pulse, the dividend N of this input signal S_IN elder generation
S1Remove last (N
P-1) after the individual pulse, dividend N again
S2Remove last 1 pulse.Therefore, N
P* Z=N
S1* (N
P-1)+N
S2* 1.As a result, Z=N
S1* (N
P-1)/N
P+ N
S2/ N
PIn like manner can push away easily, equal when the pulse duration of divisor switching signal S_DS output signal S_OUT pulse duration X doubly, this divisor Z=[N then
S1* (N
P-1)/N
P+ N
S2/ N
P] * X.
Fig. 2 shows the embodiment of structure chart of the programmable integer modulus frequency divider 110 of Fig. 1.As shown in the figure, programmable integer modulus frequency divider 110 is a chain type frequency divider (Zipper divider), and it comprises the individual bimodulus frequency unit 210 (0) to 210 (2) able to programme of N (at this N=3) of serial connection mutually.
Each grade bimodulus frequency unit 210 (k) (wherein, 0≤k≤N-1) have a clock input CP (k) to receive a signal CLK (k), a pattern input MOD (k) to receive a mode signal S_MOD (k), a clock output Q (k) to export a signal CLK_ (k+1), and a pattern output OC (k), intercouple each other and as shown in the figure.Each grade bimodulus frequency unit 210 (k) also has divisor control end DIN (k), is coupled respectively to the divisor control signal S_CTRL (k) that an external circuit (not being shown among the figure) is provided.Input signal S_IN provide to the input end of clock CP (0) of first order bimodulus frequency unit 210 (0) with as CLK (0), and the output signal CK (N) of the output terminal of clock Q (N-1) of afterbody bimodulus frequency unit 210 (N-1) produces this output signal S_OUT as the output signal S_OUT of this programmable integer modulus frequency divider 110.The divisor figure signal S_DS that mark switch 120 is produced is the mode signal S_MOD (N-1) as afterbody bimodulus frequency unit 210 (N-1).
The divisor of each grade bimodulus frequency unit 210 (k) (being defined as the frequency of frequency/signal CLK (k) of signal CLK (k+1)) is respectively 2 and 3 to be represented, and the divisor N of chain type frequency divider 110
DCan be expressed as:
N
D＝2
N+(D
N-1×2
N-1+...+D
1×2
1+D
0×2
0)
Wherein, divisor coefficient D
kThe divisor control signal S_CTRL_ (k) that is received according to divisor control end DIN (k) and mode signal S_MOD (k) to decide be 0 or 1.
Notice, though in the embodiment of this figure, be to be changed to 2 or 3 and to illustrate so that the divisor of each grade bimodulus frequency unit is variable.Yet, in all the other embodiment, can make the divisor of each grade bimodulus frequency unit be transformed to first Integer N 1 and second integer (N1+1), wherein, Integer N 1 is not restricted to 2.At this moment, the divisor Z that can analogize chain type frequency divider 110 easily can be expressed as:
N
D＝N1
N+(D
N-1×2
N-1+...+D
1×2
1+D
0×2
0)
Described in the associated description of Fig. 1, want continuously the pattern output/input control end of central bimodulus frequency unit serial connection logical circuit and suitably change design as before in order to make all integer scopes of application.More details about the chain type frequency divider can be with reference to United States Patent (USP) case numbers 5,065,415,6,281,721, the paper that C.Vaucher and Z.Wang delivered " A low-power truly-modular 1.8 GHzprogrammable divider in standard CMOS technology " (is published in ESSCIRC ' 99.pp.406 409,1999) and by C.Vaucher, I.Ferencic, M.Locher, S.Sedvallson, U.Voegeli, and the paper that the people delivered " A family oflow-power truly modular programmable dividers in standard 0.35-mm CMOStechnology " such as Z.Wang (is published in IEEE J.Solid-State Circuits SC-35, No.7, pp.10391045,2000).At this for simplicity's sake, no longer explaining more.
When divisor switching signal S_DS is first level (high level) and second level (low level), can push away to such an extent that the divisor of chain type frequency divider 110 is respectively N
D1=N1
NAnd N
D2=N1
N+ (D
N-1* 2
N-1+ ...+D
1* 2
1+ D
0* 2
0).Therefore, setting its mark when mark switch 120 is 1/N
P, equal then can obtain divisor Z=N under the pulse duration of output signal S_OUT in the pulse duration of divisor switching signal S_DS
D1* (N
P-1)/N
P+ N
D2/ N
P=N1
N+ (D
N-1* 2
N-1+ ...+D
1* 2
1+ D
0* 2
0)/N
P
Must note, the programmable integer modulus frequency divider 110 of Fig. 1 itself also can comprise that more than one frequency divider is connected in series mutually or its combination is connected in series mutually, as long as be a programmable integer modulus frequency divider one of at least in the middle of this frequency divider, Fang Yineng accepts the control of mark switch and changes its divisor and get final product.
Fig. 3 shows another embodiment of structure chart of the programmable integer modulus frequency divider 110 of Fig. 1, in order to above-mentioned situation to be described.As shown in the figure, programmable integer modulus frequency divider 110 comprises | chain type frequency divider 310, an integer frequency divider 320.The difference of this figure and Fig. 2 only is to increase integer frequency divider 320 between chain type frequency divider (this figure 310) and mark switch 120.Represent with identical cross reference number with the similar assembly of Fig. 2 among this figure, and, seldom do explanation at this for for the purpose of omitting.
When divisor switching signal S_DS is first level (high level) and second level (low level), can push away to such an extent that the whole divisor of chain type frequency divider 310 and integer frequency divider 320 is respectively N
S1=N1
N* N
D2And N
S2=N1
N* N
D2+ (2
N-1* DS
N-1+ 2
N-2* DS
N-2+ ...+2
0* DS
0).Therefore, setting its mark when mark switch 120 is 1/N
P, equal then can obtain divisor Z=N under the pulse duration of output signal S_OUT in the pulse duration of divisor switching signal S_DS
S1* (N
P-1)/N
P+ N
S2/ N
P=N
S1+ (2
0* DS
0+ 2
1* DS
1+ ...+2
N-1* DS
N-1)/N
P, Control Parameter DS wherein
0To DS
N-1Being respectively divisor control signal S_CTRL (0) determines to the level of divisor control signal S_CTRL (N_1).
Comprehensive speech, under the embodiment of the programmable integer modulus frequency divider 110 that adopts present embodiment, the divisor Z of integer/fractional divider able to programme can be expressed as:
Z＝N1
N×N
D2+2
-M×DZ
0+2
-(M-1)×DZ
1+...+2
0×DZ
N-M+...+2
N-M-2×DZ
N-2+2
N-M-1×DZ
N-1。
This figure only is that with the difference of Fig. 2 initial integer is by N1
NChange N1 into
N* N
D2, all the other all together.If need to obtain a divisor Z, must obtain this decomposition coefficient DZ earlier
0To DZ
N-1, and then with level and the set umber of pulse N of the same manner acquisition divisor control signal S_CTRL (0) to the required supply of S_CTRL (N-1)
P
The set umber of pulse of Fig. 2 and Fig. 3 is all N
P=2
MThe reason of/X is: though the divisor switch 210 of Fig. 2 and Fig. 3 is counted to such an extent that umber of pulse can be 1/N in Fig. 2 in Fig. 3 in the same time
D2Doubly, however the pulse duration of divisor switching signal S_DS is the N of pulse duration of the divisor switching signal S_DS of Fig. 2
D2Doubly.Therefore, under the two-phase compensation, set umber of pulse N
PAll equal 2
M/ X.
For example, if need one or three grades (N=3 and N1=2) but the divisor of program integer frequency divider 210 be set at Z=26.5.Because Z=2
3* 3+ (2
-1) * 1+ (2
0) * 0+ (2
1) * 1 (M=1 and X=1), so N
D2Must be set at 3, and this decomposition coefficient DZ
0To DZ
2Be respectively 1,0,1.Similarly, must make divisor control signal S_CTRL (0) equal first level (high level), second level (low level) and first level (high level) respectively and make set umber of pulse N to S_CTRL (2)
P=2.
The integer frequency divider 320 that Fig. 4 shows Fig. 3 changes an embodiment of programmable structure chart into.As shown in the figure, programmable integer modulus frequency divider 320 1 multi-modulus frequency dividers, it comprises an integer frequency divider 421, a phase switcher 422, an in-line memory 423, and a logical circuit 424.
This integer frequency divider 421 receives chain type frequency divider 310 and it is removed an Integer N (being 2 for example), in order to the phase place input of output signal S_P (0) to S_P (N-1) to this phase switcher 422 of out of phase (as 0 and 180) to be provided.The phase transition data DATA_D of two groups of above divisors of memory 423 storages, corresponding different respectively integer divisor N
D2This logical circuit 424, receive at least one second divisor control signal (such as the S_CTRL_2 among the figure (0) is to S_CTRL_2 (P-1)) and divisor switching signal S_DS, and according to the address of this second divisor control signal S_CTRL_2 (0) to S_CTRL_2 (P-1) and divisor switching signal S_DS generation memory 423, and order the memory 423 of this address that phase transition data DATA_D is provided the phase control end to this phase switcher 422.This phase switcher 422 according to receive each phase transition data DATA_D determine output signal what person that is phase input signal S_P (0) to the S_P (N-1) sequentially.Each group phase transition data DATA_D promptly represents its divisor, can make this integer frequency divider 320 have different divisor N
D, be 3,4,5,6 for example.And memory 423 can use in-line memory, has made the phase transition data DATA_D that still can change storage at any time at IC, thereby changes the divisor scope of programmable integer modulus frequency divider 110, and is easy to IPization.
Must notice that the divisor switching signal that divisor switch 120 is produced can not be coupled to single programmable frequency divider, and can be coupled to more than one programmable frequency divider.
Fig. 5 shows another embodiment of structure chart of the programmable integer modulus frequency divider 110 of Fig. 1, in order to this situation to be described.As shown in the figure, the difference of Ben Tu and Fig. 3 only is that the programmable integer modulus frequency divider 110 central chain type frequency dividers 310 that remove couple two integral frequency divisioil unit 520 and 530, and divisor switching signal S_DS also is connected to two integer frequency dividers 520 and 530 by chance.
In one embodiment, when divisor switching signal S_DS is respectively first and second level, the divisor N of integer frequency divider 520
D2Equal N respectively
D21And N
D22, and the divisor N of integer frequency divider 530
D3Equal N respectively
D31And N
D32And when divisor switching signal S_DS is first level (high level), can push away the whole divisor N of chain type frequency divider 310 and integer frequency divider 520,530
S1=N1
N* N
D21* N
D31And when divisor switching signal S_DS is second level (low level), the whole divisor N of chain type frequency divider 310 and integer frequency divider 520,530
S2=N1
N* N
D21* N
D31+ (2
N+P+Q-1* DS
N+P+Q-1+ 2
N+P+Q-2* DS
N+P+Q-2+ ...+2
0* DS
0).
Therefore, setting its mark when mark switch 120 is 1/N
P, make the pulse duration of divisor switching signal S_DS equal then can obtain divisor Z=N under the pulse duration of output signal S_OUT
S1* (N
P-1)/N
P+ N
S2/ N
P=N1
N* N
D21* N
D31+ (2
N+P+Q-1* DS
N+P+Q-1+ 2
N+P+Q-2* DS
N+P+Q-2+ ...+2
0* DS
0)/N
P, Control Parameter DS wherein
0To DS
N+P+Q-1Respectively by divisor control signal S_CTRL (0) to divisor control signal S_CTRL (N-1), and the level of the second divisor control signal S_CTRL_2 (0) to divisor control signal S_CTRL_2 (P-1) and three-divisor control signal S_CTRL_3 (0) to divisor control signal S_CTRL_3 (Q-1) determined.
Comprehensive speech if set set umber of pulse N
P=2
M, under the embodiment of the programmable integer modulus frequency divider 110 that adopts present embodiment, the divisor Z of integer/fractional divider able to programme can be expressed as:
Z＝N1
N×N
D21×N
D31+2
-M×DZ
0+2
-(M-1)×DZ
1+...+2
0×DZ
N+P+Q-M+...+2
N+P+Q-M-2×DZ
N+P+Q-2+2
N+P+Q-M-1×DZ
N+P+Q-1。
This figure only is that with the difference of Fig. 2 initial integer is by N1
NChange N1 into
N* N
D21* N
D31, all the other all together.If need to obtain a divisor Z, must obtain decomposition coefficient DZ earlier
0To DZ
N+P+Q-1, and then according to DZ
0To DZ
N+P+Q-1Obtain respectively divisor control signal S_CTRL_ (0) to S_CTRL_ (N-1) and S_CTRL_2 (0) to S_CTRL_2 (P-1) and S_CTRL_3 (0) to the level and the set umber of pulse N of the required supply of S_CTRL_3 (Q-1)
P
In like manner but class is pushed into the integer frequency divider that is coupled to arbitrary number behind the chain type frequency divider, and divisor switching signal S_DS controls the divisor of arbitrary number integer frequency divider in the middle of the described integer frequency divider.At this for simplicity's sake, seldom do explanation.
Structure shown in Figure 4 also can be used as an embodiment of integer frequency divider 520 and 530.As shown in the figure, integer frequency divider 520 and 320 difference only be in the integer frequency divider 520, logical circuit 424 receive the control of divisor switching signal S_DS and divisor control signal S_CTRL_2 (0) to both control of S_CTRL_2 (P-1) to change its divisor N
D2In preferable example, integer frequency divider 520 more comprises a phase-adjusting circuit, so that divisor switching signal S_DS1 can be synchronous with the first output signal So1 that chain type frequency divider 310 is produced. Integer frequency divider 530 and 320 difference only be to receive in the integer frequency divider 530 divisor control signal S_CTRL_3 (0) to the control of S_CTRL_3 (Q-1) to change its divisor N
D3
Must notice that the embodiment except the structure chart of the integer frequency divider 320 of Fig. 4 also can use the programmable integer modulus frequency divider with pulse/inhibition counter (Pulse/Swallow Counter) to replace integer frequency divider 320.But, itself having the advantage of suitable divisor scope, if combine with refining shape (zipper) structure, can reduce the usefulness of itself on the contrary, therefore, if can make the function that itself has except that mark, also is preferable selection.
Fig. 6 a shows another embodiment of structure chart of integer/fractional divider able to programme 100 of Fig. 1, in order to this situation to be described.As shown in the figure, this figure adopts the idea of Fig. 1 to add mark switch 620a between the input control end of output that suppresses counter 630a and dual-mode frequency divider 610a.The operation principle of this mark switch 620a such as preceding institute tell, and for for the purpose of the omission, seldom do explanation at this.
The divisor Z that just has the integer frequency divider of pulse/inhibition counter can be expressed as Z=P * N1+S, wherein, N1 and the divisor that (N1+1) produces according to the divisor switching signal for dual-mode frequency divider 610a, S is for suppressing the integer numerical value of counter 630a, and P is the integer numerical value of pulse counter 640a.
In one embodiment, when divisor switching signal S_DS was respectively first and second level, the divisor of the output S_OUT of pulse counter 640a equaled N respectively
S1And N
S2And when divisor switching signal S_DS is first level (high level), can push away the whole divisor N of integer frequency divider 100 of pulse/inhibition counter
S1=P * N1.And when divisor switching signal S_DS is second level (low level), the whole divisor N of the integer frequency divider 100 of pulse/inhibition counter
S2=P * N1+S.Therefore, be 1/N when mark switch 620a sets its mark
P, equal to suppress in the pulse duration of divisor switching signal S_DS then can obtain divisor Z=N under the pulse duration of output signal of counter 630a
S1* (N
P-1)/N
P+ N
S2/ N
P=P * N1+S/N
P
Must notice that the integer frequency divider that is subject to pulse/inhibition counter must satisfy P 〉=N1 and P 〉=S, when it is set at the kenel of fractional divider, the not enough state of S can take place, can use the embodiment of Fig. 6 b and Fig. 6 c this moment instead.When replacement (Reset) signal Synchronization of main and auxiliary inhibition counter, need at least one group of auxiliary feedback circuit (suppressing counter and mark switch), the divisor of its frequency divider 100 is Z=P * N1+S
1/ N
P1+ ...+S
N/ N
PN, N wherein
P1＞...＞N
PNAnd P 〉=S
1... S
N(as Fig. 6 b).When replacement (Reset) signal of main with auxiliary inhibition counter staggers the pulse duration of output signal of a dual-mode frequency divider 610, only need one group of auxiliary feedback circuit, the divisor of its frequency divider 100 is Z=P * N1+S
1/ N
P1+ S
2/ N
P2, N wherein
P1＞N
P2And P 〉=S
1And S
2(as Fig. 6 c).
Comprehensive speech if set set umber of pulse N
P=2
M, under the embodiment of the integer/fractional divider 110 with pulse/inhibition counter that adopts present embodiment, the divisor Z of integer/fractional divider able to programme can be expressed as:
Z=P * N1+2
-M1* S
1+ ...+2
-MN* S
N, wherein, M1＞...＞MN and S
1To S
NAll be less than or equal to P.
Fig. 7 shows an embodiment of divisor switch 120.As shown in the figure, divisor commutation circuit 120 comprises a counter 710 and a phase-adjusting circuit 720.Counter 710 receives the second output signal So2, calculates the pulse number of this second output signal So2, and produces this divisor switching signal S_DS according to this pulse number.Phase-adjusting circuit 720 is in order to the phase place of the divisor switching signal S_DS that adjusts it and produce.In the divisor commutation circuit 120 that the embodiment of the programmable integer modulus frequency divider of the 2nd, 3,5,6 figure arranges in pairs or groups mutually, the phase place of divisor switching signal S_DS is adjusted to the Phase synchronization with the output signal (CLK (N-1)) of prime frequency divider.
Must notice that integer/fractional divider able to programme can not only comprise single divisor switch, and can comprise more than one divisor switch, produces at least one divisor switching signal respectively.The counter of this area when can push away more details, seldom do explanation in this omission.
Though the present invention discloses as above with preferred embodiment; right its is not in order to limit the present invention; anyly have the knack of this skill person; without departing from the spirit and scope of the present invention; when doing a little change and retouching; therefore, protection scope of the present invention is as the criterion when looking the claim person of defining of the present invention.
Claims (33)
1. an integer/fractional divider able to programme produces an output signal in order to the frequency with an input signal divided by one first divisor, and wherein, this first divisor is an integer or mark, comprising:
One programmable integer modulus frequency divider, its frequency with this input signal produces this output signal divided by one second divisor, and wherein, this second divisor is set at first and second integer at least according to a divisor switching signal; And
One mark switch, calculate the umber of pulse of this output signal, and when the umber of pulse of this output signal equals a set umber of pulse, produce this divisor switching signal to switch to this second integer from this first integer, wherein, this set umber of pulse determines according to a fractional part of this first divisor, and the control of accepting at least one mark divisor control signal of this mark switch to be changing this set umber of pulse, and then changes the fractional part of this first divisor.
2. integer/fractional divider able to programme as claimed in claim 1, wherein, this programmable integer modulus frequency divider more receives at least one divisor control signal, in order to select the value of this first and second integer according to this divisor control signal.
3. integer/fractional divider able to programme as claimed in claim 1, wherein, set umber of pulse is set at the pulse length of output signal of this integer/fractional divider able to programme divided by the pulse length of this divisor switching signal.
4. integer/fractional divider able to programme as claimed in claim 2, wherein, this first integer be one with the irrelevant integer of this control signal,
This second integer is set at N1 according to this control signal
N+ (N1
N-1* DS
N-1+ N1
N-2* N1
N-2+ ...+N1
0* DS
0), wherein, DS
N-1To DS
0Determine to be 0 or 1 according to this control signal, N, N1 are respectively the 3rd, the 4th integers.
5. integer/fractional divider able to programme as claimed in claim 1, wherein, this programmable integer modulus frequency divider comprises a chain type frequency divider, this chain type frequency divider comprises the bimodulus frequency unit of polyphone more than, wherein, the divisor of each bimodulus frequency unit can receive other divisor control signal and a mode signal respectively and be set at the 3rd and the 4th integer, and this divisor switching signal is used as the mode signal of this last bimodulus frequency unit.
6. integer/fractional divider able to programme as claimed in claim 5, wherein, the 3rd and the 4th integer is respectively 2 and 3.
7. integer/fractional divider able to programme as claimed in claim 5, wherein, this chain type frequency divider receives this input signal, with the frequency of this input signal divided by this second integer after and produce the input signal of this mark switch, this first divisor according to other divisor control signal of each bimodulus frequency unit and mode signal, and this set umber of pulse determine.
8. integer/fractional divider able to programme as claimed in claim 7, wherein:
Z=N1
N+ N1
-M* DZ
0+ N1
-(M-1)* DZ
1+ ...+N1
0* DZ
N-M+ ...+N1
N-M-2* DZ
N-2+ N1
N-M-1* DZ
N-1, wherein, Z is this first divisor, and N is the number of this bimodulus frequency unit, and N1 is the 3rd integer, and M is an integer, DZ
0To DZ
N-1Be respectively 0 or 1, and
Divisor control signal S_CTRL (k) level of each bimodulus frequency unit is according to DZ
kBe 1 and 0 to be set at first and second level.
9. integer/fractional divider able to programme as claimed in claim 8, wherein, this set umber of pulse is (N1)
M/ X, wherein, X be this divisor switching signal make the pulse length of this switching signal equal this output signal pulse length X doubly.
10. integer/fractional divider able to programme as claimed in claim 8 or 9, wherein, the pattern output/input control end of bimodulus frequency unit is connected in series logical circuit, can change first divisor and be:
Z=N1
N+ 2
-M* DZ
0+ 2
-(M-1)* DZ
1+ ...+2
0* DZ
N-M+ ...+2
N-M-2* DZ
N-2+ 2
N-M-1* DZ
N-1, wherein, this set umber of pulse is 2
M/ X.
11. integer/fractional divider able to programme as claimed in claim 10, wherein, this integer frequency divider more comprises one second integer frequency divider, this chain type frequency divider receives this input signal, and this second integer frequency divider with the output signal of this chain type frequency divider divided by one the 5th integer to produce the output signal of this integer frequency divider.
12. integer/fractional divider able to programme as claimed in claim 11, wherein, this first divisor determines according to other divisor control signal of each double frequency frequency unit and the 5th integer and this set umber of pulse.
13. integer/fractional divider able to programme as claimed in claim 12, wherein:
Z＝N1
N×N
D2+2
-M×DZ
0+2
-(M-1)×DZ
1+...+2
0×DZ
N-M+...+2
N-M-2×DZ
N-2+2
N-M-1×DZ
N-
Wherein, Z is this first divisor, and N is the number of this bimodulus frequency unit, and N1 is the 3rd integer, N
D2Be that the 5th integer, M are integers, DZ
0To DZ
N-1Be respectively 0 or 1, and
Divisor control signal S_CTRL (k) level of each bimodulus frequency unit is according to DZ
kBe 1 and 0 to be set at first and second level.
14. integer/fractional divider able to programme as claimed in claim 13, wherein, this set umber of pulse is 2
M/ X, wherein, X be this divisor switching signal make the pulse length of this switching signal equal this output signal pulse length X doubly.
15. integer/fractional divider able to programme as claimed in claim 11, wherein, second integer frequency divider is a multi-modulus frequency divider, and its control that receives at least one second divisor control signal is to change the value of the 5th integer.
16. integer/fractional divider able to programme as claimed in claim 15, wherein, this second integer frequency divider comprises:
One the 3rd integer frequency divider, the output signal frequency that is used for this chain type frequency divider is produced are divided by one the 6th integer, so that the phase place output signal of out of phase to be provided;
One phase switcher is used for the receiving phase translation data and determines that sequentially output signal is corresponding phase place output signal;
One memory, the phase transition data of storing two groups of above divisors, the 6th corresponding different respectively integers; And
One logical circuit, be used to receive at least one the 6th integer control signal and divisor switching signal, and produce the address of memory according to the 6th integer control signal and divisor switching signal, and order the memory of this address that the phase control end of phase transition data to this phase switcher is provided.
17. integer/fractional divider able to programme as claimed in claim 7, wherein, this integer frequency divider more comprises second and third integer frequency divider, this chain type frequency divider receives this input signal, this second integer frequency divider with the output signal of this chain type frequency divider divided by a three-divisor, and receive this divisor switching signal and be at least the five and the 6th integer with the value that changes this three-divisor, and the 3rd integer frequency divider with this second integer frequency divider divided by one the 7th integer to produce the output signal of this integer frequency divider.
18. integer/fractional divider able to programme as claimed in claim 17, wherein, this first divisor is according to other divisor control signal of each double frequency frequency unit, the 5th and the 6th and the 7th integer, and this set umber of pulse and determining.
19. integer/fractional divider able to programme as claimed in claim 18, wherein:
Z=N1
N* (N
D22-N
D21) * N
D3+ 2
-M* DZ
0+ 2
-(M-1)* DZ
1+ ...+2
0* DZ
N-M+ ...+2
N-M-2* DZ
N-2+ 2
N-M-1* DZ
N-1, wherein, N is the number of this bimodulus frequency unit, and N1 is the 3rd integer, and M is an integer, N
D21Be the 5th integer, N
D22Be the 6th integer, and N
D3Be the 7th integer,
DZ
0To DZ
N-1Be respectively 0 or 1, and meet (N1
N* (N
D22-N
D21) * N
D3+ 2
0* DS
0+ 2
1* DS
1+ ...+2
N-1* DS
N-1)=(N1
N* N
D21* N
D3+ 2
0* DZ
0+ 2
1* DZ
1+ ...+2
N+Q-2* DZ
N+Q-2+ 2
N+Q-1* DZ
N+Q-1), and
Divisor control signal S_CTRL (k) level of each the bimodulus frequency unit and second integer frequency divider is according to DZ
kBe 1 and 0 to be set at first and second level, wherein, Q is the number of the divisor control end of this second integer frequency divider.
20. integer/fractional divider able to programme as claimed in claim 19, wherein, this set umber of pulse is 2
M/ X, wherein, X be this divisor switching signal make the pulse length of this switching signal equal this output signal pulse length X doubly.
21. integer/fractional divider able to programme as claimed in claim 17, wherein, this second integer frequency divider is a multi-modulus frequency divider, and its control that receives at least one second divisor control signal is to change the value of the 6th integer.
22. integer/fractional divider able to programme as claimed in claim 17, wherein, the 3rd integer frequency divider is a multi-modulus frequency divider, and its control that receives at least one three-divisor control signal is to change the value of the 7th integer.
23. as claim 17,21 or 22 described integer/fractional dividers able to programme, wherein, this second integer frequency divider comprises:
One phase-adjusting circuit is so that the output signal of the divisor switching signal of this second integer frequency divider output and chain type frequency divider is synchronous.
24. an integer/fractional divider able to programme produces an output signal in order to the frequency with an input signal divided by one first divisor, wherein, this first divisor is an integer or mark, comprising:
One bimodulus frequency divider, divided by one second divisor, wherein, this second divisor is set at first and second integer according to the divisor switching signal with the frequency of this input signal for it; And
One pulse counter calculates the umber of pulse of the output signal of this dual-mode frequency divider, and when this umber of pulse equals one the 3rd integer, produces this output signal; And
One suppresses counter, calculate the umber of pulse of the output signal of this dual-mode frequency divider, and when this umber of pulse equaled one the 4th integer, switching a mode signal was second level, and when this output signal was a set level, this mode signal of resetting was first level; And
One mark switch, calculate the umber of pulse of the mode signal of this inhibition counter, and when this umber of pulse equals a set umber of pulse, produce this divisor switching signal to switch the divisor of this dual-mode frequency divider, wherein, this set umber of pulse determines according to a fractional part of this first divisor, and the control of accepting at least one mark divisor control signal of this mark switch to be changing this set umber of pulse, and then changes the fractional part of this first divisor.
25. integer/fractional divider able to programme as claimed in claim 24, wherein, this mark switch is serially connected with between this inhibition counter and this dual-mode frequency divider, this first and second integer is continuous, the 3rd integer must be more than or equal to this first and the 4th integer, wherein, this first divisor is according to this first, the 3rd and the 4th integer, and this set umber of pulse and determining.
26. integer/fractional divider able to programme as claimed in claim 25, wherein:
Z=P * N1+2
-M* S, wherein, N1, P, S are this first, the 3rd and the 4th integers, M is an integer.
27. integer/fractional divider able to programme as claimed in claim 26, wherein, this set umber of pulse is 2
M/ X, wherein, X be this divisor switching signal make the pulse length of this switching signal equal this output signal pulse length X doubly.
28. integer/fractional divider able to programme as claimed in claim 26 more comprises:
Increase an at least one auxiliary inhibition counter and an auxiliary mark switch, only equal the 3rd integer of this pulse counter in order to the greatest measure of the 4th integer of setting this inhibition counter; And
Set this inhibition counter, this at least one auxiliary inhibition counter, this mark switch, and the control signal of this at least one auxiliary mark switch be respectively different integers, serve as continuous with the scope that satisfies this first divisor.
29. integer/fractional divider able to programme as claimed in claim 28, wherein:
Z=P * N1+2
-M1* S
1+ ...+2
-MN* S
N, wherein, N1 is this first integer, P is the 3rd integer, S
1To S
NBe the 4th integer row, M1 to MN is an integer row, and M1＞...＞MN and P 〉=S
1... S
N
30. integer/fractional divider able to programme as claimed in claim 29, wherein, the set umber of pulse of this each mark switch is respectively 2
M1/ X...2
MN/ X, wherein, X be this divisor switching signal make the pulse length of this switching signal equal this output signal pulse length X doubly.
31. integer/fractional divider able to programme as claimed in claim 28, wherein:
When the reset signal of this inhibition counter and this at least one auxiliary inhibition counter staggers the pulse duration of output signal of a dual-mode frequency divider, the quantity of this inhibition counter and this at least one auxiliary inhibition counter respectively is 1, serves as continuous with the scope that satisfies this first divisor.
32. integer/fractional divider able to programme as claimed in claim 31, wherein:
Z=P * N1+2
-M1* S
1+ 2
-M2* S
N, wherein, N1 is this first integer, P is the 3rd integer, S
1And S
2Be the 4th integer row, M1 and M2 are integer row, and M1＞M2 and P 〉=S
1And S
2
33. integer/fractional divider able to programme as claimed in claim 32, wherein, this set umber of pulse is respectively 2
M1/ X and 2
M2/ X, wherein, X be this divisor switching signal make the pulse length of this switching signal equal this output signal pulse length X doubly.
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| CN107222206B (en) * | 2017-05-23 | 2019-11-05 | 电子科技大学 | A kind of high-speed programmable arbitrary integer frequency divider |
| TWI648528B (en) * | 2017-11-23 | 2019-01-21 | 財團法人工業技術研究院 | Resistive gas sensor and gas sensing method thereof |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5111487A (en) * | 1989-07-24 | 1992-05-05 | Motorola, Inc. | Electronic timer apparatus |
| CN1180960A (en) * | 1996-08-30 | 1998-05-06 | 株式会社东芝 | Counter and semiconductor memory including counter |
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2007
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5111487A (en) * | 1989-07-24 | 1992-05-05 | Motorola, Inc. | Electronic timer apparatus |
| CN1180960A (en) * | 1996-08-30 | 1998-05-06 | 株式会社东芝 | Counter and semiconductor memory including counter |
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