CN101312499B - Video processor capable of recombination and application apparatus thereof - Google Patents
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Abstract
The invention provides a reconfigurable image processor and an application device, for reducing the cost of image treatment. The reconfigurable image processor comprises an operation module, a first memory unit, a bus control module and a connecting module. The application device of the reconfigurable image processor comprises a sensing module, a display module, a second memory unit and a reconfigurable image processor. The invention modifies the structure of the prior preview engine into a reconfigurable structure, and therefore the reconfigurable image processor can realize image preview mode and image pickup mode via a single hardware structure without other hardware and eliminating the elasticity of the hardware structure, to realize two image processing modes. The invention can reduce the image processing cost significantly, improve the image processing speed, and keep the hardware structure of high elasticity.
Description
Technical field
The present invention relates to a kind of image processing technique, relate in particular to video processor capable of recombination and application apparatus thereof.
Background technology
At present, digitized video is widely used in various fields and the electronic product.Digital camera is for producing the modal method of digitized video.Generally speaking, digital camera has the function of bimodulus (dual mode), promptly has image preview mode (preview mode) and image capture pattern.The image preview mode is to show the preview image on display module fast.So, under the image preview mode, image is had the demand of (real-time) in real time.Therefore, the resolution of image input can be fallen lowlyer, and the image preview mode also is applied to support digital camera to take video signal.In addition, the image capture pattern is the image that is used to capture complete resolution.So, image is had the demand of high-quality (high quality).Because high-quality image will be stored in the internal memory, image there is not the demand of (real-time) in real time.
The image processor of the digital camera of industrial quarters extensive use at present mainly contains two kinds: first kind is to use digital signal processor (digital signal processor, DSP) cooperate specific preview engine (preview engine), (Integrated Circuit IC) realizes with integrated circuit again.Aforesaid implementation is so that two groups of hardware circuits are incorporated in the integrated circuit.Under the image preview mode, data flow directly exports on the display module, with quick demonstration preview image after handling via the preview engine.So data flow is not handled via digital signal processor.Under the image capture pattern, data flow via digital signal processor processes after, be stored in the internal memory.So data flow is not handled via the preview engine.The advantage of this practice is owing to have digital signal processor, when image capture, can at random change algorithm, so the elasticity height.The shortcoming of this practice is, need prepare two kinds of hardware for two kinds of patterns, and under the image capture pattern, adopts digital signal processor, and processing speed is slower.
Second kind be to use Application Specific Integrated Circuit (Application Specific Integrated Circuit, ASIC).Also promptly, algorithm and the processing procedure with required use realizes with integrated circuit.The advantage of this practice is, because the process of image processing is all with the specific hardware realization, so the ability of image processing is strong.The shortcoming of this practice is, owing to the algorithm that can't replace Application Specific Integrated Circuit inside, so elasticity is not good.Because hardware designs need be taken into account the situation of two kinds of most criticals simultaneously, promptly the demand of real-time requirement and high image quality so the mode of this realization is difficult to make image processing to obtain optimization, often causes the too much investment of hardware.
Summary of the invention
For overcoming defective of the prior art and deficiency, the object of the present invention is to provide a kind of video processor capable of recombination and application apparatus thereof, to reduce the cost of image processing.
To achieve the above object of the invention, the technical scheme of video processor capable of recombination of the present invention is as follows:
A kind of video processor capable of recombination comprises:
Computing module has a plurality of arithmetic elements of recombinating, and by the described arithmetic element of recombinating of recombinating, makes the described arithmetic element of recombinating carry out the action of correspondence;
First mnemon couples described computing module, stores multiple setting configuration;
Bus control module couples described first mnemon and a system bus, in order to couple external device (ED);
On-line module couples described computing module, described first mnemon and described bus control module, by described setting configuration, and described on-line module the online of the described arithmetic element of recombinating of can recombinating.
Wherein, described bus control module comprises:
Input unit, described input unit couples described on-line module;
Output unit, described output unit couples described on-line module;
Bus bridge unit, described bus bridge unit couple described input unit, described output unit, described first mnemon and described system bus.
Wherein, described on-line module has a plurality of multiplexers.
Wherein, by described setting configuration,, make described on-line module the online of the described arithmetic element of recombinating of can recombinating to control the on-line mode of described multiplexer.
Wherein, described first mnemon is at least one configuration internal memory.
Wherein, the described arithmetic element of recombinating individually comprises:
Configuration registers couples described first mnemon;
The input selected cell couples described on-line module and described configuration registers;
Core cell couples described configuration registers and described input selected cell, in order to carry out data operation;
Output state couples described on-line module and described core cell, in order to store dateout;
Module control unit couples described configuration registers, described core cell and described output state.
Wherein, described module control unit is imported one first synchronizing signal.
Wherein, described module control unit is exported one second synchronizing signal.
Wherein, when the described arithmetic element of recombinating operates, handle the operational data and first synchronizing signal, described first synchronizing signal of described module control unit interpretation, and described module control unit is controlled described core cell, so that in the working hour, the acquisition valid data, and produce second synchronizing signal to next stage.
Wherein, by the setting configuration in the described configuration registers, can individually control described configuration registers, described input selected cell, described core cell, described output state and the indivedual corresponding actions of described module control unit execution.
Wherein, the described arithmetic element of recombinating is a restructuring colour filter array interpolation unit, in order to Bel's format image is redeveloped into the RGB image.
Wherein, described restructuring colour filter array interpolation unit comprises one first interpolative operation device, one second interpolative operation device and one the 3rd interpolative operation device, the described first interpolative operation device is carried out the diagonal angle data operation of a bayer color filter array, the described second interpolative operation device is carried out the cross data operation of described bayer color filter array, and described the 3rd interpolative operation device is done final computing.
Wherein, the described arithmetic element of recombinating is a restructuring pixel processing unit, plants the image processing computing in order to carry out plural number, and described image processing computing comprises colour correction and white balance at least.
Wherein, described restructuring pixel processing unit comprises and looks into forms units and an adder and multiplier.
Wherein, the described arithmetic element of recombinating is a restructuring row cache device, and described row cache device comprises:
A plurality of multiplexers;
A plurality of line buffers, described line buffer couple corresponding described multiplexer.
Wherein, the described arithmetic element of recombinating is a restructuring windows cache device, and described windows cache device comprises:
A plurality of multiplexers;
A plurality of buffers, described buffer couple corresponding described multiplexer.
Wherein, a plurality of row cache devices couple corresponding a plurality of windows cache devices and form the quick accessed cache device matrix that N takes advantage of N, and wherein, N is an integer.
Wherein, the described arithmetic element of recombinating is a restructuring multiplier accumulator unit, comprises a plurality of adder and multipliers, an adder and a sorting network.
Wherein, the described arithmetic element of recombinating is that a restructuring image dwindles the unit.
Wherein, the described arithmetic element of recombinating is a restructuring ALU, and described restructuring ALU has at least one basic processing unit, and described basic processing unit comprises a comparator, arithmetical logic device and multiplier at least.
Wherein, described restructuring ALU is carried out a specific program, and described specific program is stored in described first mnemon.
To achieve the above object of the invention, the technical scheme of the application apparatus of video processor capable of recombination of the present invention is as follows:
A kind of application apparatus of video processor capable of recombination comprises:
Sensing module is used to obtain an original sense data;
Display module;
Second mnemon;
One video processor capable of recombination, described video processor capable of recombination couples described sensing module, display module and described second mnemon, and have: computing module, have a plurality of arithmetic elements of recombinating, by the described arithmetic element of recombinating of recombinating, make the described arithmetic element of recombinating carry out corresponding action; First mnemon couples described computing module, stores multiple setting configuration; Bus control module couples described first mnemon and a system bus, in order to couple external device (ED); On-line module couples described computing module, described first mnemon and described bus control module, by described setting configuration, and described on-line module the online of the described arithmetic element of recombinating of can recombinating;
By replacing described setting configuration, described video processor capable of recombination can be recombinated inner online, carrying out corresponding action, and handles described original sense data.
Wherein, when carrying out an image preview mode, to described first mnemon, load corresponding described setting configuration, after described sensing module is imported described video processor capable of recombination with an original sense data,, described first sense data is carried out A image processing computing to obtain a preview image by handling the described sense data sense data of can winning, export described preview image to described display module, wherein, A＞=1, and A is an integer.
Wherein, when the image capture pattern of execution, to described first mnemon, load corresponding described setting configuration, described sensing module can get second sense data by handling described sense data after one original sense data is imported described video processor capable of recombination, and described second sense data is carried out B image processing computing to obtain a pick-up image, described pick-up image is stored to described second mnemon, wherein, B＞=1, and B is an integer.
Wherein, the data volume of second sense data is greater than the data volume of first sense data.
Wherein, described sensing module is for having a complementary metal oxide silicon assembly or a Charged Coupled Device.
Wherein, described display module has a LCD.
Wherein, described bus control module comprises:
Input unit, described input unit couples described on-line module;
Output unit, described output unit couples described on-line module;
Bus bridge unit, described bus bridge unit couple described input unit, described output unit, described first mnemon and described system bus.
Wherein, described on-line module has a plurality of multiplexers.
Wherein, by described setting configuration,, make described on-line module described online between arithmetic element of recombinating of can recombinating to control the on-line mode of described multiplexer.
Wherein, described first mnemon is at least one configuration internal memory.
Wherein, the described arithmetic element of recombinating individually comprises:
Configuration registers couples described first mnemon;
The input selected cell couples described on-line module and described configuration registers;
Core cell couples described configuration registers and described input selected cell, in order to carry out data operation;
Output state couples described on-line module and described core cell, in order to store dateout;
Module control unit couples described configuration registers, described core cell and described output state.
Wherein, described module control unit is imported one first synchronizing signal.
Wherein, described module control unit is exported one second synchronizing signal.
Wherein, when the described arithmetic element of recombinating operates, handle an operational data and one first synchronizing signal, described first synchronizing signal of described module control unit interpretation, and described module control unit is controlled described core cell, so that in the working hour, the acquisition valid data, and produce described one second synchronizing signal to next stage.
Wherein, by the setting configuration in the described configuration registers, can individually control described configuration registers, described input selected cell, described core cell, described output state and the indivedual corresponding actions of described module control unit execution.
Wherein, the described arithmetic element of recombinating is a restructuring colour filter array interpolation unit, in order to Bel's format image is redeveloped into the RGB image.
Wherein, described restructuring colour filter array interpolation unit comprises one first interpolative operation device, one second interpolative operation device and one the 3rd interpolative operation device, the described first interpolative operation device is carried out the diagonal angle data operation of a bayer color filter array, the described second interpolative operation device is carried out the cross data operation of described bayer color filter array, and described the 3rd interpolative operation device is done final computing.
Wherein, the described arithmetic element of recombinating is a restructuring pixel processing unit, plants the image processing computing in order to carry out plural number, and described image processing computing comprises colour correction and white balance at least.
Wherein, described restructuring pixel processing unit comprises and looks into forms units and an adder and multiplier.
Wherein, the described arithmetic element of recombinating is a restructuring row cache device, and described row cache device comprises:
A plurality of multiplexers;
A plurality of line buffers, described line buffer couple corresponding described multiplexer.
Wherein, the described arithmetic element of recombinating is a restructuring windows cache device, and described windows cache device comprises:
A plurality of multiplexers;
Wherein, a plurality of buffers, described buffer couple corresponding described multiplexer.
Wherein, a plurality of row cache devices couple corresponding a plurality of windows cache devices and form the quick accessed cache device matrix that N takes advantage of N, and to handle different size online image datas, wherein, N is an integer.
Wherein, the described arithmetic element of recombinating is a restructuring multiplier accumulator unit, comprises a plurality of adder and multipliers, an adder and a sorting network.
Wherein, the described arithmetic element of recombinating is that a restructuring image dwindles the unit.
Wherein, the described arithmetic element of recombinating is a restructuring ALU, and described restructuring ALU has at least one basic processing unit, and described basic processing unit comprises a comparator, arithmetical logic device and multiplier at least.
Wherein, described restructuring ALU is carried out a specific program, and described specific program is stored in described first mnemon.
Wherein, by a system bus, described video processor capable of recombination couples at least one external microprocessor.
Comprehensively above-mentioned, the present invention proposes a kind of video processor capable of recombination and its application apparatus, is suitable for image processing.Because the computing of image processing, has the height isomorphism type, so the present invention will have the framework of preview engine now and be modified as the restructuring device, make video processor capable of recombination realize image preview mode and image capture pattern by single hardware structure, and needn't use two cover hardware, also needn't sacrifice the elasticity of hardware structure, can realize two kinds of image processing patterns.Therefore, the present invention not only can make the cost of image processing significantly reduce, and can strengthen the speed of image processing, and makes hardware structure keep the elasticity of height.
Description of drawings
Fig. 1 is the functional block diagram according to the video processor capable of recombination of a preferred embodiment of the present invention;
Fig. 2 is the functional block diagram of the recombinated arithmetic element of a preferred embodiment of the present invention;
Fig. 3 is the functional block diagram of the single restructuring row cache device of a preferred embodiment of the present invention;
Fig. 4 is the functional block diagram that two restructuring windows cache devices are taken advantage of in two of a preferred embodiment of the present invention;
Fig. 5 is the functional block diagram that three restructuring windows cache devices are taken advantage of in three of a preferred embodiment of the present invention;
Fig. 6 is the schematic diagram that three quick accessed cache device matrixes are taken advantage of in three of a preferred embodiment of the present invention;
Fig. 7 is the schematic diagram that five quick accessed cache device matrixes are taken advantage of in five of a preferred embodiment of the present invention;
Fig. 8 is the functional block diagram of application apparatus of the video processor capable of recombination of a preferred embodiment of the present invention;
Fig. 9 is the schematic diagram of the data flow of the original sense data of a preferred embodiment of the present invention in preview mode;
Figure 10 is the schematic diagram of the data flow of the original sense data of a preferred embodiment of the present invention in the image capture pattern;
Figure 11 is the functional block diagram of application apparatus of the video processor capable of recombination of another preferred embodiment of the present invention;
Figure 12 is the usefulness schematic diagram of the video processor capable of recombination of a preferred embodiment of the present invention;
Figure 13 is the usefulness schematic diagram of the video processor capable of recombination of another preferred embodiment of the present invention.
Embodiment
Describe the present invention in detail below in conjunction with the drawings and specific embodiments.
Fig. 1 is the functional block diagram according to the video processor capable of recombination of a preferred embodiment of the present invention.Video processor capable of recombination 100 comprises computing module 102, first mnemon 104, bus control module 106 and on-line module 108.First mnemon 104 couples computing module 102.Bus control module 106 couples first mnemon 104 and system bus 10.On-line module 108 couples computing module 102, first mnemon 104 and bus control module 106.
Wherein, computing module 102 has a plurality of arithmetic elements of recombinating, and these arithmetic elements of can recombinating individually couple on-line module 108.The arithmetic element of can recombinating is that restructuring colour filter array interpolation unit 110, restructuring pixel processing unit 112, restructuring row cache device 114, restructuring windows cache device 116, restructuring multiplier accumulator unit 118, restructuring image dwindle unit 120 and restructuring ALU 122.Moreover bus control module 106 comprises input unit 124, bus bridge unit 126 and output unit 128.Input unit 124 individually couples on-line module 108 with output unit 128.Bus bridge unit 126 couples input unit 124, output unit 128, first mnemon 104 and system bus 10.In addition, this first mnemon is made of at least one group of configuration internal memory (context memory).
Fig. 2 is the functional block diagram according to the recombinated arithmetic element of a preferred embodiment of the present invention.In conjunction with shown in Figure 1, the arithmetic element of can recombinating 200 comprises configuration registers 202, input selected cell 204, core cell 206, output state 208 and module control unit 210.Wherein, configuration registers 202 couples first mnemon 104.Input selected cell 204 couples on-line module 108 and configuration registers 202.Core cell 206 couples configuration registers 202 and input selected cell 204, in order to carry out data operation.Output state 208 couples on-line module 108 and core cell 206, in order to store dateout.Module control unit 210 couples configuration registers 202, core cell 206 and output state 208 and aforementioned on-line module 108, to transmit synchronizing signal.
Wherein, module control unit 210 inputs first synchronizing signal and output second synchronizing signal.In the time can recombinating arithmetic element 200 runnings, by first synchronizing signal, module control unit 210 interpretations first synchronizing signal is to handle operational data.And, module control unit 210 control core cells 206, so that in working hour, the acquisition valid data, and produce second synchronizing signal and give next stage.Moreover, by the setting configuration in the configuration registers 202, the arithmetic element of can recombinating 200 can be via the different setting configuration of displacement, individually to control configuration registers 202, input selected cell 204, core cell 206, output state 208 and the indivedual corresponding actions of module control unit 210 execution.Also be, restructuring colour filter array interpolation unit 110, restructuring pixel processing unit 112, restructuring row cache device 114, restructuring windows cache device 116, restructuring multiplier accumulator unit 118, it is all identical with the arithmetic element 200 of can recombinating with the basic structure of restructuring ALU 122 inside that the restructuring image dwindles unit 120, by replacing different configurations, make the arithmetic element 200 of to recombinate have different structures and different functions, so that carry out corresponding action, this partly for the application of existing restructuring (reconfigurable) or programmable (programmable) semiconductor technology, does not repeat them here.
When the arithmetic element 200 of can recombinating during, in order to being RGB (RGB) image with Bel's form (BayerPattern) image reconstruction for restructuring colour filter array interpolation unit.Restructuring colour filter array interpolation unit 110 more comprises the first interpolative operation device, the second interpolative operation device and the 3rd interpolative operation device (aforementioned three arithmetic units are not drawn) in figure.The first interpolative operation device carry out bayer color filter array (Bayer filter array interpolation) to angular data (diagonal angle of matrix is element partly) computing, the second interpolative operation device is carried out cross (cross of matrix the is element partly) data operation of this bayer color filter array, the operation result of the 3rd interpolative operation device integration first interpolative operation device and the second interpolative operation device, and do final computing.
When the arithmetic element 200 of can recombinating is the restructuring pixel processing unit, then plant the image processing computing, for example: colour correction (color correction), white balance (white balance) in order to carry out plural number.Wherein, the restructuring pixel processing unit more comprise look into forms unit (look up table) and adder and multiplier (multiplier and accumulator, MAC).When the arithmetic element 200 of can recombinating was restructuring row cache device, then the row cache device more comprised a plurality of multiplexers and a plurality of line buffer (line buffer).A plurality of line buffers couple corresponding multiplexer.When the arithmetic element 200 of can recombinating was restructuring windows cache device, the windows cache device more comprised a plurality of multiplexers and a plurality of buffer.Buffer couples corresponding multiplexer.Fig. 3 is the functional block diagram according to the single restructuring row cache device of a preferred embodiment of the present invention, and single restructuring row cache device comprises multiplexer 302 and line buffer 304.Fig. 4 is a functional block diagram of taking advantage of two restructuring windows cache devices according to two of a preferred embodiment of the present invention.Two take advantage of two restructuring windows cache devices to comprise two multiplexers 402 and four buffers 404.Fig. 5 is a functional block diagram of taking advantage of three restructuring windows cache devices according to three of a preferred embodiment of the present invention.Three take advantage of three restructuring windows cache devices to comprise three multiplexers 502 and nine buffers 504.
A plurality of row cache devices couple corresponding a plurality of windows cache devices and form the quick accessed cache device matrix that N takes advantage of N, and to handle the image data of different sizes, wherein, N is an integer.Line buffer is for needing the internal memory of addressing, and cost is lower, and buffer does not need addressing, but direct access, but cost is higher.Because quick accessed cache device matrix is formed by line buffer serial connection line buffer, so video processor capable of recombination can be once or direct access bidimensional image data for several times, and do not need to calculate the address of image data in internal memory again.Also promptly,, use quick accessed cache device matrix efficiently data to be taken out, carry out computing to input to other arithmetic element of can recombinating because the computing major part of image processing all is the computing (window basedoperation) of window form.Fig. 6 is a schematic diagram of taking advantage of three quick accessed cache device matrixes according to three of a preferred embodiment of the present invention.Three take advantage of three quick accessed cache device matrixes to be made up of with buffer 604 a plurality of line buffers 602.Fig. 7 is a schematic diagram of taking advantage of five quick accessed cache device matrixes according to five of a preferred embodiment of the present invention.Five take advantage of five quick accessed cache device matrixes by a plurality of line buffers and 702 and buffer 704 formed.
When the arithmetic element 200 of can recombinating was the restructuring multiplier accumulator unit, the restructuring multiplier accumulator unit can be made of a plurality of adder and multipliers, an adder and a sorting network (sorting network).Dwindle the unit when the arithmetic element 200 of can recombinating also can be the restructuring image, with so that image frame can dwindle.When the arithmetic element 200 of can recombinating was the restructuring ALU, the restructuring ALU had at least one basic processing unit.Basic processing unit comprises comparator, arithmetical logic device and multiplier at least.And the restructuring ALU is carried out specific program, and specific program is stored in first mnemon.
Fig. 8 is the functional block diagram according to the application apparatus of the video processor capable of recombination of a preferred embodiment of the present invention.In conjunction with shown in Figure 1, the application apparatus of video processor capable of recombination comprises video processor capable of recombination 100, sensing module 2, display module 4, second mnemon 6.Wherein, sensing module 2 is in order to obtain original sense data.The framework of video processor capable of recombination 100 no longer repeats at this with identical shown in the 1st figure.Video processor capable of recombination 100 couples sensing module 2, display module 4 and second mnemon 6, and has at least one group of setting of first mnemon 104, the first mnemons, 104 storages configuration.By replacing different setting configurations, video processor capable of recombination 100 can be recombinated inner online, makes the application apparatus of video processor capable of recombination carry out corresponding action, and handles original sense data.Wherein, sensing module 2 have complementary metal oxide silicon (Complementary Metal Oxide Semiconductor, CMOS) assembly or Charged Coupled Device (Charge Coupled Device, CCD).Display module 4 is a LCD.
When the application apparatus of video processor capable of recombination is carried out image preview (preview) pattern, load corresponding setting configuration in video processor capable of recombination 100 to first mnemons 104.Afterwards, sensing module 2 is with original sense data input video processor capable of recombination, by handling the sense data sense data of can winning, first sense data is carried out A image processing computing to obtain the preview image, export the preview image to display module 4, wherein, A＞=1, and A is an integer.That is the data flow of original sense data is shown in the dotted line 11 of Fig. 9.Because original sense data is processed into the first less sense data of pixel, adds first sense data only by better simply algorithm process, thus the recombinated arithmetic element of minority only used, so the preview image can export display module 4 fast to.Because the image preview mode needs real-time imaging, so the realistic purposes of image preview mode of this framework.
When the application apparatus of video processor capable of recombination is carried out the image capture pattern, load corresponding setting configuration in video processor capable of recombination to the first mnemon 104.Afterwards, sensing module 2 is with original sense data input video processor capable of recombination, by handling sense data and access second mnemon 6, second sense data is carried out B image processing computing to obtain pick-up image, pick-up image is stored to this second mnemon, wherein, B＞=1, and B is an integer.That is the data flow of original sense data is shown in the dotted line 12 and dotted line 13 of the 10th figure.Because original sense data is processed into the second more sense data of pixel, adding second sense data needs by the algorithm process of (multi-pass) more repeatedly, so use most recombinated arithmetic elements, and continuous access second mnemon 6, at last, pick-up image is stored in second mnemon 6.Therefore, image capture pattern consumed time is more.Because the image capture pattern does not need real-time imaging, so the realistic purposes of image capture pattern of this framework.
What deserves to be explained is that the data volume of second sense data is greater than the data volume of first sense data.And this framework only uses single hardware structure by the different setting configuration of displacement, can finish the data processing of image preview (preview) pattern and image capture pattern.
Figure 11 is the functional block diagram according to the application apparatus of the video processor capable of recombination of another preferred embodiment of the present invention.In conjunction with Fig. 1 and shown in Figure 8, each functional block diagram shown in Figure 11 is equal to Fig. 1 and Fig. 8, no longer repeats at this.Different is that by system bus 10, this video processor capable of recombination can couple at least one external microprocessor 8.
Figure 12 is the usefulness schematic diagram according to the video processor capable of recombination of a preferred embodiment of the present invention.As shown in figure 12, when the image preview mode,, can use comparatively simple algorithm because the pixel of handling is less.Therefore, by replacing corresponding configuration, the video processor capable of recombination configuration is become the preview engine, so that in a working hour, export image to display module in real time.Thus, just can effectively reduce hardware cost.
Figure 13 is the usefulness schematic diagram according to the video processor capable of recombination of another preferred embodiment of the present invention.As shown in figure 13, when the image capture pattern, because the pixel of handling is more, so need use comparatively complicated algorithm.Therefore, by the corresponding configuration of continuous displacement, the video processor capable of recombination configuration is become image acquisition chip, make video processor capable of recombination in different working hours, configuration becomes different hardware configurations, carries out different algorithms, process image data several times.Because the image capture pattern does not have real-time requirement, so can allow processing repeatedly.Thus,, all reuse the hardware of video processor capable of recombination inside, therefore can significantly reduce the cost of hardware no matter be image preview mode or image capture pattern.Moreover, owing to the characteristic of video processor capable of recombination at image processing designs, so compare compared to digital signal processor, video processor capable of recombination of the present invention not only structurally is more suitable for doing image processing, and can reach processing speed faster.
As shown in figure 13, image data is divided into the configuration mode of repeatedly handling and is divided into two kinds.If there are six kinds of algorithms of ABCDEF to do, but then image is divided into two zones: 0 and 1.Wherein, A0 is meant and carries out the A computing on 0 zone, and A1 carries out the A computing on 1 zone, and all the other computings by that analogy.First kind of mode is, in regular turn ABCDEF is loaded video processor capable of recombination, all handle whole picture each time, for example: handle A0, A1, B0, B1 in first working hour, next working hour is handled C0, C1, D0, D1 again, and the 3rd working hour handled E0, E1, F0, F1 again.The second way is, first in regular turn processing region 0 is processing region 1 again, and for example: first period is handled A0, B0, C0, D0, and second period handled E0, F0, and the A1 of processing region 1, B1, and the 3rd period handled C1, D1, E1, F1 again.Thus,, can make video processor capable of recombination flexibly change the function of internal hardware,, can effectively reduce hardware cost to carry out different algorithms by replacing different configurations.
In sum, the present invention by replacing different configurations, makes single hardware structure can carry out two kinds of image modes, to reduce cost based on engine.
It should be noted that above-mentioned explanation only is in order to explain the present invention, and be not in order to limiting operational feasibility of the present invention that the purpose of narration specific details is for the present invention is at large understood.Yet, have the knack of this skill person when knowing this also not exclusive solution.Do not running counter to the spirit or disclosed substantive characteristics following of invention, the above embodiments can other special shape present, and the patent claim of enclosing subsequently is then in order to definition the present invention.
Claims (48)
1. video processor capable of recombination is characterized in that comprising:
Computing module has a plurality of arithmetic elements of recombinating, and by the described arithmetic element of recombinating of recombinating, makes the described arithmetic element of recombinating carry out the action of correspondence;
First mnemon couples described computing module, stores multiple setting configuration;
Bus control module couples described first mnemon and a system bus, in order to couple external device (ED);
On-line module couples described computing module, described first mnemon and described bus control module, by described setting configuration, and described on-line module the online of the described arithmetic element of recombinating of can recombinating.
2. video processor capable of recombination according to claim 1 is characterized in that, described bus control module comprises:
Input unit, described input unit couples described on-line module;
Output unit, described output unit couples described on-line module;
Bus bridge unit, described bus bridge unit couple described input unit, described output unit, described first mnemon and described system bus.
3. video processor capable of recombination according to claim 1 is characterized in that described on-line module has a plurality of multiplexers.
4. video processor capable of recombination according to claim 3 is characterized in that, by described setting configuration, to control the on-line mode of described multiplexer, makes described on-line module the online of the described arithmetic element of recombinating of can recombinating.
5. video processor capable of recombination according to claim 1 is characterized in that, described first mnemon is at least one configuration internal memory.
6. video processor capable of recombination according to claim 1 is characterized in that, the described arithmetic element of recombinating individually comprises:
Configuration registers couples described first mnemon;
The input selected cell couples described on-line module and described configuration registers;
Core cell couples described configuration registers and described input selected cell, in order to carry out data operation;
Output state couples described on-line module and described core cell, in order to store dateout;
Module control unit couples described configuration registers, described core cell and described output state.
7. video processor capable of recombination according to claim 6 is characterized in that, described module control unit is imported one first synchronizing signal.
8. video processor capable of recombination according to claim 6 is characterized in that, described module control unit is exported one second synchronizing signal.
9. video processor capable of recombination according to claim 6, it is characterized in that, when the described arithmetic element of recombinating operates, handle the operational data and first synchronizing signal, described first synchronizing signal of described module control unit interpretation, and, described module control unit is controlled described core cell, so that in the working hour, the acquisition valid data, and produce second synchronizing signal to next stage.
10. video processor capable of recombination according to claim 6, it is characterized in that, by the setting configuration in the described configuration registers, can individually control described configuration registers, described input selected cell, described core cell, described output state and the indivedual corresponding actions of described module control unit execution.
11. video processor capable of recombination according to claim 1 is characterized in that, the described arithmetic element of recombinating is a restructuring colour filter array interpolation unit, in order to Bel's format image is redeveloped into the RGB image.
12. video processor capable of recombination according to claim 11, it is characterized in that, described restructuring colour filter array interpolation unit comprises one first interpolative operation device, one second interpolative operation device and one the 3rd interpolative operation device, the described first interpolative operation device is carried out the diagonal angle data operation of a bayer color filter array, the described second interpolative operation device is carried out the cross data operation of described bayer color filter array, and described the 3rd interpolative operation device is done final computing.
13. video processor capable of recombination according to claim 1, it is characterized in that, the described arithmetic element of recombinating is a restructuring pixel processing unit, plants the image processing computing in order to carry out plural number, and described image processing computing comprises colour correction and white balance at least.
14. video processor capable of recombination according to claim 13 is characterized in that, described restructuring pixel processing unit comprises looks into a forms unit and an adder and multiplier.
15. video processor capable of recombination according to claim 1 is characterized in that, the described arithmetic element of recombinating is a restructuring row cache device, and described row cache device comprises:
A plurality of multiplexers;
A plurality of line buffers, described line buffer couple corresponding described multiplexer.
16. video processor capable of recombination according to claim 1 is characterized in that, the described arithmetic element of recombinating is a restructuring windows cache device, and described windows cache device comprises:
A plurality of multiplexers;
A plurality of buffers, described buffer couple corresponding described multiplexer.
17. video processor capable of recombination according to claim 15 is characterized in that, a plurality of row cache devices couple corresponding a plurality of windows cache devices and form the quick accessed cache device matrix that N takes advantage of N, and wherein, N is an integer.
18. video processor capable of recombination according to claim 1 is characterized in that, the described arithmetic element of recombinating is a restructuring multiplier accumulator unit, comprises a plurality of adder and multipliers, an adder and a sorting network.
19. video processor capable of recombination according to claim 1 is characterized in that, the described arithmetic element of recombinating is that a restructuring image dwindles the unit.
20. video processor capable of recombination according to claim 1, it is characterized in that, the described arithmetic element of recombinating is a restructuring ALU, described restructuring ALU has at least one basic processing unit, and described basic processing unit comprises a comparator, arithmetical logic device and multiplier at least.
21. video processor capable of recombination according to claim 20 is characterized in that, described restructuring ALU is carried out a specific program, and described specific program is stored in described first mnemon.
22. the application apparatus of a video processor capable of recombination is characterized in that comprising:
Sensing module is used to obtain an original sense data;
Display module;
Second mnemon;
One video processor capable of recombination, described video processor capable of recombination couples described sensing module, display module and described second mnemon, and have: computing module, have a plurality of arithmetic elements of recombinating, by the described arithmetic element of recombinating of recombinating, make the described arithmetic element of recombinating carry out corresponding action; First mnemon couples described computing module, stores multiple setting configuration; Bus control module couples described first mnemon and a system bus, in order to couple external device (ED); On-line module couples described computing module, described first mnemon and described bus control module, by described setting configuration, and described on-line module the online of the described arithmetic element of recombinating of can recombinating;
By replacing described setting configuration, described video processor capable of recombination can be recombinated inner online, carrying out corresponding action, and handles described original sense data.
23. the application apparatus of video processor capable of recombination according to claim 22, it is characterized in that, when carrying out an image preview mode, to described first mnemon, load corresponding described setting configuration, after described sensing module is imported described video processor capable of recombination with an original sense data, by handling the described sense data sense data of can winning, described first sense data is carried out A image processing computing to obtain a preview image, export described preview image to described display module, wherein, A＞=1, and A is an integer.
24. the application apparatus of video processor capable of recombination according to claim 23, it is characterized in that, when the image capture pattern of execution, to described first mnemon, load corresponding described setting configuration, after described sensing module is imported described video processor capable of recombination with an original sense data, can get second sense data by handling described sense data, described second sense data is carried out B image processing computing to obtain a pick-up image, described pick-up image is stored to described second mnemon, wherein, B＞=1, and B is an integer.
25. the application apparatus of video processor capable of recombination according to claim 24 is characterized in that, the data volume of second sense data is greater than the data volume of first sense data.
26. the application apparatus of video processor capable of recombination according to claim 22 is characterized in that, described sensing module is for having a complementary metal oxide silicon assembly or a Charged Coupled Device.
27. the application apparatus of video processor capable of recombination according to claim 22 is characterized in that, described display module has a LCD.
28. the application apparatus of video processor capable of recombination according to claim 22 is characterized in that, described bus control module comprises:
Input unit, described input unit couples described on-line module;
Output unit, described output unit couples described on-line module;
Bus bridge unit, described bus bridge unit couple described input unit, described output unit, described first mnemon and described system bus.
29. the application apparatus of video processor capable of recombination according to claim 22 is characterized in that, described on-line module has a plurality of multiplexers.
30. the application apparatus of video processor capable of recombination according to claim 29 is characterized in that, by described setting configuration, to control the on-line mode of described multiplexer, makes described on-line module described online between arithmetic element of recombinating of can recombinating.
31. the application apparatus of video processor capable of recombination according to claim 22 is characterized in that, described first mnemon is at least one configuration internal memory.
32. the application apparatus of video processor capable of recombination according to claim 22 is characterized in that, the described arithmetic element of recombinating individually comprises:
Configuration registers couples described first mnemon;
The input selected cell couples described on-line module and described configuration registers;
Core cell couples described configuration registers and described input selected cell, in order to carry out data operation;
Output state couples described on-line module and described core cell, in order to store dateout;
Module control unit couples described configuration registers, described core cell and described output state.
33. the application apparatus of video processor capable of recombination according to claim 32 is characterized in that, described module control unit is imported one first synchronizing signal.
34. the application apparatus of video processor capable of recombination according to claim 32 is characterized in that, described module control unit is exported one second synchronizing signal.
35. the application apparatus of video processor capable of recombination according to claim 32, it is characterized in that, when the described arithmetic element of recombinating operates, handle an operational data and one first synchronizing signal, described first synchronizing signal of described module control unit interpretation, and, described module control unit is controlled described core cell, so that in the working hour, the acquisition valid data, and produce described one second synchronizing signal to next stage.
36. the application apparatus of video processor capable of recombination according to claim 32, it is characterized in that, by the setting configuration in the described configuration registers, can individually control described configuration registers, described input selected cell, described core cell, described output state and the indivedual corresponding actions of described module control unit execution.
37. the application apparatus of video processor capable of recombination according to claim 22 is characterized in that, the described arithmetic element of recombinating is a restructuring colour filter array interpolation unit, in order to Bel's format image is redeveloped into the RGB image.
38. application apparatus according to the described video processor capable of recombination of claim 37, it is characterized in that, described restructuring colour filter array interpolation unit comprises one first interpolative operation device, one second interpolative operation device and one the 3rd interpolative operation device, the described first interpolative operation device is carried out the diagonal angle data operation of a bayer color filter array, the described second interpolative operation device is carried out the cross data operation of described bayer color filter array, and described the 3rd interpolative operation device is done final computing.
39. the application apparatus of video processor capable of recombination according to claim 22, it is characterized in that, the described arithmetic element of recombinating is a restructuring pixel processing unit, plants the image processing computing in order to carry out plural number, and described image processing computing comprises colour correction and white balance at least.
40. the application apparatus according to the described video processor capable of recombination of claim 39 is characterized in that, described restructuring pixel processing unit comprises looks into a forms unit and an adder and multiplier.
41. the application apparatus of video processor capable of recombination according to claim 22 is characterized in that, the described arithmetic element of recombinating is a restructuring row cache device, and described row cache device comprises:
A plurality of multiplexers;
A plurality of line buffers, described line buffer couple corresponding described multiplexer.
42. the application apparatus of video processor capable of recombination according to claim 22 is characterized in that, the described arithmetic element of recombinating is a restructuring windows cache device, and described windows cache device comprises:
A plurality of multiplexers;
A plurality of buffers, described buffer couple corresponding described multiplexer.
43. application apparatus according to the described video processor capable of recombination of claim 41, it is characterized in that a plurality of row cache devices couple corresponding a plurality of windows cache devices and form the quick accessed cache device matrix that N takes advantage of N, to handle different size online image datas, wherein, N is an integer.
44. the application apparatus of video processor capable of recombination according to claim 22 is characterized in that, the described arithmetic element of recombinating is a restructuring multiplier accumulator unit, comprises a plurality of adder and multipliers, an adder and a sorting network.
45. the application apparatus of video processor capable of recombination according to claim 22 is characterized in that, the described arithmetic element of recombinating is that a restructuring image dwindles the unit.
46. the application apparatus of video processor capable of recombination according to claim 22, it is characterized in that, the described arithmetic element of recombinating is a restructuring ALU, described restructuring ALU has at least one basic processing unit, and described basic processing unit comprises a comparator, arithmetical logic device and multiplier at least.
47. the application apparatus of video processor capable of recombination according to claim 22 is characterized in that, described restructuring ALU is carried out a specific program, and described specific program is stored in described first mnemon.
48. the application apparatus of video processor capable of recombination according to claim 22 is characterized in that, by a system bus, described video processor capable of recombination couples at least one external microprocessor.
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| JP6876233B2 (en) * | 2016-09-26 | 2021-05-26 | 富士フイルムビジネスイノベーション株式会社 | Image forming device and program |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6597394B1 (en) * | 1997-11-16 | 2003-07-22 | Pictos Technologies, Inc. | Programmable image transform processor for digital image processing |
| CN2650175Y (en) * | 2003-06-12 | 2004-10-20 | 智基科技开发股份有限公司 | Complementary metal oxide semiconductor digital camera |
| US20060098111A1 (en) * | 2004-11-10 | 2006-05-11 | Samsung Techwin Co., Ltd. | Digital photographing apparatus that performs integrated display mode and method of controlling the same |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6597394B1 (en) * | 1997-11-16 | 2003-07-22 | Pictos Technologies, Inc. | Programmable image transform processor for digital image processing |
| CN2650175Y (en) * | 2003-06-12 | 2004-10-20 | 智基科技开发股份有限公司 | Complementary metal oxide semiconductor digital camera |
| US20060098111A1 (en) * | 2004-11-10 | 2006-05-11 | Samsung Techwin Co., Ltd. | Digital photographing apparatus that performs integrated display mode and method of controlling the same |
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