CN101312385A - Information encoding and decoding method and apparatus - Google Patents
Information encoding and decoding method and apparatus Download PDFInfo
- Publication number
- CN101312385A CN101312385A CNA2007101093291A CN200710109329A CN101312385A CN 101312385 A CN101312385 A CN 101312385A CN A2007101093291 A CNA2007101093291 A CN A2007101093291A CN 200710109329 A CN200710109329 A CN 200710109329A CN 101312385 A CN101312385 A CN 101312385A
- Authority
- CN
- China
- Prior art keywords
- information
- piece
- line coding
- coding
- check information
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Images
Classifications
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L1/00—Arrangements for detecting or preventing errors in the information received
- H04L1/004—Arrangements for detecting or preventing errors in the information received by using forward error control
Landscapes
- Engineering & Computer Science (AREA)
- Computer Networks & Wireless Communication (AREA)
- Signal Processing (AREA)
- Detection And Prevention Of Errors In Transmission (AREA)
- Synchronisation In Digital Transmission Systems (AREA)
Abstract
The invention relates to the communication field, and discloses a method and a device for encoding-decoding information, which increases the encoding gain without changing the frame structure. In the method and the device of the invention, when in generation of check information blocks, partial bits in check synchronous heads of the check information blocks are utilized to carry partial check information, and then according to the bits carrying the partial check information, residual bits in the check synchronous heads are generated. Forward error correction (FEC) coding is carried out to significant bits in synchronous heads of information data and line code blocks after line coding to obtain the check information, and the significant bits are the bits of the type instructing the information data in the same line code block.
Description
Technical field
The present invention relates to the communications field, particularly information coding and decoding technology.
Background technology
Along with the continuous development of the communication technology, the user is more and more higher to the requirement of the various service quality such as capacity, speed of communication.Because Access Network is one of the challenging zone that possesses skills most in the whole telecommunications network, therefore in order to satisfy user's requirement growing, the high speed of realization Access Network, broadband and intelligent, the appearance that various access technologies emerge in an endless stream to bandwidth.Wherein, being considered to the most promising is EPON (Passive Optical Network is called for short " PON ") technology.
The PON technology is the optical fiber access technology of point to multiple spot.PON is made up of optical line terminal, optical network unit (Optical Network Unit is called for short " ONU ") and Optical Distribution Network (Optical DistributionNetwork is called for short " ODN ").Wherein Ethernet passive optical network (Ethernet Passive OpticalNetwork is called for short " EPON ") technology is a kind of reasonable access technology.Its main feature is to safeguard simple, and cost is lower, higher transmission bandwidth and high performance price ratio.Particularly the EPON technology can provide 1GHz (GHz) even to the bandwidth of 10GHz, this makes that transmitting voice, data and video traffic simultaneously becomes possibility.
Because EPON is a kind of technology that adopts the passive light transmission, does not use the components and parts with amplification and relay function.Therefore the transmission range and the number of branches of EPON network depend on power budget and various loss.Along with the increase of transmission range or branching ratio number, the signal to noise ratio of transmission data (Signal NoiseRatio is called for short " SNR ") reduces gradually, thereby has just caused the more bits mistake.In order to address this problem, in the EPON system, to have introduced forward error correction (Forward Error Correction is called for short " FEC ") technology and improved the antijamming capability of system, to increase the power budget of system.
The basic functional principle of FEC in the EPON system is: affix FEC check code word behind the ethernet frame that transmitting terminal is transmitted, these check code words with by the ethernet frame data of verification with certain regular interrelated (constraint) of determining, receiving terminal is by the set rule test ethernet frame data and the relation of check code word, in case make a mistake in the transmission, will destroy this relation, thereby realize error correction ethernet frame data.The FEC technology makes every effort to correct mistake as much as possible with the least possible check byte, finds the balance point an of the best between expense (increased check byte and bring expense) and the coding gain that obtains.
In the EPON system, for the data that make transmission are forms that receiver can receive, before adopting the FEC technology, need to use the line coding technology, this line coding must guarantee that also the data that sent have enough switchings (i.e. conversion between 0,1) to guarantee that receiving terminal can recovered clock.It is a kind of with the method for alignment of data to word that line coder also provides, and circuit can keep good dc balance simultaneously.
In the standard relevant, used the higher line coding mechanism of code efficiencies such as 64b/66b at Physical Coding Sublayer (Physical CodingSublayer is called for short " PCS ") with the EPON system.This line coding has used the scrambler mode that has non-scrambler synchronization character and control character.
64b/66b line coding mechanism is on the basis of 64 bit informations, has increased the synchronization character (claiming synchronous head again) of 2 bits.This 2 bit synchronous character under normal circumstances has only " 01 " or " 10 " these two kinds possibilities.Wherein, synchronization character is that " 01 " expression 64 bits all are data; Synchronization character is for comprising data and control information in " 10 " expression 64 bit informations.Mistake for having taken place in " 00 " or " 11 " expression transmission course in synchronization character.Simultaneously, the use of this synchronization character guaranteed the transmission data every 66 bits at least conversion once, this mode is convenient to realize piece synchronously (block synchronization).The information of 64 bits is carried out scrambling by a kind of motor synchronizing scrambling mechanism, has guaranteed that to the full extent institute's transmission information has enough switchings, is convenient to the clock recovery of receiving terminal.
At present, as shown in Figure 1 at the scheme of a kind of FEC coding of the PCS layer in the 10G EPON system.Left-half is an information data to be verified among Fig. 1, and right half part is the check information that is associated with this information data.Specifically, the Ethernet data that enters the PCS layer is earlier through the 64b/66b line coding, and forming with 66 bits is the line coding piece (shown in Fig. 1 left-half) of unit.When the number of line coding piece reaches FEC and encodes desired data length, carry out the FEC coding.Through obtaining the check information that length is the multiple of 64 bits behind the FEC coding.Forming this check information a plurality of is the check block of unit with 64 bits.The verification synchronous head " 00 " that adds 2 bits then in the front of first check block, the verification synchronous head " 11 " that adds 2 bits in remaining check block front, to be that the check block of unit forms with 66 bits with 64 bits be the check information piece (shown in Fig. 1 right half part) of unit, that is to say, comprised verification synchronous head and check block in the check information piece.The multiple that information data behind the process FEC system coding and check information are 66 bits.
Because information data is through line coding, contain the synchronous head of 2 bits in the line coding piece of per 66 bits, this 2 bit is inequality always.And 2 bits of the verification synchronous head in the check information piece are always identical.Therefore can utilize these information to realize the synchronous of check information piece and line coding piece simultaneously, thereby be convenient to carry out FEC decoding and circuit decoding at receiving terminal.
Yet the present inventor finds, in above-mentioned prior art, adds 2 bit verification synchronous heads (i.e. " 11 " or " 00 ") in the check block front that with 64 bits is unit and has realized the synchronous of check information piece, but the performance raising of FEC coding is not had help.This be because, though the bit number in the check information piece is total up to 66 bits, the bit number that is used for information data is carried out verification still has only 64 bits, 2 bits of increase only be used to realize the check information piece synchronously.That is to say that under the situation that has increased by 2 overhead bits, the gain of acquisition is less relatively.
In addition, prior art is to carry out the FEC coding through the data behind the line coding, and through comprising redundant information (being 2 bit synchronous heads of line coding piece) in the data behind the line coding, that is to say that FEC also is used as the FEC coded data to the redundant information of line coding and partly encodes, reduced the performance of FEC coding.
Summary of the invention
Embodiment of the present invention provides a kind of information encoding and decoding method and device, makes system under the situation that does not change frame structure, has improved coding gain.
For solving the problems of the technologies described above, embodiments of the present invention provide a kind of information coding method, comprise following steps:
When generating the check information piece, X bit predetermined in the verification synchronous head of this check information piece is inserted the part check information, generates remaining Y bit in this verification synchronous head according to the check information of this X bit;
Wherein, X and Y are positive integer.
Embodiments of the present invention also provide a kind of information decoding method, comprise following steps:
X bit acquisition unit predetermined from the verification synchronous head of check information piece is divided verification information, according to the check information that carries outside the verification synchronous head in this part check information and this check information piece, the line coding piece corresponding with this check information piece deciphered, and wherein X is a positive integer.
Embodiments of the present invention also provide a kind of information coding device, comprise:
Insert module, be used for the part check information is inserted the predetermined X bit of verification synchronous head of check information piece;
Generation module is used for generating the remaining Y bit of verification synchronous head according to the check information of X bit;
Wherein, X and Y are positive integer.
Embodiments of the present invention also provide a kind of information decoding device, comprise:
Acquisition module is used for obtaining check information from the check information piece, and wherein part check information predetermined X bit from the verification synchronous head of this check information piece obtains, and X is a positive integer;
Decoding module, the check information pair line coding piece corresponding with this check information piece that is used for obtaining according to acquisition module deciphered.
Embodiment of the present invention compared with prior art, the main distinction and effect thereof are:
When generating the check information piece, utilize the partial bit in the verification synchronous head of this check information piece to come the bearing part check information, generate remaining bits in this verification synchronous head according to the bit of this bearing part check information again.Thereby do not changing frame structure, do not increasing under the situation of complexity, using, improving coding gain, increasing the power budget of system being used for synchronous information in the check information piece of the prior art.
Description of drawings
Fig. 1 is at the information coding method schematic diagram of the PCS layer in the 10G EPON system in the prior art;
Fig. 2 is the information coding method flow chart according to first embodiment of the invention;
Fig. 3 is the information coding method schematic diagram according to first embodiment of the invention;
Fig. 4 is the information decoding method flow diagram according to second embodiment of the invention;
Fig. 5 is the information decoding method schematic diagram according to second embodiment of the invention;
Fig. 6 is the schematic diagram that comprises the line coding piece synchronous head of 2 bits according to information to be verified in the first embodiment of the invention;
Fig. 7 is the schematic diagram that information to be verified does not comprise the less important bit in the line coding piece synchronous head in the information coding method according to third embodiment of the invention;
Fig. 8 is the schematic diagram that does not participate in the FEC coding according to the less important bit that 64b/66b line coder in the third embodiment of the invention generates;
Fig. 9 is the information coding method flow chart according to third embodiment of the invention;
Figure 10 is the information coding method schematic diagram according to third embodiment of the invention;
Figure 11 is the information decoding method schematic diagram according to four embodiment of the invention;
Figure 12 is the structural representation according to the information coding device of fifth embodiment of the invention;
Figure 13 is the structural representation according to the information coding device of sixth embodiment of the invention;
Figure 14 is the structural representation according to the information decoding device of seventh embodiment of the invention.
Embodiment
For making the purpose, technical solutions and advantages of the present invention clearer, embodiments of the present invention are described in further detail below in conjunction with accompanying drawing.
First execution mode of the present invention relates to a kind of information coding method, information coding method in the present embodiment is applied to the line coding piece in the EPON system is encoded, the verification synchronous head of the check information piece that generates is 2 bits, and idiographic flow as shown in Figure 2.
In step 210, transmitting terminal with information data from the form of Reconciliation Sublayer with ethernet data frame (Ethernetpacket), be sent to the PCS layer by Ethernet media independent interface, the 64b/66b line coder carries out line coding by the type of transfer information data to it then, and the type of information data is divided into the data of clear data and band control information.
Specifically, after data are sent to the PCS layer from Ethernet media independent interface, be that unit is divided into the little block message of K with the information data that receives with 64 bits by 64 bit information modules.Then, by the 64b/66b line coder every little block message is carried out line coding, promptly add the synchronous head of 2 bits in every fritter information front, a bit in the synchronous head has carried the information of indicating data type in this block of information, as shown in Figure 3.
Then, enter step 220, will be sent to scrambler through the line coding piece of 64b/66b line coding and carry out the scrambling processing, enough switchings are arranged, be convenient to the clock recovery of receiving terminal to guarantee institute's transmission information to the full extent.That is to say, each the line coding piece behind the 64b/66b line coding is carried out scrambling (added 2 bit synchronous heads do not participate in this scrambling before each line coding piece), the information data S in the line coding piece after the scrambling again
i(i=0,1 ... K) expression in each the line coding piece after the scrambling, comprises the information data of the synchronous head and 64 bits of 2 bits, as shown in Figure 3.
Then, enter step 230, code word buffer memory/order module is arrived in the line coding block movement after scrambling.Code word buffer memory/order module is carried out caching process to the data of receiving, after the data of code word buffer memory/order module reception reach the desired length of FEC encoder, the data that receive are sorted, form a FEC coded frame, and this FEC coded frame is sent to the FEC encoder.As shown in Figure 3, the line coding piece is carried out buffer memory, when the data length of the line coding piece of buffer memory satisfies the desired length of FEC encoder, it is sent to the FEC encoder, the data length (i.e. FEC coded frame) that is sent to the FEC encoder is 66 * K bit.
Then, enter step 240, the FEC encoder carries out the FEC coding to the information that is received, and generates corresponding check information, and the length of the check information of generation is 65 multiple, as 65 * M bit, as shown in Figure 3, P
iPiece (i=1,2 ... the check information that is generation of carrying M).
Specifically, the FEC encoder carries out the FEC coding to the FEC coded frame of receiving, promptly the line coding piece after scrambling is carried out the FEC coding, generates corresponding check information.Exist restriction relation between check information and the line coding piece, strengthened the antijamming capability of line coding piece just because of this restriction relation.
Then, enter step 250, the FEC code word behind the FEC coding is sent to check word synchronous head maker, and check word synchronous head maker generates the check information piece that comprises verification block sum check synchronous head.Specifically, as shown in Figure 3, be each P
iPiece adds 1 bit information, the value of this bit information and this P
iThe value of the 1st bit of piece is identical, this bit of interpolation and this P
iThe 1st bit of piece constitutes the verification synchronous head of check information piece jointly.Such as, P
iThe 1st bit of piece is " 1 ", so, can one of (or after this bit) interpolation be the bit of " 1 " before this bit, and value has constituted the verification synchronous head of this check information piece jointly for two bits of " 11 ".Thereby formed with 66 bits is the check information piece of unit, and this length is that preceding 2 bits in the check information piece of 66 bits are the verification synchronous head, this length is that second bit to last bit in the check information piece of 66 bits is a check information, that is to say, second bit both had been used for the synchronous of check information piece in the check information piece, was used for the verification to information data again.Verification synchronous head in each check information piece is for information data in the FEC coding codeword and check information being made a distinction, promptly being used to distinguish S
iPiece and P
iPiece.
Preceding 2 bits are the verification synchronous head in the check information piece if continue to use, back 64 notions that bit is a check block, and so, it is the P of 65 bits that present embodiment can be understood as length
i64 bits in the piece are inserted in the check block, and remaining 1 bit is inserted the verification synchronous head, and the value of another bit is set to the value that equates with this bit in the verification synchronous head.
Owing to have a bit to carry check information in the verification synchronous head of 2 bits, so can have 65 bits to carry check information in each check information piece.Compared with prior art; present embodiment is not increasing system complexity and is changing under the situation of system frame structure; use being used for synchronous bit in the verification synchronous head in the verification block of information; allowing has more check digit that information data is protected in the FEC coding; thereby improved the coding gain of FEC, and then increased the power budget of EPON system.
And the value by another bit in the verification synchronous head is set to the value that equates with the bit of carrying check information in the verification synchronous head, makes the verification synchronous head have the equal characteristic of bit value.Because the synchronous head of the line coding piece that the via line coding generates is " 01 ", or " 10 ", and the verification synchronous head that generates in the present embodiment only may be " 00 " or " 11 ", therefore, can make things convenient for receiving terminal to utilize the inequality of line coding piece synchronous head and the characteristic that equates of verification synchronous head to carry out the synchronous of line coding block sum check block of information.Such as receiving terminal can be " 00 " (or " 11 ") by synchronous head, and still directly to judge this piece be line coding piece or check information piece in " 10 " (or " 01 "), thus carry out piece synchronously.
Then, enter step 260, the line coding piece in FEC code word part partly is sent to into reorganization, the framing that frame module carries out data with the check information piece, be sent to the physical medium additional sub with the form of frame and send.As shown in Figure 3, line coding block sum check block of information is recombinated and framing, carry out being sent to the physical medium additional sub again after code check is in harmonious proportion and send.
What deserves to be mentioned is, in the present embodiment be after finishing line coding, before the line coding piece carried out FEC coding, information data is carried out scrambling, but in actual applications, also can conducting transmission line before the coding, earlier information data is carried out scrambling, again the information data after scrambling is carried out line coding.In addition, in actual applications, the line coding of employing also can be a 32b/34b coding (or other n/ (n+2) coded system), and the check information length of generation is 33 bits (or n+1 bits), specific implementation and present embodiment are similar, do not repeat them here.
Second execution mode of the present invention relates to a kind of information decoding method, and present embodiment is corresponding to the information coding method of first execution mode, and idiographic flow as shown in Figure 4.
In step 410, the information that the physical medium additional sub will receive from the relevant sublayer of physical medium is carried out frame synchronization.Specifically, the physical medium additional sub is sent to fec frame and line coding piece synchronization module with the information that receives, and utilizes the inequality of line coding synchronous head and the characteristic that equates of verification synchronous head to finish the synchronous of line coding block sum check block of information.
Then, enter step 420, finish line coding block sum check block of information synchronously after, first bit in each check information piece is got rid of.Owing to have a bit to carry the part check information in the verification synchronous head of check information piece, and the verification synchronous head of 2 bits is " 00 " or " 11 ", has the identical characteristic of bit value, therefore, as long as remove a bit in the verification synchronous head, just can obtain the check information that carries in this check information piece, be convenient to the FEC decoding of carrying out later.
Then, enter step 430, with the line coding piece after synchronously be removed the check information piece of a bit in the verification synchronous head, deliver to FEC code word order module and carry out the ordering of fec frame, when the data in the FEC code word order module constitute a fec frame, this fec frame is sent to the FEC decoder, as shown in Figure 5.
Then, enter step 440, the FEC decoder is deciphered the fec frame that is received, and the information data with synchronous head in the line coding piece and 64 bits in decode procedure (is S
iPiece) recover, simultaneously with the check information of redundancy, i.e. P
iPiece removes, as shown in Figure 5.
Specifically, the FEC decoder is according to the check information that carries in the verification synchronous head that obtains, and the check information that carries except that the verification synchronous head in the check information piece, and the line coding piece corresponding with this check information piece carried out FEC decoding.This FEC decoder carries out FEC decoding to the line coding piece corresponding with this check information piece in the following manner: the synchronous head to the information data in the line coding piece and this line coding piece carries out FEC decoding.
Then, enter step 450, to carry out segmentation through the information after the FEC decoding, that is to say, to be divided into K section (promptly being divided into K line coding piece) through the information after the FEC decoding, the synchronous head of the line coding piece of every section via line information encoded data that comprise 64 bits and 2 bits, as shown in Figure 5.
Then, enter step 460, the information that is divided into the K section is carried out descrambling, that is to say, the information data in K the line coding piece is carried out descrambling.
Then, enter step 470, the K behind the descrambling line coding piece carried out the decoding of 64b/66b circuit.Specifically, synchronous head in information data in each line coding piece behind the descrambling and this line coding piece is carried out the decoding of 64b/66b circuit, and the information that will finish after the 64b/66b circuit decoding is sent to Reconciliation Sublayer by Ethernet media independent interface, as shown in Figure 5.
What deserves to be mentioned is, because in first execution mode is after finishing line coding, before the line coding piece carried out FEC coding, information data is carried out scrambling, therefore present embodiment need carry out between FEC decoding and the decoding of 64b/66b circuit the information data in K the line coding piece being carried out descrambling.If be before conducting transmission line is encoded in first execution mode, earlier information data is carried out scrambling, again the information data after scrambling is carried out line coding, then in the present embodiment, need after finishing the decoding of 64b/66b circuit, carry out the descrambling of information data again.
The 3rd execution mode of the present invention relates to a kind of information coding method, the present embodiment and first execution mode are roughly the same, its difference is, in the first embodiment, by information data in the line coding piece behind the via line coding and synchronous head are carried out the FEC coding, obtain check information, as shown in Figure 6; And in the present embodiment, by information data in the line coding piece behind the via line coding and the significant bits in the synchronous head are carried out the FEC coding, obtain check information, as shown in Figure 7, this significant bits is the bit that is used for indicating the type of same line coding piece information data.
Specifically, because after the information data of 64 bits is carried out the 64b/66b line coding, in the line coding piece synchronous head of 2 bits that generate, a bit is arranged except that being used for piece also is used to indicate this line coding piece information data synchronously type, therefore, this bit can be considered as significant bits, another bit is considered as less important bit, and, because 2 bit synchronous heads in the line coding piece have the characteristic (being " 01 " or " 10 ") of inequality, that is to say, can obtain this less important bit by negate to significant bits.Therefore, the information data of 64 bits and this significant bits input data bit as the FEC encoder can be sent in code word buffer memory/order module, be sent to the FEC encoder when data bit in code word buffer memory/order module constitutes a FEC coded frame data by the time more in the lump and carry out the FEC coding; And the less important bit in the line coding piece synchronous head does not participate in this FEC coding, as shown in Figure 8.This scheme can be so that the less important information bit of the check information block protection of identical size, thereby has improved the performance of FEC coding.
The flow chart of present embodiment and schematic diagram are respectively as Fig. 9 and shown in Figure 10.Through having only one of them significant bits to participate in the FEC coding in the line coding piece synchronous head behind the 64b/66b line coding, therefore participating in FEC information encoded length is the multiple of 65 bits, and the check information length that generates through FEC coding back still is the multiple of 65 bits.The generation method of check information piece is identical with first execution mode, and second bit in each check information piece both had been used for the synchronous of check information piece, was used for the verification to information data again.
This shows; owing to there is a bit not participate in the FEC coding in the line coding piece synchronous head; effectively reduced the amount of information that needs by the FEC coding protection; make more check bit protect to the least possible Useful Information data; thereby obtain bigger coding gain, increased the power budget of EPON system.And because the bit that is used for the designation data type has been carried out the FEC coding protection, bigger coding gain can improve the correct probability that the data type is judged.
The 4th execution mode of the present invention relates to a kind of information decoding method, and present embodiment is corresponding to the information coding method of the 3rd execution mode.Therefore, the present embodiment and second execution mode are roughly the same, its difference is, in second execution mode, receiving terminal is that the synchronous head to the information data in the line coding piece and this line coding piece carries out FEC decoding, after finishing FEC decoding, the information of carrying out the decoding of 64b/66b circuit is information data in the line coding piece after FEC decoding and the synchronous head in this line coding piece; And in the present embodiment, receiving terminal is to the information data in the line coding piece, carry out FEC decoding with the significant bits in the synchronous head of this line coding piece, this significant bits is the bit (as shown in figure 11) that is used for indicating the type of same line coding piece information data, after finishing FEC decoding, the information of carrying out 64b/66b circuit decoding is information data in the line coding piece after FEC decoding and the significant bits in the synchronous head in this line coding piece, and has neither part nor lot in the less important bit in this synchronous head of this FEC decoding.
The 5th execution mode of the present invention relates to a kind of information coding device, comprises: the line coding module, be used for information data to be verified is carried out line coding, and generate the line coding piece that comprises synchronous head; The check information generation module is used for the information data and the synchronous head of line coding piece are carried out the FEC coding, obtains check information; Insert module, be used for the part check information is inserted the predetermined X bit of verification synchronous head of check information piece; Generation module is used for generating the remaining Y bit of verification synchronous head according to the check information of X bit, and wherein, X and Y are positive integer; Sending module is used to send the check information piece and corresponding to the line coding piece of this check information piece.Owing to utilized being used for synchronous bit in the verification synchronous head in the verification block of information in the present embodiment, thereby, improved coding gain, and then increased the power budget of EPON system not changing frame structure, not increasing under the situation of complexity.
Line coding piece in the present embodiment is the line coding piece of EPON, and the size of verification synchronous head is 2 bits, X=1, and Y=1, this generation module are set to the value that equates with the X bit of 1 bit with the value of the Y bit of 1 bit.Receiving terminal make the verification synchronous head have the characteristic that bit value equates, so that can utilize the inequality of line coding synchronous head and the characteristic that equates of verification synchronous head to carry out the synchronous of line coding block sum check block of information.
In addition, present embodiment can also comprise scrambling module, is used for information data is carried out scrambling.The scrambling result of scrambling module outputs to this line coding module; Perhaps, scrambling module carries out scrambling to the information data of line coding module output, again the scrambling result is outputed to the check information generation module.
Specifically, as shown in figure 12, the data of coming from the upper strata enter 64b/66b line coder (being the line coding module), and line coder adds the corresponding synchronous head according to information type, generates a line coding piece that comprises 2 bit synchronous heads.Then 64 bit information data in the line coding piece are sent to scrambler (being scrambling module) and carry out delivering in buffer memory/sorting unit after the scrambling, simultaneously the synchronous head in the line coding piece also directly is sent to buffer memory/sorting unit.Buffer memory/sorting unit is according to certain regular storage data, when the data of storage reach the desired message length 66 * K of FEC encoder (being the check information generation module), buffer memory/sorting unit sequentially is sent to the FEC encoder to this group information, begins to receive and store new block of information then.The FEC encoder carries out the FEC coding according to selected coding rule to information sets after receiving information sets, generate corresponding check information.Then with check information with 65 bits be unit sequence be sent in check information block cache/sorting unit, simultaneously the 1st bit in the constituent parts is repeated to deliver in check information block cache/sorting unit, so just realized inserting the function of module and generation module, the verification synchronous head that first bit in the feasible check information piece that generates and second bit have constituted this check information piece.Meanwhile, to information data buffer memory/sorting unit, information data buffer memory/sorting unit and check information block cache/sorting unit receives after the full data data are sent to and sends to the physical medium additional sub after sending module is waited for framing the FEC encoder with block transfer.
The 6th execution mode of the present invention relates to a kind of information coding device, present embodiment and the 5th execution mode are roughly the same, its difference is, in the 5th execution mode, the check information generation module is used for the information data of line coding piece and synchronous head are carried out the FEC coding, obtains check information; And in the present embodiment, the check information generation module is used for the information data of line coding piece and the significant bits in the synchronous head are carried out the FEC coding, obtain check information, this significant bits is the bit that is used for indicating the type of same line coding piece information data.
Specifically, as shown in figure 13, entering into the 64b/66b line coder from the data on upper strata encodes, line coder adds corresponding synchronous head (synchronous head can be positioned over the head end or the tail end of information) according to information type, and line coder is sent to corresponding buffer memory/sorting unit to 66 bit informations that comprise synchronous head that carry out line coding then.Specifically, the 64b/66b line coder is sent to scrambler to 64 bit information data and carries out scrambling, then 64 bit information data after the scrambling and the significant bits in the line coding piece synchronous head are delivered in first buffer memory/sorting unit, prepared for carrying out the FEC coding; Less important bit in this line coding piece synchronous head is sent in synchronous head buffer memory/sorting unit.Each buffer memory/sorting unit is according to certain regular storage data.When the data of first buffer memory/sorting unit storage reached the desired message length 65 * K of FEC encoder, first buffer memory/sorting unit was sent to the FEC encoder to this group information order, begins to receive and store new block of information then.The FEC encoder carries out the FEC coding according to selected coding rule to information sets after receiving information sets, generate corresponding check information.Then with check information with 65 bits be unit sequence be sent in check information block cache/sorting unit, also repeat to deliver to the 1st bit in the constituent parts in check information block cache/sorting unit simultaneously, like this, first bit in the check information piece of generation and second bit have constituted the verification synchronous head of this check information piece.Meanwhile, the FEC encoder with block transfer in information data buffer memory/sorting unit, after information data buffer memory/sorting unit and check information block cache/sorting unit receive full data, data are sent to send to the physical medium additional sub after sending module is waited for framing.
Because in the present embodiment; there is a bit not participate in the FEC coding in the line coding piece synchronous head; effectively reduced the amount of information that needs by the FEC coding protection; make more redundant (check bit) protect to the least possible Useful Information data; thereby obtain bigger coding gain, increased the power budget of EPON system.And because the bit that is used for the designation data type has been carried out the FEC coding protection, bigger coding gain can improve the correct probability that the data type is judged.
The 7th execution mode of the present invention relates to a kind of information decoding device, information coding device in correspondence and the 5th or the 6th execution mode, specifically as shown in figure 14, comprise receiver module, be used to receive check information piece and the line coding piece corresponding with this check information piece; Synchronization module is used for the synchronous head according to verification synchronous head and line coding piece, and check information piece and the line coding piece of receiving corresponding with this check information piece carried out synchronously; Acquisition module, the check information piece that is used for after synchronously obtains check information, and wherein part check information predetermined X bit from the verification synchronous head of this check information piece obtains, and X is a positive integer; Decoding module, the check information pair line coding piece corresponding with this check information piece that is used for obtaining according to this acquisition module deciphered.
This decoding module can be deciphered the line coding piece corresponding with the check information piece in the following manner: the synchronous head to the information data in the line coding piece and this line coding piece carries out FEC decoding; Perhaps, the significant bits in the synchronous head of the information data in the line coding piece and this line coding piece is carried out FEC decoding, this significant bits is the bit that is used for indicating the type of same line coding piece information data.
Information decoding device in the present embodiment also can comprise circuit decoding module and descrambling module.This circuit decoding module is used for the information data of the line coding piece of this decoding module output and the synchronous head in this line coding piece are carried out circuit decoding; Perhaps, to the significant bits in the synchronous head of the information data in the line coding piece of decoding module output and this line coding piece, carry out circuit decoding together with other bit in this synchronous head of not importing this decoding module, judge the type of information data during circuit decoding according to the significant bits in this synchronous head.
This descrambling module is used for information data is carried out descrambling.Specifically, this descrambling module carries out descrambling to the information data of circuit decoding module output, and perhaps, this descrambling module carries out descrambling to the information data of decoding module output, again the descrambling result is outputed to the circuit decoding module.
In sum, in embodiments of the present invention, when generating the check information piece, utilize the partial bit in the verification synchronous head of this check information piece to come the bearing part check information, generate remaining bits in this verification synchronous head according to the bit of this bearing part check information again.Thereby do not changing frame structure, do not increasing under the situation of complexity, using, improving coding gain, and then increased the power budget of system being used for synchronous information in the check information piece of the prior art.
With the carrying of 1 bit in the verification synchronous head of 2 bits check information, and with the value of 1 bit in addition in the verification synchronous head, be set to the value that equates with the bit of this carrying check information, receiving terminal make the verification synchronous head have the characteristic that bit equates, so that can utilize the inequality of line coding synchronous head and the characteristic that equates of verification synchronous head to carry out the synchronous of line coding block sum check block of information.
Significant bits in the synchronous head of information data behind the via line coding and line coding piece is carried out the FEC coding obtain check information, this significant bits is the bit that is used for indicating the type of same line coding piece information data.Do not participate in the FEC coding owing to be used for the synchronous partial bit of line coding piece in this synchronous head; effectively reduced the amount of information that needs by the FEC coding protection; make more redundant (check bit) protect to the least possible Useful Information data; thereby obtain bigger coding gain, increased the power budget of EPON system.And because the bit that is used for the designation data type has been carried out the FEC coding protection, bigger coding gain can improve the correct probability that the data type is judged.
Though pass through with reference to some of the preferred embodiment of the invention, the present invention is illustrated and describes, but those of ordinary skill in the art should be understood that and can do various changes to it in the form and details, and without departing from the spirit and scope of the present invention.
Claims (25)
1. an information coding method is characterized in that, comprises following steps:
When generating the check information piece, X bit predetermined in the verification synchronous head of this check information piece is inserted the part check information, generates remaining Y bit in this verification synchronous head according to the check information of this X bit; Wherein, X and Y are positive integer.
2. information coding method according to claim 1 is characterized in that, described X=Y;
The mode that generates remaining Y bit in the described verification synchronous head according to the check information of described X bit is as follows:
The value of described Y bit is set to the value with described X bit correspondent equal.
3. information coding method according to claim 2 is characterized in that,
Described X=1, Y=1.
4. according to each described information coding method in the claim 1 to 3, it is characterized in that, before the step of described generation check information piece, also comprise following steps:
Information data to be verified is carried out line coding, generate the line coding piece that comprises information data and synchronous head.
5. information coding method according to claim 4 is characterized in that, after the step of described generation line coding piece, before the step of described generation check information piece, also comprises following steps:
Information data in the described line coding piece and synchronous head are carried out forward error correction coding, obtain described check information; Perhaps,
Information data in the described line coding piece and the significant bits in the synchronous head are carried out forward error correction coding, obtain described check information; Described significant bits is the bit that is used for indicating the type of same line coding piece information data.
6. information coding method according to claim 5 is characterized in that, before the step of carrying out described line coding, or between the step of the step of described line coding and described forward error correction coding, also comprises following steps:
Described information data is carried out scrambling.
7. information coding method according to claim 4 is characterized in that, after the step of described generation check information piece, also comprises following steps:
Send described check information piece and corresponding to the line coding piece of this check information piece.
8. information coding method according to claim 4 is characterized in that, the described line coding that information data to be verified is carried out is 64b/66b coding or 32b/34b coding.
9. an information decoding method is characterized in that, comprises following steps:
X bit acquisition unit predetermined from the verification synchronous head of check information piece is divided verification information, according to the check information that carries outside the verification synchronous head in this part check information and this check information piece, the line coding piece corresponding with this check information piece deciphered, and wherein X is a positive integer.
10. information decoding method according to claim 9 is characterized in that, before the step that the line coding piece corresponding with described check information piece deciphered, also comprises following steps:
Receive described check information piece and the line coding piece corresponding with this check information piece;
According to the synchronous head of described verification synchronous head and described line coding piece, the described check information piece received and the line coding piece corresponding with this check information piece are carried out synchronously.
11., it is characterized in that the mode that the line coding piece corresponding with described check information piece deciphered is as follows according to claim 9 or 10 described information decoding methods:
Synchronous head to the information data in the described line coding piece and this line coding piece carries out forward error correction decoding; Perhaps,
Significant bits in the synchronous head of the information data in the described line coding piece and this line coding piece is carried out forward error correction decoding; Described significant bits is the bit that is used for indicating the type of same line coding piece information data.
12. information decoding method according to claim 11 is characterized in that, after the step that the line coding piece of described check information piece correspondence is deciphered, also comprises following steps:
Information data in the described line coding piece after described forward error correction decoding and the synchronous head in this line coding piece are carried out circuit decoding; Perhaps,
To the significant bits in the synchronous head of the information data in the described line coding piece after described forward error correction decoding and this line coding piece, carry out circuit decoding together with other bit in this synchronous head that has neither part nor lot in this forward error correction decoding, judge the type of described information data during circuit decoding according to the significant bits in this synchronous head.
13. information decoding method according to claim 12 is characterized in that, after the step of described circuit decoding, perhaps between the step that the step and the described circuit of described forward error correction decoding are deciphered, also comprises following steps:
Described information data is carried out descrambling.
14. an information coding device is characterized in that, comprises:
Insert module, be used for the part check information is inserted the predetermined X bit of verification synchronous head of check information piece;
Generation module is used for generating the remaining Y bit of described verification synchronous head according to the check information of described X bit;
Wherein, X and Y are positive integer.
15. information coding device according to claim 14 is characterized in that, described X=Y;
Described generation module is as follows according to the mode that the check information of described X bit generates remaining Y bit in the described verification synchronous head:
The value of described Y bit is set to the value with described X bit correspondent equal.
16. information coding device according to claim 15 is characterized in that,
Described X=1, Y=1.
17., it is characterized in that this device also comprises according to each described information coding device in the claim 14 to 16:
The line coding module is used for information data to be verified is carried out line coding, generates the line coding piece that comprises information data and synchronous head.
18. information coding device according to claim 17 is characterized in that, this device also comprises:
The check information generation module is used for the information data and the synchronous head of described line coding piece are carried out forward error correction coding, obtains described check information;
Perhaps, described check information generation module is used for the information data of described line coding piece and the significant bits in the synchronous head are carried out forward error correction coding, obtains described check information; Described significant bits is the bit that is used for indicating the type of same line coding piece information data.
19. information coding device according to claim 18 is characterized in that, this device also comprises:
Scrambling module is used for described information data is carried out scrambling;
The scrambling result of described scrambling module outputs to described line coding module; Perhaps,
Described scrambling module carries out scrambling to the information data of described line coding module output, and the scrambling result is outputed to described check information generation module.
20. information coding device according to claim 18 is characterized in that, this device also comprises:
Sending module is used to send described check information piece and corresponding to the line coding piece of this check information piece.
21. an information decoding device is characterized in that, comprises:
Acquisition module is used for obtaining check information from the check information piece, and wherein part check information predetermined X bit from the verification synchronous head of this check information piece obtains, and X is a positive integer;
Decoding module, the check information pair line coding piece corresponding with this check information piece that is used for obtaining according to described acquisition module deciphered.
22. information decoding device according to claim 21 is characterized in that, this device also comprises:
Receiver module is used to receive described check information piece and the line coding piece corresponding with this check information piece;
Synchronization module is used for the synchronous head according to described verification synchronous head and described line coding piece, and described check information piece and the line coding piece of receiving corresponding with this check information piece carried out synchronously;
The check information piece of described acquisition module after synchronously obtains described check information.
23., it is characterized in that the described decoding module pair mode that the line coding piece corresponding with described check information piece deciphered is as follows according to claim 21 or 22 described information decoding devices:
Synchronous head to the information data in the described line coding piece and this line coding piece carries out forward error correction decoding; Perhaps,
Significant bits in the synchronous head of the information data in the described line coding piece and this line coding piece is carried out forward error correction decoding; Described significant bits is the bit that is used for indicating the type of same line coding piece information data.
24. information decoding device according to claim 23 is characterized in that, this device also comprises:
The circuit decoding module is used for the information data and the synchronous head in this line coding piece of the described line coding piece of described decoding module output are carried out circuit decoding; Perhaps,
Described circuit decoding module is used for the significant bits in the synchronous head of the information data of the described line coding piece of described decoding module output and this line coding piece, carry out circuit decoding together with other bit in this synchronous head that has neither part nor lot in described forward error correction decoding, judge the type of described information data during circuit decoding according to the significant bits in this synchronous head.
25. information decoding device according to claim 24 is characterized in that, this device also comprises:
Descrambling module is used for described information data is carried out descrambling;
Described descrambling module carries out descrambling to the information data of described circuit decoding module output, and perhaps, described descrambling module carries out descrambling to the information data of described decoding module output, the descrambling result is outputed to described circuit decoding module again.
Priority Applications (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 200710109329 CN101312385B (en) | 2007-05-23 | 2007-05-23 | Information encoding and decoding method and apparatus |
| PCT/CN2008/071015 WO2008141582A1 (en) | 2007-05-23 | 2008-05-20 | A method and apparatus for information coding/decoding |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 200710109329 CN101312385B (en) | 2007-05-23 | 2007-05-23 | Information encoding and decoding method and apparatus |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN101312385A true CN101312385A (en) | 2008-11-26 |
| CN101312385B CN101312385B (en) | 2013-02-27 |
Family
ID=40031423
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN 200710109329 Expired - Fee Related CN101312385B (en) | 2007-05-23 | 2007-05-23 | Information encoding and decoding method and apparatus |
Country Status (2)
| Country | Link |
|---|---|
| CN (1) | CN101312385B (en) |
| WO (1) | WO2008141582A1 (en) |
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101938326A (en) * | 2009-06-30 | 2011-01-05 | 中兴通讯股份有限公司 | Method and device for decoding control information of long-term evolution system |
| CN102025449A (en) * | 2010-11-19 | 2011-04-20 | 中兴通讯股份有限公司 | Method and device for synchronization of data code blocks |
| WO2011107004A1 (en) * | 2010-03-02 | 2011-09-09 | 中兴通讯股份有限公司 | Processing method and device for downlink frame synchronization used in gigabit-capable passive optical network system |
| WO2014094227A1 (en) * | 2012-12-18 | 2014-06-26 | 华为技术有限公司 | Communication method, system and device for optical network system |
| CN113196661A (en) * | 2021-03-15 | 2021-07-30 | 华为技术有限公司 | Data processing method and related device |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN113381836B (en) * | 2020-02-25 | 2023-03-24 | 华为技术有限公司 | Line coding method and device |
Family Cites Families (11)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO1998006174A1 (en) * | 1996-08-05 | 1998-02-12 | Mitsubishi Denki Kabushiki Kaisha | High-frequency integrated circuit for high-frequency radio transmitter-receiver suppressed in influence of high-frequency power leakage |
| US5983388A (en) * | 1997-08-25 | 1999-11-09 | Analog Devices | Forward error correction arrangement (FEC) for multipoint to single point communication systems |
| US6628725B1 (en) * | 2001-03-28 | 2003-09-30 | Ciena Corporation | Method and system for encoding data for transmission over a serial link |
| JP3922979B2 (en) * | 2002-07-10 | 2007-05-30 | 松下電器産業株式会社 | Transmission path encoding method, decoding method, and apparatus |
| US7570643B2 (en) * | 2003-02-12 | 2009-08-04 | Cisco Technology, Inc. | Efficient framing procedure for variable length packets |
| CA2470546C (en) * | 2003-06-13 | 2010-08-17 | The Directv Group, Inc. | Method and apparatus for providing carrier synchronization in digital broadcast and interactive systems |
| US7284182B2 (en) * | 2003-07-30 | 2007-10-16 | Alcatel | Error correction on M-bit encoded links |
| US7257759B2 (en) * | 2004-08-19 | 2007-08-14 | Alcatel Lucent | Accounting for error carryover in error correction on M-bit encoded links |
| US7440513B2 (en) * | 2005-05-24 | 2008-10-21 | Avago Technologies General Ip (Singapore) Pte. Ltd. | Coding and decoding packetized data |
| CN100359834C (en) * | 2005-07-25 | 2008-01-02 | 深圳市好易通科技有限公司 | Coding and decoding method of wireless digital signalling |
| US7487426B2 (en) * | 2005-10-17 | 2009-02-03 | Enigma Semiconductor, Inc. | 64b/66b coding apparatus and method |
-
2007
- 2007-05-23 CN CN 200710109329 patent/CN101312385B/en not_active Expired - Fee Related
-
2008
- 2008-05-20 WO PCT/CN2008/071015 patent/WO2008141582A1/en active Application Filing
Cited By (13)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101938326B (en) * | 2009-06-30 | 2013-02-27 | 中兴通讯股份有限公司 | Method and device for decoding control information of long-term evolution system |
| CN101938326A (en) * | 2009-06-30 | 2011-01-05 | 中兴通讯股份有限公司 | Method and device for decoding control information of long-term evolution system |
| CN102195738B (en) * | 2010-03-02 | 2015-06-10 | 中兴通讯股份有限公司 | Synchronous processing method and device for downlink frames of GPON (gigabit passive optical network) system |
| CN102195738A (en) * | 2010-03-02 | 2011-09-21 | 中兴通讯股份有限公司 | Synchronous processing method and device for downlink frames of GPON (gigabit passive optical network) system |
| WO2011107004A1 (en) * | 2010-03-02 | 2011-09-09 | 中兴通讯股份有限公司 | Processing method and device for downlink frame synchronization used in gigabit-capable passive optical network system |
| US9232287B2 (en) | 2010-03-02 | 2016-01-05 | Zte Corporation | Method and apparatus for processing downlink frame synchronization in gigabit-capable passive optical network system |
| CN102025449A (en) * | 2010-11-19 | 2011-04-20 | 中兴通讯股份有限公司 | Method and device for synchronization of data code blocks |
| CN102025449B (en) * | 2010-11-19 | 2015-10-21 | 中兴通讯股份有限公司 | A kind of method of synchronization of data code blocks and device |
| WO2014094227A1 (en) * | 2012-12-18 | 2014-06-26 | 华为技术有限公司 | Communication method, system and device for optical network system |
| AU2012397151B2 (en) * | 2012-12-18 | 2015-11-05 | Huawei Technologies Co., Ltd. | Communications method, system, and apparatus for optical network system |
| US9787432B2 (en) | 2012-12-18 | 2017-10-10 | Huawei Technologies Co., Ltd. | Communications method, system, and apparatus for optical network system |
| CN113196661A (en) * | 2021-03-15 | 2021-07-30 | 华为技术有限公司 | Data processing method and related device |
| WO2022193101A1 (en) * | 2021-03-15 | 2022-09-22 | 华为技术有限公司 | Data processing method and related apparatus |
Also Published As
| Publication number | Publication date |
|---|---|
| WO2008141582A1 (en) | 2008-11-27 |
| CN101312385B (en) | 2013-02-27 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN101267210B (en) | Data decoding and coding and receiving/transmission method and device | |
| CN101312349B (en) | Method and apparatus for information block encoding and synchronous detecting | |
| CN101436917B (en) | Method and apparatus for encoding and decoding data | |
| CN100353690C (en) | Multiplex system using common network group to transmit multiple 8B/10B bit stream | |
| TW416188B (en) | Time division multiplexing expansion subsystem | |
| CN101288255B (en) | Communication apparatus, transmitter, receiver, and error correction optical communication system | |
| CN101312385B (en) | Information encoding and decoding method and apparatus | |
| CN101345745B (en) | Data framing method and equipment thereof | |
| CN101729194B (en) | Methods, devices and system for coding and decoding data | |
| CN1968036B (en) | A forward correcting decoding device and control method | |
| US7050468B2 (en) | Multiplexed signal transmitter/receiver, communication system, and multiplexing transmission method | |
| US8560914B2 (en) | Method and device for indicating an uncorrectable data block | |
| CN101795174A (en) | Data transmission method, device and system in 10G EPON (Ethernet-based Passive Optical Network) | |
| CN108183771A (en) | Data processing method, equipment and system in optical network system | |
| CN112690007B (en) | Method and equipment for converting burst signal into continuous signal | |
| US8009993B2 (en) | Hybrid balanced coding scheme | |
| CN101729193A (en) | Coding method and device, decoding method and device and coding and decoding system | |
| CN101572834B (en) | Method, device and passive optical network system for processing passive optical network data | |
| CN110474718B (en) | Data coding method, synchronization method, system and communication system | |
| CN101488820A (en) | Data sending method, data receiving method and related device | |
| JPH0993215A (en) | Stuff synchronizing frame control system | |
| CN113225155A (en) | Frame delimitation method and related device | |
| KR20020041568A (en) | Apparatus and controlling method for high rate data transmitter in mobile communication system |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant | ||
| CF01 | Termination of patent right due to non-payment of annual fee |
Granted publication date: 20130227 Termination date: 20150523 |
|
| EXPY | Termination of patent right or utility model |