CN101308895A - Metal semiconductor field effect light emitting transistor and preparing method thereof - Google Patents
Metal semiconductor field effect light emitting transistor and preparing method thereof Download PDFInfo
- Publication number
- CN101308895A CN101308895A CNA2008100294264A CN200810029426A CN101308895A CN 101308895 A CN101308895 A CN 101308895A CN A2008100294264 A CNA2008100294264 A CN A2008100294264A CN 200810029426 A CN200810029426 A CN 200810029426A CN 101308895 A CN101308895 A CN 101308895A
- Authority
- CN
- China
- Prior art keywords
- layer
- type layer
- highly doped
- type
- doped
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Images
Landscapes
- Junction Field-Effect Transistors (AREA)
- Led Devices (AREA)
Abstract
The invention discloses a metal semiconductor field effect transistor and the fabrication method thereof. The metal semiconductor field effect transistor comprises a substrate, a buffer layer which is arranged on the substrate, a first n type heavily doped layer above the buffer layer, a multi-quantum well layer and a p type layer which are sequentially arranged on the n type layer, a second n type heavily doped layer above the buffer layer, a source electrode which is in Ohmic contact with the second n type heavily doped layer, and a drain electrode which is in Ohmic contact with the p type layer. The first n type heavily doped layer is not connected with the second n type heavily doped layer. The metal semiconductor field effect transistor is characterized in that a slightly doped n type layer is arranged between the buffer layer and first and second n type heavily doped layers, and a SiO2 layer connected with the slightly doped n type layer is embedded between the substrate and the buffer layer. The metal semiconductor field effect transistor further comprises a gate electrode which is in Schottky contact with the SiO2 layer. The metal semiconductor field effect transistor reduces etching damages, thus improving the performance of the components.
Description
Technical field
The present invention relates to lighting transistor, belong to field of semiconductor devices.
Background technology
Wide bandgap semiconductor GaN is the ideal material of preparation photoelectric device (LED, LD etc.) and high temperature high power electronic device (MESFET, HEMT etc.).Because the difficulty of GaN body crystals growth, most GaN materials all is that employing method of heteroepitaxy on sapphire or semi-insulation SiC substrate is made, therefore when making the GaN device, for extraction electrode, make Schottky contacts on n type GaN, etching is absolutely necessary.Therefore the GaN chemical stability is stronger, does not also have a kind of effective wet chemical etching technique liquid at present, adopts dry etching in device manufacturing processes, and using more at present in GaN technology is induction coupled plasma (ICP) etching.But the etching injury that dry etching is introduced brings severe bad influence for the optical characteristics and the electrology characteristic of device, for example, the bombardment of energetic ion causes a large amount of point defects and defect cluster in the etching, the pollution of etch product and mask material, surface roughening, and the introducing of other impurity etc., all can influence Devices Characteristics.The ICP etching can be introduced damage on the GaN surface, causes that schottky barrier height reduces thereby form the electron trap energy level, and ideal factor increases, reverse leakage current increase etc.These damages are not enough worries for n type GaN ohmic contact, because the reduction of n-GaN surface resistivity helps the formation of n type ohmic contact on the contrary after the etching, but for n type GaN Schottky contacts very big influence are arranged.For example the etching injury of introducing in the groove grid manufacturing process can cause the characteristic of GaN FET to descend.
Summary of the invention
The object of the present invention is to provide a kind of metal semiconductor field effect light emitting transistor and preparation method thereof, to reduce the device property decline that etching injury causes.
A kind of metal semiconductor field effect light emitting transistor comprises the resilient coating on substrate and the substrate; The multiple quantum well layer, the p type layer that are included in the first highly doped n type layer on the resilient coating and on the first highly doped n type layer, grow successively; Be included in the second highly doped n type layer on the resilient coating, the first highly doped n type layer does not link to each other with the second highly doped n type layer; Comprise with the source electrode of the second highly doped n type layer ohmic contact, with the drain electrode of p type layer ohmic contact; It is characterized in that also comprising low-doped n type layer between the resilient coating and the first highly doped n type layer, the second highly doped n type layer, in substrate and resilient coating, embedded the SiO that links to each other with low-doped n type layer
2Layer; Also comprise and SiO
2The gate electrode of layer Schottky contacts.
A kind of preparation method of metal semiconductor field effect light emitting transistor is characterized in that may further comprise the steps:
(a) grown buffer layer, low-doped n type layer, highly doped n type layer, multiple quantum well layer, p type layer successively on substrate;
(b) etched substrate and resilient coating form a groove, and groove is to the low doping concentration layer; SiO grows in described groove
2Layer;
(c) in the selected drain region of p type layer, etching p type layer, multiple quantum well layer are etched to highly doped n type layer with the zone outside the drain region;
(d) at the selected source area of the exposed area of highly doped n type layer, the exposed area outside the etching source district is divided into the first highly doped n type layer and the second highly doped n type layer to low-doped n type floor with highly doped n type layer;
(e) at SiO
2Form the gate electrode of Schottky contacts below the layer; Form the source electrode of ohmic contact on the second highly doped n type layer; On p type layer, form the drain electrode of ohmic contact.
The present invention is suitable for GaN, GaAlInP based material, and GaN material glow color is green, blue, and the GaAlInP material is red, orange, yellow.
A kind of method of the grid of preparation lighting transistor is groove of etching on highly doped n type layer, growth one deck low-doped n type layer on groove then, make gate electrode at low-doped n type layer then, will form etching product or other pollutants deposition at low-doped n type layer and highly doped n type layer sidewall like this, thereby cause device performance to reduce.Characteristics of the present invention are the low-doped n type of one deck layers of having grown on the resilient coating in device, make grid at bottom groove, have reduced the etching injury between low-doped n type layer and the highly doped n type layer, thereby device performance is strengthened.
Description of drawings
Fig. 1 is that embodiment 1 cuts open the formula structure chart;
Fig. 2 is a manufacturing process schematic diagram of the present invention;
Fig. 3 is embodiment 1 a manufacturing process schematic diagram;
Fig. 4 is embodiment 1 a manufacturing process schematic diagram;
Fig. 5 is embodiment 1 a manufacturing process schematic diagram;
Fig. 6 is the vertical view of embodiment 1.
Fig. 7 is the upward view of embodiment 1.
Among Fig. 1-7, the 1st, drain electrode, the 2nd, p type layer, the 3rd, multiple quantum well layer, the 4th, highly doped n type layer, 41 is first highly doped n type layers, 42 is second highly doped n type layers, the 5th, low-doped n type layer, the 6th, resilient coating, the 7th, grid, the 8th, source electrode, the 9th, SiO
2Layer, the 10th, substrate.
Embodiment
Below in conjunction with drawings and Examples the present invention is further described.
Prepare metal semiconductor field effect light emitting transistor as follows, base material is selected GaN for use:
(1) as shown in Figure 2, on square Sapphire Substrate 10 growth 2.0um thick at GaN resilient coating 6;
(2) as shown in Figure 2, the thick low-doped n type layer 5 of growth 3.0um on resilient coating 6, GaN doping Si, doping content is 10
17Cm
-3
(3) as shown in Figure 2, the thick highly doped n type layer 4 of continued growth 3um is as electron-emitting area, GaN doping Si, and doping content is 10
19Cm
-3Energy gap is 3.4eV;
(4) as shown in Figure 2, continued growth GaN/InGaN material superlattice structure forms multiple quantum well layer 3, as the active luminous zone of transistorized high brightness, forms 10～20 quantum well, and active area thickness is 150～300nm;
(5) as shown in Figure 2, continued growth p type layer 2, the GaN doped with Mg, doping content is 10
18Cm
-3Thickness is 0.2um, and energy gap is 3.4eV, has formed emitter region, p type hole;
(6) as shown in Figure 3, utilize ICP etching machine to remove part substrate 10 and resilient coating 6, form a groove, groove is until low doping concentration layer 5; Growth one deck SiO in this groove
2Layer 9;
(7) as shown in Figure 4, the selection left area is the drain region, and the zone, the right of using ICP etching machine engraving erosion p type layer 2 and multiple quantum well layer 3 is until highly doped n type layer 4;
(8) as shown in Figure 5, select the zone, the right of highly doped n type layer 4 exposed area to be source area, groove of etching is divided into first highly doped n type the layer 41 and second highly doped n type layer 42 with highly doped n type layer 4 on highly doped n type layer 4;
(9) utilize the SiO of the method for photoetching in the device bottom
2Layer 9 forms grid Schottky contacts electrode pattern, utilizes materials such as method of evaporating evaporation Au/Pt alloy and Ti/Al/Au alloy, forms the gate electrode 7 of schottky junctions; On the second highly doped n type layer 42, form the source electrode 8 of ohmic contact; On p type layer 2, form the drain electrode 1 of ohmic contact, obtain the field effect light emitting transistor of present embodiment, as shown in Figure 1.
Fig. 6 is the vertical view of present embodiment, and Fig. 7 is the upward view of present embodiment.
Prepare metal semiconductor field effect light emitting transistor as follows, base material is selected GaN for use:
(1) as shown in Figure 2, on square Sapphire Substrate 10 growth 2.0um thick at GaN resilient coating 6;
(2) as shown in Figure 2, the thick low-doped n type layer 5 of growth 3.0um on resilient coating 6, GaN doping Si, doping content is 10
17Cm
-3
(3) as shown in Figure 2, the thick highly doped n type layer 4 of continued growth 3um is as electron-emitting area, GaN doping Si, and doping content is 10
19Cm
-3Energy gap is 3.4eV;
(4) as shown in Figure 2, continued growth GaN/InGaN material superlattice structure forms multiple quantum well layer 3, as the active luminous zone of transistorized high brightness, forms 10～20 quantum well, and active area thickness is 150～300nm;
(5) as shown in Figure 2, continued growth p type layer 2, the GaN doped with Mg, doping content is 10
18Cm
-3Thickness is 0.2um, and energy gap is 3.4eV, has formed emitter region, p type hole;
(6) utilize ICP etching machine to dig a circular hole, until low doping concentration layer 5 in the central area of substrate 10 and resilient coating 6; Growth one deck SiO in this circular hole
2Layer;
(7) selecting the central square zone of p type layer 2 is the drain region, and the outer peripheral areas of using ICP etching machine engraving erosion p type layer 2 and multiple quantum well layer 3 is until highly doped n type layer 4;
(8) selecting the periphery of highly doped n type layer 4 exposed area is source area, and square groove of etching is divided into first highly doped n type layer of center and the second highly doped n type layer of peripheral block form with highly doped n type layer 4 on highly doped n type layer 4;
(9) utilize the SiO of the method for photoetching in the device bottom
2Layer forms grid Schottky contacts electrode pattern, utilizes materials such as method of evaporating evaporation Au/Pt alloy and Ti/Al/Au alloy, forms the gate electrode of schottky junctions; On the second highly doped n type layer, form the block form source electrode of ohmic contact; On p type layer, form the drain electrode of ohmic contact, obtain the field effect light emitting transistor of present embodiment.
Claims (9)
1, a kind of metal semiconductor field effect light emitting transistor comprises the resilient coating (6) on substrate (10) and the substrate (10); The multiple quantum well layer (3), the p type layer (2) that are included in the first highly doped n type layer (41) on the resilient coating (6) and on the first highly doped n type layer (4), grow successively; Be included in the second highly doped n type layer (42) on the resilient coating (6), the first highly doped n type layer (41) does not link to each other with the second highly doped n type layer (42); Comprise with the source electrode (8) of second highly doped n type layer (42) ohmic contact, with the drain electrode (1) of p type layer (2) ohmic contact; It is characterized in that also comprising low-doped n type layer (5) between the resilient coating (6) and the first highly doped n type layer (41), the second highly doped n type layer (42), in substrate (10) and resilient coating (6), embedded the SiO that links to each other with low-doped n type layer
2Layer (9); Also comprise and SiO
2The gate electrode (7) of layer (9) Schottky contacts.
2, lighting transistor according to claim 1 is characterized in that: described low-doped n type layer (5) is for square.
3, lighting transistor according to claim 2 is characterized in that: the described first highly doped n type layer (41), with the second highly doped n type layer (42) be square.
4, lighting transistor according to claim 3 is characterized in that: described source electrode (8) is a strip.
5, lighting transistor according to claim 1 is characterized in that: described SiO
2Layer (9) is a strip.
6, lighting transistor according to claim 5 is characterized in that: described gate electrode (7) also is strip.
7, lighting transistor according to claim 1 is characterized in that: described SiO
2Layer (9) is positioned at the center of substrate (10) and resilient coating (6).
8, lighting transistor according to claim 7 is characterized in that: described SiO
2Layer (9) is circular.
9, a kind of preparation method of metal semiconductor field effect light emitting transistor is characterized in that may further comprise the steps:
(a) grown buffer layer (6), low-doped n type layer (5), highly doped n type layer (4), multiple quantum well layer (3), p type layer (2) successively on substrate (10);
(b) etched substrate (10) and resilient coating (6) form a groove, and groove is to low doping concentration layer (5); SiO grows in described groove
2Layer (9);
(c) in the selected drain region of p type layer (2), etching p type layer (2), multiple quantum well layer (3) are etched to highly doped n type layer (4) with the zone outside the drain region;
(d) at the selected source area of the exposed area of highly doped n type layer (4), the exposed area outside the etching source district is divided into the first highly doped n type layer (41) and the second highly doped n type layer (42) to low-doped n type floor (5) with highly doped n type layer (4);
(e) at SiO
2Form the gate electrode (7) of Schottky contacts below the layer (9); The second highly doped n type layer (42) is gone up the source electrode (8) that forms ohmic contact; Go up the drain electrode (1) that forms ohmic contact at p type layer (2).
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN200810029426A CN100590900C (en) | 2008-07-14 | 2008-07-14 | Metal semiconductor field effect light emitting transistor and preparing method thereof |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN200810029426A CN100590900C (en) | 2008-07-14 | 2008-07-14 | Metal semiconductor field effect light emitting transistor and preparing method thereof |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN101308895A true CN101308895A (en) | 2008-11-19 |
| CN100590900C CN100590900C (en) | 2010-02-17 |
Family
ID=40125205
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN200810029426A Expired - Fee Related CN100590900C (en) | 2008-07-14 | 2008-07-14 | Metal semiconductor field effect light emitting transistor and preparing method thereof |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN100590900C (en) |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102064261A (en) * | 2010-11-03 | 2011-05-18 | 中国科学院半导体研究所 | GaN (gallium nitride)-based light-emitting diode (LED) device structure with grid modulated vertical structure and preparation method thereof |
| CN106449640A (en) * | 2016-11-30 | 2017-02-22 | 上海芯石微电子有限公司 | Novel schottky device for full-bridge rectifying and manufacturing method |
| CN111430401A (en) * | 2020-02-25 | 2020-07-17 | 南京邮电大学 | Monolithic optoelectronic integrated circuit and method of forming the same |
-
2008
- 2008-07-14 CN CN200810029426A patent/CN100590900C/en not_active Expired - Fee Related
Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102064261A (en) * | 2010-11-03 | 2011-05-18 | 中国科学院半导体研究所 | GaN (gallium nitride)-based light-emitting diode (LED) device structure with grid modulated vertical structure and preparation method thereof |
| CN102064261B (en) * | 2010-11-03 | 2012-09-05 | 中国科学院半导体研究所 | GaN (gallium nitride)-based light-emitting diode (LED) device structure with grid modulated vertical structure and preparation method thereof |
| CN106449640A (en) * | 2016-11-30 | 2017-02-22 | 上海芯石微电子有限公司 | Novel schottky device for full-bridge rectifying and manufacturing method |
| CN106449640B (en) * | 2016-11-30 | 2023-07-18 | 上海芯石微电子有限公司 | Novel schottky device for full-bridge rectification and manufacturing method |
| CN111430401A (en) * | 2020-02-25 | 2020-07-17 | 南京邮电大学 | Monolithic optoelectronic integrated circuit and method of forming the same |
| CN111430401B (en) * | 2020-02-25 | 2022-09-09 | 南京邮电大学 | Monolithic optoelectronic integrated circuit and method of forming the same |
Also Published As
| Publication number | Publication date |
|---|---|
| CN100590900C (en) | 2010-02-17 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| KR100769727B1 (en) | Forming method for surface unevenness and manufacturing method for gan type led device using thereof | |
| KR20090010284A (en) | Semiconductor light emitting device and fabrication method thereof | |
| CN102024888B (en) | Light-emitting diode and manufacturing method thereof | |
| KR20110049799A (en) | Method for fabricating semiconductor light-emitting device with double-sided passivation | |
| CN204407349U (en) | A kind of gallium nitride based light emitting diode | |
| CN105144415A (en) | Nitride semiconductor light-emitting device and method of manufacturing same | |
| CN112701200B (en) | Monolithic integrated device of HEMT and embedded electrode structure LED and method thereof | |
| CN111326611B (en) | Method for etching table top of III-nitride semiconductor light-emitting device | |
| CN100590900C (en) | Metal semiconductor field effect light emitting transistor and preparing method thereof | |
| KR100897871B1 (en) | Light emitting diode and method of fabrication thereof | |
| US8928006B2 (en) | Substrate structure, method of forming the substrate structure and chip comprising the substrate structure | |
| WO2017101522A1 (en) | Light emitting diode and method for manufacturing same | |
| CN101140968B (en) | Light element device and method for manufacturing same having patterned substrate | |
| CN111599904A (en) | LED epitaxial wafer grown on Si substrate and preparation method thereof | |
| CN110838538B (en) | Light-emitting diode element and preparation method thereof | |
| CN211295112U (en) | Gallium nitride-based Schottky diode | |
| CN214848665U (en) | Monolithic integrated device of HEMT and embedded electrode structure LED | |
| KR100999695B1 (en) | Semiconductor light emitting device and fabrication method thereof | |
| KR100781660B1 (en) | Light emitting device having light emitting band and the method therefor | |
| US8394653B2 (en) | Method for fabricating semiconductor lighting chip | |
| CN202797053U (en) | Gallium nitride light emitting diode structure | |
| CN218215342U (en) | Structure of light emitting device | |
| CN218004894U (en) | Semiconductor light emitting diode chip | |
| CN212848468U (en) | LED epitaxial wafer grown on Si substrate | |
| CN113410346B (en) | Deep ultraviolet LED chip with flip structure and preparation method thereof |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant | ||
| C17 | Cessation of patent right | ||
| CF01 | Termination of patent right due to non-payment of annual fee |
Granted publication date: 20100217 Termination date: 20120714 |