CN101308517B - Method for detecting and calibrating semiconductor device - Google Patents
Method for detecting and calibrating semiconductor device Download PDFInfo
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- CN101308517B CN101308517B CN2007101025434A CN200710102543A CN101308517B CN 101308517 B CN101308517 B CN 101308517B CN 2007101025434 A CN2007101025434 A CN 2007101025434A CN 200710102543 A CN200710102543 A CN 200710102543A CN 101308517 B CN101308517 B CN 101308517B
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Abstract
A method for detecting and correcting a semiconductor is designed. The method includes: applying a first set of hot spot conditions to a global route to produce a detailed route; applying a second set of hot spot conditions to the detailed route to produce a post-detailed route; and applying a third set of hot spot conditions to the post-detailed route to produce the layout. In another aspect, the method includes: providing a circuit design; applying a first hot spot filter to a global routing of the circuit design to produce a detailed route; applying a second hot spot filter to the detailed route to produce a post-detailed route; and performing a rip-up and reroute of the post-detailed route to produce a final layout. The system and method of this invention can ensure and correct the hot spots of semiconductor devises so as to reduce the cost and time of manufacturing semiconductor devices.
Description
Technical field
The present invention relates to a kind of method, particularly a kind of method of focus.
Background technology
The technology of semiconductor manufacturing ceaselessly develops, and makes that shape size (feature size) is more and more little, as 65 nanometers (nanometers), 45 nanometers or littler.When the Design of device size is dwindled, will be than easier generation focus of the device of big shape size or other problem.In ensuing explanation, focus is relevant with the characteristic of device, and the characteristic of device may hinder device, makes it can't be as carrying out as the expection.For example, variation, aluminium slag and other characteristic of bundle (pinching), bridge joint (bridging), plate-like (dishing), erosion (erosion), RC delay, metal wire thickness may produce focus certainly, thereby the usefulness of required device.The design of circuit and (or) control of processing procedure, all may produce focus.Therefore, it is essential having usefulness height and cheap focus detection system and method.Though present device and method can achieve the goal, and can't fully meet all requirements.
Summary of the invention
The present invention is at least the drawback that solves prior art and designs.
A kind of also method of calibrating semiconductor device that detects comprises circuit design is provided; The first focus stripper is provided, and this first focus stripper has the first focus rule; This first focus stripper is applied in the overall routing of this circuit design, to produce detailed routing; The second focus stripper is provided, and this second focus stripper has the second focus rule, and this second focus stripper is handled the required maximum duration of focus and handled the required maximum duration of focus less than this first focus stripper; This second focus stripper is applied in this detailed routing, to produce the back detailed routing; And to this back detailed routing execution rip-up and rewiring, to produce layout.
According to method of the present invention, wherein this back detailed routing is carried out the step of rip-up and rewiring, comprise: the 3rd focus stripper is provided, the 3rd focus stripper has the 3rd focus rule, and the 3rd focus stripper is handled the required maximum duration of focus and handled the required maximum duration of focus less than this second focus stripper; Predict the hotspot location of this back detailed routing; Definition focus form, this focus form surrounds each and defaults to focus; And the 3rd focus stripper is applied in each focus form, in order to produce this layout, the step that wherein the 3rd focus stripper is applied in each focus form comprises carries out rip-up and wiring to the line in each focus form.
According to method of the present invention, wherein the step that the line in each focus form is carried out rip-up and wiring limits any through hole rewiring.
According to method of the present invention, wherein the step that the line in each focus form is carried out rip-up and wiring is fully forbidden any through hole rewiring.
According to method of the present invention, also comprise: the position of the focus of prediction in the detailed routing of back;
Definition one intercepts, and this intercepts the focus around each prediction; And the line by this obstruct carried out rip-up and rewiring.
According to method of the present invention, wherein this first, second and third focus stripper all has a plurality of focus rules.
A kind of also method of calibrating semiconductor device that detects in circuit design, obtains layout, comprises the first focus principle combinations is applied in overall routing, to produce detailed routing; The second focus principle combinations is applied in this detailed routing, to produce the back detailed routing; And the 3rd focus principle combinations is applied in this back detailed routing, to produce this layout.
According to method of the present invention, wherein this second focus principle combinations maximum duration of being applied in this detailed routing is applied in the maximum duration of this overall routing less than this first focus principle combinations, and the 3rd focus principle combinations maximum duration that is applied in this back detailed routing is applied in the maximum duration of this detailed routing less than this second focus principle combinations.
According to method of the present invention, the step that wherein the 3rd focus principle combinations is applied in this back detailed routing comprises: the parameter of the 3rd focus principle combinations and this back detailed routing relatively; And revise this back detailed routing to obtain this layout, wherein this layout is not violated the 3rd focus principle combinations.
According to method of the present invention, the step of wherein revising this back detailed routing comprises rip-up and rewiring.
According to method of the present invention, wherein the 3rd focus principle combinations comprises, definition focus form, this focus form be around any focus that is detected, and rip-up and rewiring are carried out at the focus in the focus form.
In sum, system and method for the present invention can be confirmed the also focus of calibrating semiconductor device, the therefore time that can reduce cost and make semiconductor device.
Description of drawings
Fig. 1 and 2 shows the semi-conductor chip sectional view with plate-like and etching effect.
Fig. 3 and 4 is presented at the synoptic diagram of the bridge effect (bridging effect) on the semi-conductor chip.
Fig. 5 and 6 show on the semi-conductor chips from Shu Xiaoying (pinching effect).
Fig. 7 is the process flow diagram of the inventive method.
Fig. 8 is another possibility process flow diagram of the present invention.
Fig. 9 and 10 is other possibility embodiment of the present invention.
Figure 11 is another possibility embodiment of the present invention, to obtain final layout.
Figure 12 is for carrying out the possible embodiment of step 500 shown in Figure 11.
Figure 13 is another possibility embodiment of the present invention.
Figure 14 and 15 is the synoptic diagram of semi-conductor chip 550.
Figure 16 and 17 is the synoptic diagram of semi-conductor chip 570.
Figure 18 shows in order to carry out the calcspar of method of the present invention
Wherein, description of reference numerals is as follows:
110,120,130,140,150,160: semiconductor device;
112,122: dielectric material;
114,124: metal;
116: the plate-like effect;
126: etching effect;
132,134: metal wire;
136,142: bridge effect:
152,154,156: metal wire;
158,162: from Shu Xiaoying;
200,300,400,498,520: method;
202～212,302～314,402～430,499～516,522～528: step;
550,570: semi-conductor chip;
552,554,558,560,572,574: line;
55: through hole;
564: the focus form;
562,578: focus;
580: intercept;
600: node;
602: microprocessor;
604: input media;
606: storage device;
608: image controller;
610: system storage;
614: display;
616: conveyer.
Embodiment
For above-mentioned and other purposes of the present invention, feature and advantage can be become apparent, cited below particularlyly go out preferred embodiment, and conjunction with figs., be described in detail below.
The following example that a plurality of different embodiment is provided or can carries out different qualities that discloses.The specific example and the arrangement of element below will clearly be described.These ways are embodiment only, and is in no way limited in this.In many occasions, the characteristic of a certain embodiment may combine with the characteristic of another embodiment.In addition, at present openly may in many exemplary examples, be repeated with reference to for several times.These repeat in order simply and clearly to discuss, and are not in specified relationship between the different embodiment or the specified relationship between the different structure.
The technology of semiconductor manufacturing ceaselessly develops, and makes that shape size (feature size) is more and more little, as 65 nanometers (nanometers), 45 nanometers or littler.When the Design of device size is dwindled, will be than easier generation focus of the device of big shape size or other problem.In ensuing explanation, focus is relevant with the characteristic of device, and the characteristic of device may hinder device, makes it can't be as carrying out as the expection.For example, variation, aluminium slag and other characteristic of bundle (pinching), bridge joint (bridging), plate-like (dishing), erosion (erosion), RC delay, metal wire thickness may produce focus certainly, thereby the usefulness of required device.The design of circuit and (or) control of processing procedure, all may produce focus.
When dimensions scale downward and when being transferred to time the micron level, dual-damascene structure (dualdamascene) technology often is used during semiconductor makes.In dual-damascene structure technology, Copper Foil or other conductive material are often used as connecting.Other conductive material comprises, tungsten, titanium, titanium nitride (titanium nitride), but be not to be limited to this.In addition, Si oxide, fluorinated silica glass (fluorinated silica glass; FSG) or dielectric materials, often by inner dielectric (the inter level dielectric of user; Hereinafter to be referred as ILD) layer.Chemically mechanical polishing (chemical mechanical polishing; Hereinafter to be referred as CMP) technology be used in dark etching (etch back) and (planarize) conductive material of planarization integrally and (or) the ILD layer.Yet,,, thereby produce focus so CMP will produce plate-like and etching effect because the rate that removes of metal is different from the rate that removes of dielectric medium.When metal was not positioned on the same surface level (metal is lower) with adjacent dielectric medium, plate-like then often took place.Erosion makes the part of dielectric medium become thinner.Plate-like and erosion are vulnerable to patterning, pattern density and processing procedure to be influenced.
Fig. 1～6 show different focus embodiment.Fig. 1 and 2 shows the semi-conductor chip sectional view with plate-like and etching effect.CMP or other semiconductor fabrication are easy to cause the effect shown in Fig. 1 and 2.In certain embodiments, plate-like and etching effect will form isolation structure, as shallow trench isolation from (shallow trench isolation; STI).In Fig. 1, semiconductor device 110 comprises dielectric material 112 and metal 114.In the technology (as CMP) of planarization, when the rate that removes of metal greater than dielectric medium remove rate the time, then sinking on face profile or error are called plate-like.Because the material removal rate of metal 114 is greater than dielectric material 112, so semiconductor device 110 presents plate-like effect 116.In the present embodiment, metal 114 can have the combination of copper, tungsten, titanium, titanium nitride, tantalum, tantalum nitride, other metal or other metal.Dielectric material 112 can have Si oxide, fluorinated silica glass, dielectric materials or other combination.In integrated semiconductor circuit, dielectric material 112 and metal 114 link to each other, and can make by dual-damascene structure technology.Dual-damascene structure technology has multiprogramming, for example deposition, etching and CMP.
In Fig. 2, semiconductor device 120 has dielectric material 122 and metal 124.In flatening process (as CMP), when the rate that removes of dielectric medium greater than metal remove rate the time, then sinking on face profile or error are called etching effect.Because the rate that removes of dielectric material 122 is greater than the rate that removes of metal 124, so make semiconductor device 120 present etching effect 126.
Fig. 3 and 4 is presented at the synoptic diagram of the bridge effect (bridging effect) on the semi-conductor chip.In Fig. 3, semiconductor device 130 has metal wire 132,134.The bridge effect 136 that semiconductor device 130 is presented is between metal wire 132,134.In Fig. 4, the bridge effect 142 of the row tail that semiconductor device 140 is presented (line end). Bridge effect 136 and 142 may be by many reasons produce, for example change or the copper ashes of topological design, technology controlling and process, unaccommodated line-spacing, plate-like, erosion, metal line-width, but be not to be defined in this.
Fig. 5 and 6 show on the semi-conductor chips from Shu Xiaoying (pinching effect).In Fig. 5, semiconductor device 150 has metal wire 152,154.Metal wire 152,154 is respectively in the both sides of metal wire 156.What semiconductor device 150 was presented occurs in metal wire between metal wire 152 and 154 from Shu Xiaoying 158.In Fig. 6, semiconductor device 160 presents from Shu Xiaoying 162.May be from Shu Xiaoying 158 and 162 by many reasons produced, for example change or the copper ashes of topological design, technology controlling and process, unaccommodated line-spacing, plate-like, erosion, metal line-width, but be not to be defined in this.
Semiconductor device 110,120,130,140,150 and 160 may also have the many circuit and the semiconductor-based end.These circuit may have metal oxide semiconductor field effect and answer combination between transistor (MOSFET), two-carrier transistor, diode, storage unit, resistance, electric capacity, inductance, high voltage transistor, sensor or other said elements.The semiconductor-based end, may have basic semiconductor, composite semiconductor (compound semiconductor) and alloy semiconductor (alloy semiconductor).
Basic semiconductor comprises crystal silicon (crystal silicon), polysilicon (polycrystalline silicon), amorphous silicon (amorphous silicon), reaches germanium (germanium).Composite semiconductor comprises silit (siliconcarbide), gallium arsenide (gallium arsenic).Alloy semiconductor comprises the combination of SiGe (silicon germanium), gallium arsenide phosphide (gallium arsenide phosphide), indium arsenide aluminium (aluminum indium arsenide), Aluminum gallium arsenide (aluminum gallium arsenide), InGaP (gallium indium phosphide) and/or these materials.
The semiconductor-based end, can be (the buried oxide that has buried oxide; BOX) (the semiconductor on insulator of semiconductor at the bottom of the insulation; SOI).In certain embodiments, the composite semiconductor substrate can comprise silicon structure.This silicon structure has multilayer silicon or has the MULTILAYER COMPOSITE semiconductor structure.
In certain embodiments, disclosed technology of the present invention can be applicable in system or the method, in order to confirm the also focus of calibrating semiconductor device.Focus may be by plate-like, erosion, bridge joint, bundle or other reason is produced certainly.Particularly, system and method for the present invention is used in design and dummy run phase, rather than after chip is made.By system and method for the present invention, just can confirm the also focus of calibrating semiconductor device.So time that reduces cost and make semiconductor device.The embodiment of system and method for the present invention is used in designing for manufacturing (design for manufacture; DFM) in the application.In addition, system and method for the present invention can be implemented by router (router) or wiring system (routing system).
Fig. 7 is the process flow diagram of the inventive method, in order to detect the also focus of calibrating semiconductor device.At first, provide input file (step 202).This input file is circuit layout or chip design.In certain embodiments, this input file is accessed by design database.Circuit layout is provided by computing machine.This computer-aided design (CAD) form is as GDS II form.In certain embodiments, circuit layout produces by the simulator (as VCMP or other simulator) of virtual program.In addition, layout can utilize a plurality of simulator to produce, as ecp mode, CMP pattern, etching pattern or the combination of other simulator.The general circuit layout has multiple layer metal.Each metal level has metal and connects.The metal connection is set at dielectric layer.The metal level of circuit layout can be divided into many zones (just grid (gride) or tiling (tiles)).The quantity in zone can be changed according to the technology and the complexity of circuit design.Method described herein can be applicable in individual layer district, multilayer or other the relevant layout of chip design.For example, method described herein in order to detect because of the influence between the metal level or manufacture process (as ECP, CMP, and etching) in the focus that influence produced that caused.
Then, hot spot detector begins to detect the focus (step 204) of this input file.Hot spot detector is a Software tool, abides by the focus rule in order to the circuit layout that judges whether this input file.Hot spot detector with the parameter of the circuit layout of this input file and a plurality of focus rule and (or) specification of focus rule database 206 makes comparisons.Hot spot detector can once whole circuit layouts, or circuit layout is divided into several zones, detect these zones more respectively.For example, wherein a kind of focus rule is exactly the minimum density rule, is applicable to the connection of metal level.Each zone of metal level all has the density of oneself.The zone that line in the zone is shared just can obtain this regional density divided by this regional overall area.Each regional density of minimum density rule request needs greater than minimum density values.Therefore, density and minimum density values that hot spot detector is regional with each are made comparisons, in order to judge whether to meet the minimum density rule.Because all focus rules can't be described, thus below only with the declaratives rule.
The use of hot spot detector comprises software application, and it can be performed by different program languages, according to the focus rule, judges whether focus exists in the special pattern layout.The focus rule can be stored in the database, and is controlled by hot spot detector.In addition, the focus rule also can become the part of the program of hot spot detector own.Form, topological design, shape size or other suitable group according to handling just can arrange the focus rule.In certain embodiments, the focus rule can be defined in advance.In addition, in certain embodiments, the focus rule can be defined and (or) the focus rule that additionally added replaces.
Then, hot spot detector judges whether this input file violates the focus rule (step 208) in a plurality of focus rules.Continue above-mentioned minimum density rule, if each regional density that hot spot detector is judged in this input file meets minimum density rule and other all focus rule, then system provides output file (step 210).Output file is the circuit layout that was corrected.The circuit layout that was corrected may be provided for the computer-aided design (CAD) form, as GDS II form.In certain embodiments, the form of output file is identical with the form of input file, for example is GDS II form.Therefore, output file may be produced by virtual simulator may, for example VCMP or other simulation tool.In addition, output file also can be produced by a plurality of simulators (for example ecp mode, CMP pattern, erosion pattern and other combination).
Output file can be used in the manufacturing of device effectively, and can not violate any focus rule.In certain embodiments, output file meets the rule of test or with other modification or method of testing, to improve design and the layout before the fabrication phase.On the other hand, if hot spot detector learns when the density in a certain zone of input file is violated minimum density values, then revise input file, to avoid violating minimum density values or other focus rule (step 212).In certain embodiments, according to guide parameters or according to the focus rule that it is violated, just can revise input file.Utilize computer system or program and (or) user, just can obtain the modification of suggestion according to guide parameters.When the user directly learns the modification of suggestion, just can utilize computer system or program, manually revise input file.When the modification of suggestion was learnt by computer system or program, then guide parameters can be stored in the database, by computer system or the access of program institute.Similarly, when the user writes down guide parameters, just can directly learn the required modification part of input file.In certain embodiments, system will be according to guide parameters and the proposed amendments layout, but the user just additional modifications to reach optimal topological design as possible.
After revising, system provides second input file (step 202) according to guide parameters.Second input file is circuit layout or chip design.In certain embodiments, second input file is accessed by a design database.The form of circuit layout is a computer-aided design (CAD) form, as GDS II form.In certain embodiments, circuit layout produces by virtual simulator (as VCMP or other simulator).The input file that was modified (second input file) can pass through step 204,208 and 212 again, does not violate any focus rule up to the input file that is provided.Repeated steps will last till that input file do not violate any focus rule.At this moment, output file can be optimal, makes in the stage of manufacturing installation, and device can not violated any focus rule.Yet in certain embodiments, the legal test of output file or the modification and the test that utilize other method to make are to improve layout and the design before the manufacturing installation.
In certain embodiments, above-mentioned disclosed content can directly be applied in system and method, detects and the calibration correction system in order to the calibration focus.For example, all be disclosed in order to the system and method for the focus of identification and calibrating semiconductor device, wherein focus can be because of dishization, erosion, bridge joint, bundle and other are former thereby be formed certainly.Particularly, system and method for the present invention is used in design and dummy run phase, rather than after chip is made.By system and method for the present invention, just can confirm the also focus of calibrating semiconductor device.So time that reduces cost and make semiconductor device.The embodiment of system and method for the present invention is used in designing for manufacturing (design for manufacture; DFM) in the application.Yet, if system or method are not passed through correct calibration, can't provide accurate data, to confirm and the correction focus.Method described herein can be applicable in individual layer district, multilayer or other the relevant layout of chip design.For example, method described herein in order to detect because of the influence between the metal level or manufacture process (as ECP, CMP, and etching) in the focus that influence produced that caused.
Fig. 8 is another possibility process flow diagram of the present invention, in order to calibration system, makes it can detect the also focus of calibrating semiconductor device.At first, provide input file (step 302).This input file is a circuit layout or chip design.In certain embodiments, this input file is accessed by design database.Circuit layout is the computer-aided design (CAD) form, as GDS II form.In certain embodiments, circuit layout produces by the simulator (as VCMP or other simulator tool) of virtual program.The general circuit layout has multiple layer metal.Each metal level has metal and connects.The metal connection is set at dielectric layer.The metal level of circuit layout can be divided into many zones (just grid (gride) or tiling (tiles)).The quantity in zone can be changed according to the technology and the complexity of circuit design.
Then, hot spot detector is sought the focus (step 304) of input file.Hot spot detector is a Software tool, and in order to position and the parameter of judging possible focus, wherein focus comprises physics and electrical focus.For example, physical parameter is the size that the surface changes.The reason that can cause the surface to change comprises the factor of plate-like, erosion or other treating apparatus.The surface that the central area that just example of continuity, hot spot detector may detect device has 15mm changes.The surface changes a just possibility embodiment of physical parameter.The parasitic RC characteristic that electrical parameter is produced when being design.Because all focus rule and parameter can't be described, thus below only with the declaratives rule.In certain embodiments, hot spot detector compares the circuit layout and the focus rule of input file, to judge the position and the parameter of focus.Hot spot detector compares parameter and a plurality of focus rule of the circuit layout of input file, or makes comparisons with the characteristic of focus rule database.Hot spot detector can be once just comparator circuit layout whole, or circuit layout is divided into several zones, detect these zones more respectively, up to relatively intacter all zones.
According to the layout of this input file, finish actual product (step 306).This actual product can be manufactured into test chip, produce the track or the other products of chip, chip.In certain embodiments, this product is producing manufactured finishing on the line.Then, provide this actual product to give the analysis of central issue instrument, whether have focus (step 308) in order to detect this product.Whether the analysis of central issue instrument exists in order to detect focus, as electronic type microscopy, scanning electron microscopy (scanning electron microscopy; SEM), scanning tunnel microscopy (scanning tunneling microscopy; STM), transmission electron microscopy (transmission electron microscopy; TEM), atomic force microscopy (atomic forcemocroscopy; AFM), other method or the combination of these methods.The example that changes with above-mentioned surface is an example, and AFM changes according to the surface of this product, judges whether the existence of focus.In addition, with the data of AFM and SEM or TEM relatively or with the data and SEM and TEM comparison, the accuracy of just provable AFM data of AFM.Similarly, also can learn the electric characteristics of this actual product, as the RC characteristic.
Relatively the focus of the hotspot prediction of this input file and this actual product detects, with the actual treatment of learning hot spot detector self-consistentency (step 310) whether.If the hotspot prediction of this input file and the focus of this actual product detect when identical, finish then that focus detects and correction (step 312).That is to say, if the actual detected result of hot spot detector is a self-consistentency, then system just can detect the also focus of correcting circuit layout.Yet, be inconsistent if the focus of the hotspot prediction of this input file and this actual product detects, need calibrate hot spot detector (step 314,316).Continue the example of above-mentioned surface variation, if the hot spot detector precognition will have the surface of 15mm to change, and the AFM analyser only can analyze the surface variation of 25mm, then needs to calibrate hot spot detector according to the analysis degree of AFM analyser.
Step 314 representative utilizes first method calibration hot spot detector.In step 314, the parameter of hot spot detector and (or) logic can be adjusted, in order to the focus that arrives that can detect on the realistic product.In the method, many hot spot parameters can be analyzed, in order to the calibration hot spot detector.In this regard, calibration circuit layout or other test circuit can be used to calibrate hot spot detector.After calibration, execution in step 312.
Step 316 representative utilizes second method calibration hot spot detector, in step 316, the parameter of hot spot detector and (or) logic can be adjusted, in order to the focus that arrives that can detect on the realistic product.In the method, many hot spot parameters can be analyzed, in order to the calibration hot spot detector.In this regard, calibration circuit layout or other test circuit can be used to calibrate hot spot detector.After calibration, execution in step 304 makes hot spot detector according to the parameter after calibrating, prediction/detection input file.
Then, whether relatively the focus of the hotspot prediction of input file and actual product detects, consistent with actual treatment to judge hot spot detector.In this regard, may make a new product, as once more than than usefulness, or the actual product that is produced when reusing for the first time relatively.If when the hotspot prediction of input file was consistent with the focus detection of actual product, then execution in step 312, finish focus and detect and corrective system.Yet if the focus of the hotspot prediction of input file and actual product detects when inconsistent, execution in step 316 is to calibrate hot spot detector.Above-mentioned steps can repeat to be performed, and is consistent with the focus detection of actual product up to the hotspot prediction of input file.After having calibrated hot spot detector, the focus of prediction just should be identical with the detected focus of actual product, therefore, just can finish focus and detect and corrective system (step 312).
In certain embodiments, disclosed technology of the present invention can be applicable in a kind of system or a kind of method, in order to confirm the also focus of calibrating semiconductor device.Focus may be by plate-like, erosion, bridge joint, bundle or other reason produced certainly.Particularly, system and method for the present invention is used in design and dummy run phase, rather than after chip is made.By system and method for the present invention, just can confirm the also focus of calibrating semiconductor device.So time that reduces cost and make semiconductor device.The embodiment of system and method for the present invention is used in designing for manufacturing (design for manufacture; DFM) in the application.In addition, in certain embodiments, also can detect the also focus of the All Ranges of means for correcting.Semiconductor can be divided into many zones, detect and proofread and correct the focus in the described zone again, just can increase processing speed, and when analyzing whole layout, can reduce the treatment capacity of computing machine, and the power attenuation that reduces storer.By analyzing and when proofreading and correct each regional focus, just all focuses of recoverable layout.Method described herein can be applicable in individual layer district, multilayer or other the relevant layout of chip design.For example, method described herein in order to detect because of the influence between the metal level or manufacture process (as ECP, CMP, and etching) in the focus that influence produced that caused.
Fig. 9 and 10 is other possibility embodiment of the present invention, all in order to detect the focus on the semiconductor device.As shown in Figure 9.At first, provide input file (step 402).This input file is circuit layout or chip design.In certain embodiments, this input file is accessed by design database.Circuit layout is that computing machine is supported format, as GDS II form.In certain embodiments, circuit layout produces by the simulator (as VCMP or other simulator) of virtual program.The general circuit layout has multiple layer metal.Each metal level has metal and connects.The metal connection is set at dielectric layer.The metal level of circuit layout can be divided into many zones (just grid (gride) or tiling (tiles)).The quantity in zone can be changed according to the technology and the complexity of circuit design.Method described herein can be applicable in individual layer district, multilayer or other the relevant layout of chip design.For example, method described herein in order to detect because of the influence between the metal level or manufacture process (as ECP, CMP, and etching) in the focus that influence produced that caused.
Select local zone, to analyze this zone (step 404).Hot spot detector detects the focus (step 406) of this input file.Hot spot detector is a Software tool, and whether the zone that is chosen in order to judgement is according to the focus rule.The parameter in the zone that hot spot detector will be chosen to and a plurality of focus rule and (or) specification of focus rule database 206 makes comparisons.Hot spot detector judges whether input file violates arbitrary focus rule.If when a certain regional area that hot spot detector is judged input file is violated at least one focus rule, then revise this regional area, to avoid violating focus rule (step 408).In certain embodiments, the mode of modification according to guide parameters and (or) the focus rule violated of this regional area.According to method shown in Figure 7 200, computer system or program and (or) user directly revises the modification result obtain according to guide parameters and will replace input file.On the other hand, if when this regional area that hot spot detector is judged input file meets all focus rules, then need not revise this regional area.
After revising this regional area, or this regional area do not violate under the situation of any focus rule, then judges whether to have analyzed All Ranges (step 410).If All Ranges is all analyzed intact, and when all meeting all focus rules, then system provides output file (step 412).Because output file is not violated any focus rule, so in the device process of making, output file is perfect.In certain embodiments, before the stage of making, output file meets the rule of test, or utilizes other method to revise or test, with improve before the fabrication phase design and (or) layout.On the other hand, if do not analyzed all zones as yet, then execution in step 404, and is in order to select other zone, all analyzed intact up to all zones.When analyzing all zones, and when all meeting the focus rule, then system provides output file (step 412).
Figure 10 provides other embodiment of step 404 and 406.As shown in figure 10, step 406 is begun by step 414.Judge selected to regional area whether violate hot spot parameters A.Hot spot parameters is preset in advance, can represent any focus rule, parameter or characteristic.Below will illustrate special rule.In a possibility embodiment, hot spot parameters A is local maximum metal density.Each zone of metal level has the density of itself.With the line area in zone the total area, just can obtain the density in zone itself divided by the zone.Each regional density of maximal density rule request need be equal to or less than maximum density values, as 90%.Therefore, in step 416, the density and the maximum density values in the zone that hot spot detector will be chosen to are made comparisons, and whether the zone that is chosen to judgement meets rule.
If when hot spot parameters A is violated in the zone that is chosen to, then provide the guidance rule (step 418) relevant with hot spot parameters A.For detected focus, instruct rule to offer suggestions and possible solution.Therefore, continue the example of above-mentioned maximal density rule, instruct rule may have following suggestion, the firstth, add oxide slit (oxide slot) in the metallic region of broad; The secondth, wide metal wire is divided into several thin metal wires; The 3rd is that the lametta that will cross over the metal level of wide metal area removes; And (or) the 4th other suitable rule suggestion.Then, according to instruct rule and (or) meet the specification of other hot spot parameters, revise selecteed zone (step 420).After having revised selecteed zone, hot spot detector is tested selecteed zone (step 422) according to hot spot parameters B.On the other hand, if hot spot parameters A is not violated in selecteed zone, then direct execution in step 422.
In step 422, hot spot detector is tested selecteed zone according to hot spot parameters B.Hot spot parameters B can represent any focus rule, parameter or characteristic.Below will illustrate special rule.Below will illustrate special rule.In a possibility embodiment, hot spot parameters B is the minimum line distance between the width metal lines.Minimum line is apart from needing the fixing distance of tool between the rule request width metal lines.If the distance between the metal wire is not enough, then violate minimum line apart from rule.For example, minimum line may require width at metal wire between 1.5～4.5 μ m and the distance between another width metal lines 0.5 μ m need be arranged at least apart from rule, and width is greater than the distance that need have 1.5 μ m between the metal wire of 4.5 μ m and another width metal lines.Therefore, in step 424, hot spot detector with the distance between the metal wire in the selecteed zone and minimum line apart from relatively, with judging whether to meet rule.
When if hot spot parameters B is violated in selecteed zone, then produce and instruct rule (step 426) according to hot spot parameters B.Guide parameters is carried out suggestion at detected focus, to solve hot issue.Therefore, continue the example of above-mentioned minimum line distance, instruct rule may comprise following suggestion, first with the metal wire and the minimum 0.5 μ m that increases to of the distance between another width metal lines of width between 1.5～4.5 μ m; Second with metal wire and distance another width metal lines between minimum the increase to 1.5 μ ms of width greater than 4.5 μ m; The 3rd is that the metal wire that will cross over the metal level of wide metal area removes; The 4th is other rule that is fit to suggestion.According to instruct rule and (or) other characteristic according to hot spot parameters B, revise selecteed zone (step 428).After having revised, hot spot detector can be tested selecteed zone and whether be violated other parameter (step 430).On the other hand,, then need not revise selecteed zone if selecteed zone do not violate hot spot parameters B, and execution in step 430 directly.
The focus that step 430 and hot spot parameters X representative is general detects and according to any other hot spot parameters, in order to revise selecteed zone.In this regard, method 400 can only have single hot spot parameters, or has a plurality of hot spot parameters.Hot spot parameters can according to the characteristic of treatment technology, shape size, layout and (or) program made is identified.Step 432 contains hot spot detector and tests selecteed zone and hot spot parameters X.Hot spot parameters X can change list one or a plurality of focus rule, parameter or characteristic.Below will illustrate special hot spot parameters.In a possibility embodiment, hot spot parameters X is the maximum metal density error between the adjacent areas.Density metal between the maximum metal density error rule request adjacent area is in preset range.If the density metal between two adjacent areas is during greater than default maximum metal density error, then the focus rule is violated in expression.Therefore, in step 434, hot spot detector is made comparisons the density metal that selecteed zone is adjacent between the zone with default maximum metal density, in order to judge whether to meet rule.
When if hot spot parameters X is violated in selecteed zone, then produce and instruct rule (step 436) according to hot spot parameters X.Instruct rule to offer suggestions at the focus that is detected.Therefore, continue the example of above-mentioned maximum metal density error, instruct rule may comprise following suggestion, the firstth, dummy metal (dummy metal) is inserted isolated area; The secondth, width metal lines is divided into several lamettas; The 3rd is to add oxide slit (oxide slot) in the metallic region of broad; The 4th makes the density metal error less than 15%; The 5th is other suitable suggestion.According to instruct rule and (or) characteristic of hot spot parameters X, revise selecteed zone (step 438).After modification is finished, or selecteed zone do not violate hot spot parameters X, then continues the selecteed zone of test and whether violates other hot spot parameters.
When all hot spot parameters had all been tested selecteed zone, and correspondingly revise selecteed zone, judge then whether hot spot detector has analyzed the All Ranges (step 410) of input file.If all analyzed mistake of All Ranges, and meet all focus rules, then system provides output file (step 412).On the other hand, if, also have the zone not analyzed, then execution in step 404, in order to select another not analyzed zone, up to all analyzed mistake of All Ranges.When all analyzed mistake of All Ranges, and meet all focus rules, then execution in step 412, make system that output file is provided.
As shown in the figure,, can finish the step 406 that focus detects by continuous step, wherein continuous step and hot spot parameters A, B ..., X is relevant.Yet in other example, the focus of different hot spot parameters detects step, also can be done simultaneously.In addition, above-mentioned the disclosed embodiments are divided into many regional areas with single partitioning scheme with circuit layout.Yet, in certain embodiments, utilize a plurality of layouts with different boundaries, the collating unit layout, wherein each layout with different boundaries has a plurality of regional areas.At different local segmentation zones, need constantly repeat the step that focus detects and revises.Layout is divided into many different zones, can avoids some focus not to be detected, to reduce fault rate.For example, a high desnity metal zone might generally be divided into half, and obtains two zones.A zone in these two zones has suitably density metal, so meet hot spot parameters.But the hot spot parameters of maximum metal density may be violated in another zone in these two zones.
In certain embodiments, disclosed technology of the present invention can be applicable in system or the method, in order to confirm and any possible focus of calibrating semiconductor device.Focus may be by plate-like, erosion, bridge joint, bundle or other reason produced certainly.Particularly, in certain embodiments, system and method for the present invention is used in design and dummy run phase, rather than after chip is made.By system and method for the present invention, just can confirm the also focus of calibrating semiconductor device.So time that reduces cost and make semiconductor device.The embodiment of system and method for the present invention is used in designing for manufacturing (design formanufacture; DFM) in the application.In addition, system and method for the present invention can be implemented by router or wiring system.
In certain embodiments, semiconductor can be divided into many zones, detect and proofread and correct the focus in these zones again, just can increase processing speed, and when analyzing whole layout, can reduce the treatment capacity of computing machine, and the power attenuation that reduces storer.By analyzing and when proofreading and correct each regional focus, but just all focuses of Compensation Design layout.In certain embodiments, above-mentioned method recoverable is at the focus of same metal level.In certain embodiments, the also focus in two local fields of recoverable on same metal level.Method described herein can be applicable in individual layer district, multilayer or other the relevant layout of chip design.In addition, method described herein is in order to detect because of influence that line caused or the focus that influence produced because of being caused in the manufacture process between the metal level.
Fig. 1 l is another possibility embodiment of the present invention, to obtain final layout.At first, provide circuit design (step 499).Then, by router (router), this circuit design is begun wiring (routing) (step 500).In other embodiments, circuit design is a computer-aided design (CAD) form, for example GDS II form.This circuit design is connected up, just can reduce widely also (or) focus of eliminating in final circuit design layout.At last, for fear of focus, in when wiring, the final circuit design layout that is produced can be considered be corrected and (or) revised.
Figure 12 is for carrying out a possibility embodiment of step 500 shown in Figure 11.Step 500 connects up in order to the circuit design to semiconductor device, to avoid focus.Step 500 comprises wiring processing 502, the focus filtering handles 504.Each step of wiring processing 502 all can be provided for corresponding focus filtering and handle 504 focus stripper.The step 506 of wiring processing 502 is that all or entire chip connect up.Step 506 provides general layout to give this device, and all modifications are all from this device.The first focus stripper 508 of focus filtering processing 504 can be used in step 506.First kind of focus rule of the first focus stripper, 508 definition.Overall routing need meet first kind of focus rule.The special rules of the first focus stripper 508 according to required layout, shape size, treatment technology, required characteristic (as sequential) and (or) other form of device or manufacturing course and being determined.
In a possibility embodiment, the maximum duration of the first focus stripper 508 (pessimistic) is the longest in all focus strippers.For example, the first focus stripper 508 may suppose all lines, through hole, layer (layer) or other form may produce focus, so all lines, through hole, layer or other form all can be arranged.Therefore, when wiring that overall routing is offered suggestions, the first focus stripper 508 will detect the focus that may exist, and is sent to router, to use the route of selecting.The first focus stripper 508 is the overall routing of analysis and suggestion (once only analyzing a line, a through hole, a layer or other form) in order, and side by side considers many lines, through hole, layer or other form).The first focus stripper 508 also has the purpose of this device of optimization.For example, the first focus stripper 508 may be monitored the continuous event-order serie in preset range.When the purpose of this device was not reached, the first focus stripper 508 will send router to, in order to use selectable wiring.In certain embodiments, the first focus stripper, 508 rules own can be modified, in order to the layout rewiring to this device.
Wiring is handled 502 and is continued execution in step 510.Step 510 detailed routing, it can provide original detailed routing to give this device, this device comprise the suggested position of wired, through hole, layer and other form.The second focus stripper 512 of filtering processing 504 is used in the step 510.The second focus stripper, 512 definition, the second focus rule, cloth carefully must meet the second focus rule in detail.In certain embodiments, the maximum duration of the second focus stripper 512 is less than the first focus stripper 508, and can provide analysis of central issue accurately at layout.In certain embodiments, the second focus stripper 512 is considered each bar line, through hole, layer or other arrangement form in order, to detect possible focus.When the focus of the second focus stripper 512 rule was violated, the second focus stripper 512 will send router to, in order to using selectable route, and (or) again to this device rewiring.
Wiring is handled 502 and is continued step 514.Step 514 is the back detailed routing, and it will provide through the amended detailed routing of the second focus stripper and give device.After providing overall routing and detailed routing, if a large amount of focus is detected and when getting rid of, because special layout may cause the part focus still to exist to first and second focus stripper.Therefore, the 3rd focus stripper 516 of filtering processing 504 is used in step 514.The 3rd focus rule that the 3rd focus stripper 516 definition back detailed routings need meet.In certain embodiments, the maximum duration of the 3rd focus stripper 516 is less than first and second focus stripper.In this regard, in certain embodiments, the focus stripper has hot spot detector, in order to detect the focus that may exist.Any layout that may violate the focus rule, the 3rd focus stripper 516 will be to its rewiring.In certain embodiments, utilize rip-up and wiring technique, manually rewiring again.In other embodiments, by wiring system and (or) the focus stripper, rewiring can be performed once more.May according to the focus of the 3rd focus stripper rule and (or) compellent focus design rule, rewiring.After rewiring, the focus of this device layout should all should be got rid of.There is not the layout of focus to be final layout.
Though above-mentioned focus stripper has different focus rules, in other embodiments, also can use focus stripper with identical focus rule.In addition, according to layout, shape size, treatment technology or other factors, special focus stripper can be applied in a certain step of filtering processing.Many focus stripper definition may be stored in the database.In certain embodiments, wiring is handled and that it(?) may not can be provided to the focus stripper.In addition, in other embodiments, wiring handles 502 may have more or less step.
Figure 13 is another possibility embodiment of the present invention, in order to obtain not having the final layout of focus.In certain embodiments, method 520 may be handled equally with the part rewiring, and wherein the 3rd focus stripper 516 of rewiring processing and step 500 li is relevant.Similarly, in certain embodiments, method 520 is handled the same with the part modification of any focus stripper.
In method 520, at first define focus form (step 522).The focus form is a zone, in order to center on possible focus or to center on detected focus.The size of focus form depends on the kind of focus, and in some instances, the focus form has enough sizes, to comprise all lines that influenced by focus, through hole and characteristic.Step 522 definable goes out the focus form.Then, the extra focus rule that adds can be applicable in the focus form (step 524).In certain embodiments, the extra focus rule that adds is compared to previous applied focus rule, and is more compellent.Then, according to the focus rule of extra adding, in the focus form, the line that is affected, through hole and other characteristic are carried out rip-up and rewiring (step 526).
Rip-up and rewiring need to handle at the focus in the focus form, in order to avoid possible focus occurs in the outer zone of focus form.Put, in certain embodiments, the extra focus rule that adds can be prevented from moving, requiring again to revise the through hole that is produced, to avoid hot issue at this point.In other embodiments, the extra focus rule that adds will allow through hole to be moved, but do not influence other layer and (or) through hole that do not need to be done under the situation of rewiring moves.In certain embodiments, the focus rule will be by prediction or the focus that has detected, and the definition rewiring intercepts (routing blockage).The size that wiring intercepts can be fixed or adjust arbitrarily.The size that wiring intercepts can according to the size of focus and (or) position and determining.Any line or characteristic must intercept round being connected up, and rewiring, to get rid of focus.After rip-up and rewiring, should remove has a job has just existed earlier or detected afterwards focus.If when the zones of different of device detects many focuses, then will define a plurality of focus forms, and the line in the focus form, through hole and characteristic will be carried out rip-up and rewiring, to get rid of focus.After all focus forms have finished rip-up and rewiring, then can produce final layout (step 528).
Figure 14 and 15 is the synoptic diagram of semi-conductor chip 550.As shown in the figure, part 550 comprises line 552 and 554.Through hole 556 connecting lines 552 and 556.Part 550 also has line 558, is set at the position vertical with the bearing of trend of line 554.Part 550 also has line 526, is set at the position vertical with the bearing of trend of line 558.In the present embodiment, line 560 parallel lines 554, and arrange in line with line 554.As shown in figure 15, the wiring of line 554,558,560 produces focus 562.Focus 562 is for producing from Shu Xiaoying, but the focus that also can be other factors and produced.Please refer to Figure 14 and 15, focus form 564 is defined by around focus 562.In certain embodiments, according to above-mentioned method 520, the line 554,558,560 in rip-up and the rewiring focus form 564.
Figure 16 and 17 is the synoptic diagram of semi-conductor chip 570.The 17th figure shows according to said method and the part semiconductor chip 570 of rewiring.As shown in figure 16, part semiconductor chip 570 has line 572 and 574.Through hole connecting line 574 and another line (not shown).As shown in the figure, line 572 and 574 wiring will produce focus 578.Focus 578 may represent to appoint the focus of pattern.Focus intercepts 580 and can be defined by around focus 578.In certain embodiments, as shown in figure 17, but, intercept 580 to break away from focus according to just rip-up and rewiring 572 of method 520.
Please refer to Figure 18, the node of its explanation (node) 600 is to carry out the embodiment of said method.Node 600 has microprocessor 602, input media 604, storage device 606, image controller 608, system storage 610, display 614 and conveyer 616.These devices utilize one or more bus-bars 612 and connect.Storage device 606 can be the storage device of disk drive, hard disk, CR-ROM, optical drive or other form.In addition, storage device 606 has ability to receive disk, CR-ROM, DVD-ROM or other computer fetch medium, the wherein executable operations of computer-readable medium may command computing machine.In addition, conveyer 616 can be modem, network interface card or other can be sent to the data of node 616 device of another node.Arbitrary node can be represented a plurality of connections (connection of computer-internal or the Internet) of computer system, and computer system can be personal computer, mainframe computer, PDA and mobile phone.
Computer system generally not only has at least one hardware, in order to the extract operation of execution machine readable, and also has software, in order to carry out to obtain required result.In addition, computer system not only has software and combination of hardware, but also has computer system.
Hardware generally has at least one processor platform and hand held treating apparatus.For example, processor platform can be customer set up (being personal computer or servomechanism).And the hand held treating apparatus can be intelligent mobile phone (smart phone), personal digital assistant (personal digital assistants; PDA) or personal computing device (personal computing devices; PCD).In addition, hardware may have any other physical unit, in order to store readable operation, and for example storer or other data memory device.Other form of hardware comprises hardware system.For example, hardware system comprises conversion equipment, as data card, interface (port), interface card (port card).
Software comprises any machinery sign indicating number that is stored in the medium.For example, medium comprises RAM, ROM with other device (disk, flash memory or CD-ROM).For example, software may have source or object code.Software comprises any operational order performed on customer set up or server.
By the above embodiments, just can increase function and usefulness in conjunction with software and hardware.It is directly software function to be write in the silicon wafer that an example is arranged.Software and hardware can be combined in the computer system, and by above-mentioned disclosing, just can imagine software and combination of hardware after, issuable structure of institute and method.
Computer fetch medium not only comprises passive data storing, as random access memory (randomaccess memory; RAM), but also has semifixed storage, as CD-ROM storer (compactdisk read only memory; CD-ROM).In addition, the above embodiments also can be used among the RAM with computing machine, in order to standard computer is converted to the specific calculations device.
Data structure definable system data, and can be implemented according to this by the above embodiments institute.For example, data structure may provide system data or system's actuating code.Data-signal can be transferred into transfer mechanism, and can store and transmit many data structures, therefore, can be used on transmission the foregoing description.
This system may be designed to operate in any special structure.For example, this system can operate in single computing machine, LAN (Local Area Network), client/server net (client-server network), wide area network (wide area network), the Internet (internet), hand held and other portable and wireless device and network.
Database can be the database of any standard or software (as Oracle, Microsoft Access, SyBase or Dbase is II) itself.These data may have scope, record, data and other database element.By the database special software, other database element is combined togather.Draw and be the process between binding data and another data.For example, the Data Position in characteristic file can be drawn into the file in second form.The physical location of database is also unrestricted, and database can be separated.For example, database may be from servomechanism position far away, and is performed on branch's platform, in addition, can obtain database by the Internet.Also can utilize a plurality of databases.
Though the present invention with preferred embodiment openly as above; right its is not in order to qualification the present invention, any those skilled in the art, without departing from the spirit and scope of the present invention; when can doing a little variation and modification, so protection scope of the present invention is as the criterion when looking the accompanying Claim person of defining.
Claims (11)
1. one kind is detected the also method of calibrating semiconductor device, comprising:
Circuit design is provided;
The first focus stripper is provided, and this first focus stripper has the first focus rule;
This first focus stripper is applied in the overall routing of this circuit design, to produce detailed routing;
The second focus stripper is provided, and this second focus stripper has the second focus rule, and this second focus stripper is handled the required maximum duration of focus and handled the required maximum duration of focus less than this first focus stripper;
This second focus stripper is applied in this detailed routing, to produce the back detailed routing; And
This back detailed routing is carried out rip-up and rewiring, to produce layout.
2. the method for detection as claimed in claim 1 and calibrating semiconductor device wherein to the step of this back detailed routing execution rip-up and rewiring, comprising:
The 3rd focus stripper is provided, and the 3rd focus stripper has the 3rd focus rule, and the 3rd focus stripper is handled the required maximum duration of focus and handled the required maximum duration of focus less than this second focus stripper;
Predict the hotspot location of this back detailed routing;
Definition focus form, this focus form surrounds each and defaults to focus; And
The 3rd focus stripper is applied in each focus form, and in order to produce this layout, the step that wherein the 3rd focus stripper is applied in each focus form comprises carries out rip-up and wiring to the line in each focus form.
3. the method for detection as claimed in claim 2 and calibrating semiconductor device wherein limits any through hole rewiring to the step that the line in each focus form carries out rip-up and wiring.
4. the method for detection as claimed in claim 1 and calibrating semiconductor device is wherein fully forbidden any through hole rewiring the step that the line in each focus form carries out rip-up and wiring.
5. the method for detection as claimed in claim 1 and calibrating semiconductor device also comprises:
The position of the focus of prediction in the detailed routing of back;
Definition one intercepts, and this intercepts the focus around each prediction; And
Line by this obstruct is carried out rip-up and rewiring.
6. as the method for claim 1 a described detection and calibrating semiconductor device, wherein this first, second and third focus stripper all has a plurality of focus rules.
7. one kind is detected the also method of calibrating semiconductor device, in circuit design, obtains layout, comprising:
The first focus principle combinations is applied in overall routing, to produce detailed routing;
The second focus principle combinations is applied in this detailed routing, to produce the back detailed routing; And
The 3rd focus principle combinations is applied in this back detailed routing, to produce this layout.
8. the method for detection as claimed in claim 7 and calibrating semiconductor device, wherein this second focus principle combinations maximum duration of being applied in this detailed routing is applied in the maximum duration of this overall routing less than this first focus principle combinations, and the 3rd focus principle combinations maximum duration that is applied in this back detailed routing is applied in the maximum duration of this detailed routing less than this second focus principle combinations.
9. the method for detection as claimed in claim 8 and calibrating semiconductor device, the step that wherein the 3rd focus principle combinations is applied in this back detailed routing comprises:
The parameter of the 3rd focus principle combinations and this back detailed routing relatively; And
Revise this back detailed routing to obtain this layout, wherein this layout is not violated the 3rd focus principle combinations.
10. the method for detection as claimed in claim 9 and calibrating semiconductor device, the step of wherein revising this back detailed routing comprises rip-up and rewiring.
11. the method for detection as claimed in claim 10 and calibrating semiconductor device, wherein the 3rd focus principle combinations comprises, definition focus form, this focus form be around any focus that is detected, and rip-up and rewiring are carried out at the focus in the focus form.
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| US11/689,197 US7725861B2 (en) | 2006-05-15 | 2007-03-21 | Method, apparatus, and system for LPC hot spot fix |
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| WO2011051791A2 (en) | 2009-10-30 | 2011-05-05 | Synopsys, Inc. | Method and system for lithography hotspot correction of a post-route layout |
| CN102054074B (en) * | 2009-10-30 | 2015-06-24 | 新思科技有限公司 | Method and system for correcting photoetching hot spots in rear winding arrangement |
| CN102054082B (en) * | 2009-10-30 | 2015-06-03 | 新思科技有限公司 | Method and device for correcting photoetching hotspots of rear-winding layout |
| NL2010196A (en) * | 2012-02-09 | 2013-08-13 | Asml Netherlands Bv | Lens heating aware source mask optimization for advanced lithography. |
| US9330221B2 (en) * | 2014-05-23 | 2016-05-03 | Globalfoundries Inc. | Mask-aware routing and resulting device |
| KR102303301B1 (en) * | 2014-12-18 | 2021-09-16 | 삼성전자주식회사 | Method of designing semiconductor device, system for designing semiconductor device |
| US20160217240A1 (en) | 2015-01-28 | 2016-07-28 | Dmo Systems Limited | Methodology Of Incorporating Wafer Physical Measurement With Digital Simulation For Improving Semiconductor Device Fabrication |
| CN110073176B (en) * | 2019-03-15 | 2020-11-27 | 深圳市汇顶科技股份有限公司 | Correction circuit and related signal processing circuit and chip |
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