CN101304528B - Method for mapping video processor video data and memory space - Google Patents
Method for mapping video processor video data and memory space Download PDFInfo
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- CN101304528B CN101304528B CN 200810062246 CN200810062246A CN101304528B CN 101304528 B CN101304528 B CN 101304528B CN 200810062246 CN200810062246 CN 200810062246 CN 200810062246 A CN200810062246 A CN 200810062246A CN 101304528 B CN101304528 B CN 101304528B
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Abstract
The invention belongs to the technical field of digital video encoding and decoding, in particular relates to a mapping method of video data of a video processor and memory space of a memory which includes six steps. According to the mapping relation, the characters of concurrency, etc. of data access in different pages of the memory with a page structure are fully utilized. The luminance component and the chromaticity component of video images are divided, and mapped into the corresponding page address, row address and column address of the memory in the modes of luminance grouping and chromaticity grouping, so that the access bandwidth of the video processor to the video data is improved to a great extent. The memory, replacing and update processes inside the memory of the video images entering the memory are prescribed, thereby guaranteeing the normal operation of the video processor.
Description
Technical field
The invention belongs to the digital video decoding technical field, particularly relate to the mapping method of a kind of video processor video data and memory storage space.
Background technology
A main feature of video processor is that handled the video data volume is big, needs very high data bus bandwidth could satisfy the requirement that real-time video is handled.Current most of coding and decoding video processor adopting hybrid video coding model, the standard that designing institute is followed has MPEG4, H.264, AVS etc., these standards have all adopted the spatial domain prediction coding, the time domain prediction coding, technology such as loop filtering, and the problem of the maximum that these technology are brought for coding and decoding video processor design is the data that the encoding and decoding processor need be visited a large amount of original images and reconstructed image, this not only requires the plug-in mass storage of Video Codec to store original video data and reconstruction video data, and requires memory to provide enough data bandwidths for the data access of Video Codec.
To have a memory space big because of it for memories such as SDRAM, DDR SDRAM, DDR2SDRAM, and low cost and other advantages is widely used in the coding and decoding video processor.The characteristics of these memories are to have paging structure, and their memory space is determined by three allocation indexs, is respectively row address, column address and page address; Work characteristics is the different rows for same paging the inside when conducting interviews, and must be earlier that delegation of last time visit be carried out precharge operation, and then to the current row transmission activation command that will visit.And aforesaid operations can be introduced latent period on data/address bus; And can parallel work-flow to the row in the different pagings, can be covered by the data read process in the current paging the activation command that the row in another paging carries out, same, can be covered by the data read process of another paging for the precharge command that the row in the current paging carries out, rationally utilize this specific character, it is maximum to be that data transfer rate on the data/address bus reaches, and promptly every bat all has the data output of an address location.
Characteristics according to memories such as SDRAM, DDR SDRAM, DDR2SDRAM, can draw: want to improve to greatest extent data transfer rate, adjacent twice visit deposit data address pointed should be positioned at the same delegation of same paging, perhaps is positioned at different pagings.
Video image generally comprises two components: luminance component and chromatic component, chromatic component wherein generally comprise two color difference components.Video processor usually will be with luminance component and chromatic component separate processes to the encoding-decoding process of video image.The process that research coding and decoding video processor data references characteristic and raw video image are gathered, we can find, the data access of video processor is based on the data access of piece basically, in order to improve data transfer rate, need be put in the different memory pagings once visiting involved data block, and the data in each piece preferably leave within the delegation of a paging of memory, and the collection of raw video image and input process are based on capable data input sequence substantially, in order to reduce time delay, reduce storage buffering expense, raw video image can be deposited according to row.
The coding and decoding video processor mainly is meant the processing procedure of video image to the handling process of video sequence, comprise processing procedure to the different frame type, processing procedure during special circumstances such as appearance frame-skipping, and the processes such as storage covering of the video image that enters memory that draws therefrom.Arrangement rationally enters the mapping of the video image and your memory space of memory of memory, could guarantee carrying out smoothly of Video processing flow process.
Because video processor is a continuous process to the processing of video, raw video image constantly enters memory, the video image of being stored in the memory constantly refreshes, this makes the storage of video data in memory space of video processor itself comprise two level content, first level is for selecting memory space when the video image that advances into memory, related particular content comprises opening up how many memory spaces, for each memory space is set one group of initial row address and initial column address, according to what kind of mode is that the video image that enters memory distributes initial row address and initial column address, can be referred to as frame and deposit management; Second level is that this video data is deposited according to certain form in selected memory space, and related particular content is to divide page address, row address and column address for each pixel in the video image distributes.
Through literature search, find that Hansoo Kim and In-Cheol Park are in " High-Performance andLow-Power Memory-Interface Architecture for video Processing Applications ", design a kind of video data at the SDRAM of MPEG-2 Video Decoder and different branch numbers of pages and deposited form, the main thought of utilization is deposited by piece exactly, data placement in same is in the same delegation of same paging, and the data placement of adjacent block is in the different paging of SDRAM.This method can also be used for Video Decoder, but for video encoder, especially adopt the H.264 video encoder of standard, mpeg 4 standard and AVS standard, the search window that estimation relates to often will be striden the more data piece, can better not improve data access speed according to this method, be the video image of the required storage of every frame, the memory space aspect suitable according to the Video processing process selecting do not provide corresponding solution yet.
Summary of the invention
The objective of the invention is to overcome the deficiencies in the prior art, a kind of reasonable in design, needs that can better meet the normal encoding-decoding process of video processor are provided, and support the video data of special processings such as frame-skipping and the mapping method of memory storage space.
The objective of the invention is to adopt such technical solution to realize: to it is characterized in that described mapping method comprises following six steps:
(a) set the pixel number PPU that each address location of memory is deposited; Set Totalspace group initial row address and initial column address; Luminance component, Cb chromatic component and the Cr chromatic component of the video image of required storage are divided according to row and a kind of dividing mode of piece in dividing is divided into corresponding brightness grouping, the grouping of Cb colourity and the grouping of Cr colourity;
(b) in Totalspace group initial row address of setting and initial column address, select one group of initial row address and initial column address initial row address and initial column address as the video image of working as the required storage that advances into memory;
(c) page address and the row address that distributes brightness to divide into groups;
(d) column address of each the luminance pixel point in the distribution brightness grouping;
(e), obtain the page address and the row address of grouping of corresponding C b colourity and the grouping of Cr colourity according to the page address and the row address of brightness grouping;
(f) column address of chroma pixel point in grouping of distribution Cb colourity and the grouping of Cr colourity.
Because the inventive method adopts video image is divided according to luminance component and chromatic component, and the mode of dividing into groups with brightness grouping and colourity is mapped in the corresponding page address of memory, row address and the column address, this mapping relations make full use of the characteristics such as concurrency of the interior data access of the different pagings of memory of band paging structure, make video processor be improved to a great extent the access bandwidth of video data; And the storage of the video image of having stipulated to enter memory in memory, substitute and renewal process, thereby guaranteed the operate as normal of video processor.
Description of drawings
The pixel that Fig. 1 equals 4 o'clock address locations for PPU among the present invention takies the schematic diagram of address bus
The schematic diagram that Fig. 2 divides by row for luminance component among the present invention
Fig. 3 presses the schematic diagram of row division for Cb chromatic component among the present invention and Cr chromatic component
Fig. 4 presses one of schematic diagram of piece division for luminance component among the present invention
Fig. 5 press one of schematic diagram of piece division for Cb chromatic component among the present invention and Cr chromatic component
Fig. 6 is one of the video image of required storage among the present invention and mapping relations schematic diagram of initial row address and initial column address
Fig. 7 is one of mapping relations schematic diagram of the page address row address of brightness grouping among the present invention and memory
Fig. 8 is two of the mapping relations schematic diagram of the page address row address of brightness grouping among the present invention and memory
Fig. 9 divides into groups by the schematic diagram of row expansion for dividing the brightness that obtains by piece among the present invention
Figure 10 is two of the mapping relations schematic diagram of the video image of required storage among the present invention and initial row address and initial column address
Figure 11 is for dividing the schematic diagram that the Cb colourity that obtains is divided into groups or the grouping of Cr colourity launches by row by piece among the present invention
The pixel that Figure 12 equals 2 o'clock address locations for PPU among the present invention takies the schematic diagram of address bus
Figure 13 is three of the mapping relations schematic diagram of the video image of required storage among the present invention and initial row address and initial column address
Figure 14 press for luminance component among the present invention the piece division schematic diagram two
Figure 15 press for Cb chromatic component among the present invention and Cr chromatic component the piece division schematic diagram two
Explanation of nouns related among the present invention is as follows:
Luminance component:
For progressive scanning sequence, the luminance component of video image refers to the luminance array that all luminance pixel points of a two field picture consist of, for interlaced video sequence, the luminance component of video image refers to that all luminance pixel points of two field picture that consist of a two field picture intersect according to interlacing, perhaps a luminance array forming of one on the other mode.
Chromatic component:
For sequence line by line, the chromatic component of video image refers to the chrominance arrays that all chroma pixel points of a two field picture consist of, for the field sequence, the chromatic component of video image refers to that all luminance pixel points of two field picture that consist of a two field picture intersect according to interlacing, and perhaps one on the other mode forms a chrominance arrays. Cb chroma pixel point and Cr chroma pixel point:
Pixel in the chromatic component has the pixel of two kinds of different types, and regulation is a kind of Cb chroma pixel point that cries wherein, the another kind of Cr chroma pixel point that cries.
Cb chromatic component and Cr chromatic component:
In the chromatic component, the array called after Cb chromatic component that is consisted of by all Cb chroma pixel points; The array called after Cr chromatic component that is consisted of by all Cr chroma pixel points.
floor(x)：
Lower bracket function, the functional value of this function are the maximum integer that is not more than x.
ceil(x)：
Last bracket function, the functional value of this function are the smallest positive integrals that is not less than x.
Embodiment:
The mapping method of video processor video data of the present invention and memory storage space is that employing above-mentioned (a) to (f) step realizes, wherein:
The pixel number PPU that address location in described (a) step is deposited is by the decision of memory data bus bit wide, and PPU pixel in each address location takies the data/address bus bit wide of address location in order; Described Totalspace group initial row address is corresponding with the totalframes of the video image of required storage with the initial column address, the corresponding group address space in each group initial row address and initial column address;
Described row is divided and piece is divided into: row is divided: the luminance component of the video image of required storage is divided into the capable brightness of LiH by row divides into groups, the Cb chromatic component of the video image of required storage is divided into the capable Cb colourity grouping of LiH/2 by row, the Cr chromatic component of the video image of required storage is divided into the capable Cr colourity grouping of LiH/2 by row; Piece is divided: with the luminance component of the video image of required storage be divided into McH capable * the brightness grouping of McV row 16 * 16 size, with the Cb chromatic component of the video image of required storage be divided into McH capable * the Cb colourity grouping of McV row 8 * 8 size, with the Cr chromatic component of the video image of required storage be divided into McH capable * the Cr colourity grouping of McV row 8 * 8 size.
The present invention makes full use of the characteristics such as concurrency of data access in the different pagings of the memory of being with paging structure according to mapping relations, the luminance component and the chromatic component of video image are divided, and be mapped in the corresponding page address of memory, row address and the column address in the mode of brightness grouping and colourity grouping, make video processor be improved to a great extent to the access bandwidth of video data; Stipulate to enter storage, the alternative and renewal process of video image in memory of memory, thereby guaranteed the operate as normal of video processor.
Below in conjunction with drawings and Examples, the invention will be further described:
Embodiment 1: encoder 7 frame storage schemes
Used memory is the W986432DH 512K * 4BANKS of Winbond company * 32BITSSDRAM, and the data/address bus bit wide of this memory is 32, and branch number of pages Banknum equals 4; The resolution of video image is 720 * 576, and sample format is 4:2:0; Be that the proportionate relationship that luminance pixel is selected the number of Y and two chromatic image vegetarian refreshments Cb, Cr is: Y: Cb: Cr equals 4: 1: 1, and P frame coding between continuous two P frames, perhaps has two B frames at most with reference to 2 two field pictures at most between P frame and the I frame; Video processor requires original image and reconstructed image that independent memory space will be arranged, and both do not cover in memory mutually; Handled video sequence is a frame sequence.
Data/address bus bit wide by memory can get: PPU equals 4, and the situation that PPU pixel takies address bus as shown in Figure 1.
Between the required reference picture number of P frame compression, continuous two P frames, the perhaps number of the B frame of depositing between P frame and the I frame and video processor depositing requirement and can get original image and reconstructed image: the video image totalframes Totalspace of required storage equals 7, set 7 groups of initial row addresses and initial column address in memory: the 1st group of initial row address and initial column address are respectively 0 and 0, represent with S1 for this reason; The 2nd group of initial row address and initial column address are 160 and 0, represent with S2; The 3rd group of initial row address and initial column address are 320 and 0, represent with S3; The 4th group of initial row address and initial column address are 480 and 0, represent with S4; The 5th group of initial row address and initial column address are 640 and 128, represent with S5; The 6th group of initial row address and initial column address are 1280 and 0, represent with S6; The 7th group of initial row address and initial column address are 1280 and 128, represent with S7.
The luminance component of the original image of required storage is divided into 576 brightness groupings by row, as shown in Figure 2; The Cb chromatic component is divided into 288 Cb colourity groupings by row, and the Cr chromatic component is divided into 288 Cr colourity groupings by row, as shown in Figure 3; The luminance component of the reconstructed image of required storage divides into groups by the brightness that piece is divided into 16 * 16 sizes of 36 row * 45 row, as shown in Figure 4; The Cb chromatic component divides into groups by the Cb colourity that piece is divided into 8 * 8 sizes of 36 row * 45 row, and the Cr chromatic component divides the Cr chromatic component that is divided into 8 * 8 sizes of 36 row * 45 row by piece, as shown in Figure 5.
I, B, P represent the original image of three types of I frames, B frame, P frame, and i, p represent the I frame, and the encoded back of handling of P frame rebuilds the reconstructed image that generates.The Video processing flow process is: original image enters in the memory at a certain time interval successively, begins original image is encoded after three width of cloth raw image storage finish.Original image is encoded according to the structure of IBBPBBPBBP....Just can begin after I frame and P frame are stored and finished its coding, the B frame will wait until that I frame or P frame that its forward direction is adjacent just can begin it is encoded to adjacent I frame or after the P frame is encoded and reconstruction finishes with the back.
The initial row address of the original image of required storage and initial column address are S1, S2, S3, one of these 4 groups of initial row addresses of S4 and initial column address, in the starting stage of Video processing, initial row address that original image distributed and initial column address that preceding 4 width of cloth enter memory are respectively S1, S2, S3 and S4, in video processing procedure, the if there is no situation of frame-skipping, the initial row address of the original image of required storage and initial column address are S1, S2, S3, the original image that compression recently disposes in these 4 groups of initial row addresses of S4 and the initial column address pairing that group initial row address and initial column address, if there is the situation of frame-skipping, that group initial row address and initial column address that the initial row address of the original image of required storage and initial column address are distributed for that width of cloth original image that need skip.The initial row address of the reconstructed image of required storage and initial column address are S5, S6, one of these 3 groups of initial row addresses of S7 and initial column address, in the starting stage of Video processing, the initial row address of the reconstructed image of first required storage and initial column address assignment are S5, the initial row address of the reconstructed image of second required storage and initial column address assignment are S6, the initial row address of the reconstructed image of the 3rd required storage and initial column address assignment are S7, in video processing procedure, the initial row address of the reconstructed image of required storage and initial column address are S5, S6, the reconstructed image of storing at first among the S7 pairing that group initial row address and initial column address.The mapping relations of the video image of required storage and initial row address and initial column address as shown in Figure 6.
For the original image of required storage, the brightness grouping number SPR that the interior row address of each paging of memory can be deposited equals 1, brightness grouping k as shown in Figure 2, and when k equaled 1, the page address of this brightness grouping elected 0 as, and row address is the initial row address; When k equaled 2, the page address of this brightness grouping was 1, and row address is the initial row address, and when k equaled 3, the page address of this brightness grouping was 2, and row address is the initial row address, and when k equaled 4, the page address of this brightness grouping was 3, and row address is the initial row address; When k greater than 4 the time, then the page address of this brightness grouping is the page address that is distributed with 4 pairing those brightness groupings of remainder that remove the k gained, its row address be with 4 except that the merchant of k gained and initial row address with.Its brightness of the original image of required storage be grouped in the memory with the mapping relations of page address and row address as shown in Figure 7.
For the reconstructed image of required storage, brightness grouping Lx_y as shown in Figure 4, for L1_1, the page address of its distribution is 0, its row address is exactly the initial row address; For L1_2, the page address of its distribution is 1, and row address is the initial row address; For L1_3, the page address of its distribution is 2, and row address is the initial row address; For L1_4, the page address of its distribution is 3, and row address is the initial row address; For L1_k, when k greater than 4 the time, then the page address of this brightness grouping is the page address that is distributed with 4 pairing those brightness groupings of remainder that remove the k gained, its row address be with 4 except that the merchant of k gained and initial row address with; For L3_k, its page address is identical with page address and the row address of L1_k with row address, for L2_k, the page address that its page address equals L1_k adds 2 again to the result of 4 deliverys, side-play amount with respect to the page address of L1_k is 2, its row address be the row address that distributes of L1_k and ceil (McV/ (SPR*Banknum)) and, i.e. initial row address+ceil (45/ (1*4))=initial row address+12; For L4_k, its page address is identical with page address and the row address that L2_k is distributed with row address, for Lz_k, when z greater than 4 the time, its page address is with to remove k the page address that luminance component distributed of the pairing row of remainder of z gained with 4 identical, its row address for add with 4 k the row addresses that luminance component distributed that remove the pairing row of remainder of z gained be grouped in memory interior and page address and row address with 4 that remove the merchant of z gained and 12 long-pending gained and, its brightness of the reconstructed image of required storage mapping relations as shown in Figure 8.
Original image for required storage, be positioned at the luminance pixel point of LinepositionL position in its brightness grouping by order from left to right, the column address of the memory cell of being distributed is the initial column address, side-play amount h, floor ((LinepositionL-1)/4) three's sum, because a brightness grouping is only deposited by delegation, so side-play amount h equals 0.Reconstructed image for required storage, pixel in the brightness grouping is launched integral body by row be combined into delegation, as shown in Figure 9, then be positioned at the luminance pixel point of ELinepositionL position according to order from left to right, the column address of being distributed is the initial column address, side-play amount e, floor ((ELinepositionL-1)/PPU) three sum, two brightness groupings are arranged in the row address, Lx_k and L (x+2) _ k, then for Lx_k, the value of e is 0, for L (x+2) _ k, the value of e is 64.
Original image for required storage, Cb colourity grouping p as shown in Figure 3, page address+1 that its page address equals brightness grouping (2*p-1) is again to the result of 4 deliverys, page address side-play amount with respect to brightness grouping (2*p-1) is 1, its row address equals row address+640 of brightness grouping (2*p-1), Cr colourity grouping p, page address+1 that its page address equals brightness grouping (2*p) is again to the result of 4 deliverys, page address side-play amount with respect to brightness grouping (2*p) is 1, and its row address equals row address+640 of brightness grouping (2*p); Reconstructed image for required storage, be positioned at the grouping of Cb colourity and the grouping of Cr colourity of the capable u row of y, their page address is identical with the page address that the brightness grouping that is positioned at the capable u of y row is distributed, and their row address equals row address+320 that the brightness grouping of the capable u row of y is distributed.
Original image for required storage, be positioned at the Cb chroma pixel point or the Cr chroma pixel point of LinepositionC position in grouping of Cb colourity or the grouping of Cr colourity by order from left to right, the column address of the memory cell of being shone upon is initial column address+floor ((LinepositionC-1)/PPU); Reconstructed image for required storage, Cb chroma pixel point in grouping of Cb colourity or the grouping of Cr colourity or Cr chroma pixel are pressed the row expansion, integral body be in line Cb pixel or Cr pixel, as shown in figure 11, then be positioned at the Cb chroma pixel point or the Cr chroma pixel point of ELinepositionC position according to order from left to right, the column address of being distributed is Initcol_C1+floor ((ELinepositionC-1)/4), the colourity grouping that is assigned in the same row address has four: Cbx_y, Cb (x+2) _ y, Crx_y, Cr (x+2) _ y, Initcol_C1 equals the initial column address, for Crx_y, Initcol_C1 equals initial column address+16, for Cb (x+2) _ y, Initcol_C1 equals initial column address+32, and for Cr (x+2) _ y, Initcol_C1 equals initial column address+48.
Embodiment 2: encoder 6 frame storage schemes
Used memory is the W986432DH 512K * 4BANKS of Winbond company * 32BITSSDRAM, and the data/address bus bit wide of this memory is 32, and branch number of pages Banknum equals 4; The resolution of video image is 720 * 576, and sample format is 4:2:0; Be that the proportionate relationship that luminance pixel is selected the number of Y and two chromatic image vegetarian refreshments Cb, Cr is: Y: Cb: Cr equals 4: 1: 1, and P frame coding between continuous two P frames, perhaps has two B frames at most with reference to 2 two field pictures at most between P frame and the I frame; Video processor allows original image and reconstructed image to share memory space, and they can cover in memory space mutually; Handled video sequence is a sequence.
Data/address bus bit wide by memory can get: PPU equals 4, and the situation that PPU pixel takies address bus as shown in Figure 1.
Between the required reference picture number of P frame compression, continuous two P frames, the perhaps number of the B frame of depositing between P frame and the I frame and video processor depositing requirement and can get original image and reconstructed image: the video image totalframes Totalspace of required storage equals 6.Set 6 groups of initial row addresses and initial column address in memory: the 1st group of initial row address and initial column address are respectively 0 and 0, represent with S1 for this reason; The 2nd group of initial row address and initial column address are 108 and 0, represent with S2; The 3rd group of initial row address and initial column address are 216 and 0, represent with S3; The 4th group of initial row address and initial column address are 324 and 0, represent with S4; The 5th group of initial row address and initial column address are 432 and 0, represent with S5; The 6th group of initial row address and initial column address are 540 and 0, represent with S6.
The luminance component of the video image of required storage divides into groups by the brightness that piece is divided into 16 * 16 sizes of 36 row * 45 row, as shown in Figure 4; The Cb chromatic component divides into groups by the Cb colourity that piece is divided into 8 * 8 sizes of 36 row * 45 row, and the Cr chromatic component divides the Cr chromatic component that is divided into 8 * 8 sizes of 36 row * 45 row by piece, as shown in Figure 5.
I, B, P represent the original image of three types of I frames, B frame, P frame, and i, p represent the I frame, and the encoded back of handling of P frame rebuilds the reconstructed image that generates.The Video processing flow process is: original image enters in the memory at a certain time interval successively, begins original image is encoded after three width of cloth raw image storage finish.Original image is encoded according to the structure of IBBPBBPBBP....Just can begin after I frame and P frame are stored and finished its coding, the B frame will wait until that I frame or P frame that its forward direction is adjacent just can begin it is encoded to adjacent I frame or after the P frame is encoded and reconstruction finishes with the back.
The initial row address of the original image of required storage and initial column address, in the starting stage of Video processing, initial row address and initial column address that preceding 6 width of cloth original images are distributed are followed successively by S1, S2, S3, S4, S5 and S6; When not having the situation of frame-skipping, if the encoded B frame that finishes is arranged in the memory, the initial row address of the original image of required storage and initial column address are pairing that group initial row address and initial column address of this B frame, i frame or p frame that reference no longer is provided for current and next code are arranged in the memory else if, then the initial row address of the original image of required storage and initial column address are this i frame or p frame pairing that group initial row address and initial column address, if there is the situation of frame-skipping, the initial row address of the original image of required storage and initial column address are initial row address and the initial column addresses that width of cloth original image that need skip is distributed, the initial row address of the reconstructed image of required storage and initial column address are this reconstructed image un-encoded, original image before the reconstruction process pairing that group initial row address and initial column address, the mapping relations of video image and 6 groups of initial row addresses and initial column address as shown in figure 10.
As shown in Figure 4 brightness grouping Lx_y, for L1_l and L1_2, for the page address of its distribution is 1, the row address of distribution is exactly the initial row address; For L1_3 and L1_4, for the page address of its distribution is 2, the row address of distribution is the initial row address; For L1_5 and L1_6, for the page address of its distribution is 3, the row address of distribution is the initial row address; For L1_7 and L1_8, for the page address of its distribution is 0, the row address of distribution is the initial row address; For L1_k, when k greater than 8 the time, then the page address of this brightness grouping is the page address that is distributed with 8 pairing those brightness groupings of remainder that remove the k gained, its row address be with 8 merchants that remove the k gained and initial row address with, for brightness grouping L3_k, its page address is identical with page address and the row address of brightness grouping L1_k with row address, for L2_k, its page address equals the brightness grouping page address that L1_k distributed and adds 2 again to the result of 4 deliverys, side-play amount with respect to the brightness grouping page address that L1_k distributed is 2, its row address be the brightness grouping row address that L1_k distributed with ceil (45/8) with, i.e. initial row address+6; For L4_k, its page address is identical with page address and the row address that L2_k is distributed with row address, for Lz_k, when z greater than 4 the time, its page address is with to remove k the page address that luminance component distributed of the pairing row of remainder of z gained with 4 identical, its row address for add with 4 k the row addresses that luminance component distributed that remove the pairing row of remainder of z gained with 4 except that the long-pending gained of the merchant of z gained and 6 with.
Pixel in the brightness grouping is launched integral body by row be combined into delegation, as shown in Figure 9.Then be positioned at the luminance pixel point of ELinepositionL position according to order from left to right, the column address of being distributed is the initial column address, side-play amount e, floor ((ELinepositionL-1)/4) three's sum, the brightness grouping that is assigned to a row address has 4: Lx_k, Lx_ (k+1), L (x+2) _ k and L (x+2) _ (k+1), perhaps there are two: Lx_k and L (x+2) _ k, then for Lx_k, the value of e is 0, and for L (x+2) _ k, the value of e is 64, for Lx_ (k+1), the value of e is 128, and for L (x+2) _ (k+1), the value of e is 192.
Be positioned at the grouping of Cb colourity and the grouping of Cr colourity of the capable u row of y, their page address is identical with the page address that the brightness grouping that is positioned at the capable u row of y is distributed, for initial row address and initial column address is the video image of S1, S3, S5, be positioned at the grouping of Cb colourity and the grouping of Cr colourity of the capable u of y row, their row address equals to be positioned at row address+648 that the brightness grouping of the capable u row of y is distributed; For initial row address and initial column address is the video image of S2, S4, S6, is positioned at the grouping of Cb colourity and the grouping of Cr colourity of the capable u of y row, and their page address equals to be positioned at page address+540 that the brightness grouping of the capable u row of y is distributed.
Cb chroma pixel point in grouping of Cb colourity or the grouping of Cr colourity or Cr chroma pixel are pressed the row expansion, integral body be in line Cb pixel or Cr pixel, as shown in figure 11, then be positioned at the Cb chroma pixel point or the Cr chroma pixel point of ELinepositionC position according to order from left to right, the column address of being distributed is Initcol_C1+floor ((ELinepositionC-1)/4), the colourity grouping that is assigned in the same row address has 8: Cbx_y, Cbx_ (y+1), Cb (x+2) _ y, Cb (x+2) _ (y+1), Crx_y, Crx_ (y+1), Cr (x+2) _ y and Cr (x+2) _ (y+1), perhaps there are 4: Cbx_y, Cb (x+2) _ y, Crx_y and Cr (x+2) _ y, when the initial row address and the initial column address of the video image at current chroma component place are S1, when S3 or S5, for Cbx_y, Initcol_C1 equals the initial column address, for Crx_y, Initcol_C1 equals initial column address+16, for Cb (x+2) _ y, Initcol_C1 equals initial column address+32, for Cr (x+2) _ y, Initcol_C1 equals initial column address+48, for Cbx_ (y+1), Initcol_C1 equals initial column address+64, for Crx_ (y+1), Initcol_C1 equals initial column address+80, for Cb (x+2) _ (y+1), Initcol_C1 equals initial column address+96, for Cr (x+2) _ (y+1), Initcol_C1 equals initial column address+112; When the initial row address of the video image at current chroma component place and initial column address are S2, S4 or S6, for Cbx_y, Initcol_C1 equals 128, for Crx_y, Initcol_C1 equals 144, and for Cb (x+2) _ y, Initcol_C1 equals 160, for Cr (x+2) _ y, Initcol_C1 equals 176, and for Cbx_ (y+1), Initcol_C1 equals 192, for Crx_ (y+1), Initcol_C1 equals 208, and for Cb (x+2) _ (y+1), Initcol_C1 equals 224, for Cr (x+2) _ (y+1), Initcol_C1 equals 240.
Embodiment 3: decoder 4 frame storage schemes
Used memory is the DDR SDRAM of the MT46V8M16 of Micron company model, and this memory data bus is 16, and branch number of pages Banknum equals 4; The resolution of the video image of decoder processes is 720 * 576, and sample format is 4:2:0; The P frame decoding is supported B frame decoding function at most with reference to 2 two field pictures.
Data/address bus bit wide by memory can get: PPU equals 2, and the situation that PPU pixel takies address bus as shown in figure 12.
Number according to the required reference frame of decoder P frame decoding can get: the video image totalframes of required storage is 4.Set 4 groups of initial row addresses and initial column address in memory: the 1st group of initial row address and initial column address are respectively 0 and 0, represent with S1 for this reason; The 2nd group of initial row address and initial column address are 0 and 256, represent with S2; The 3rd group of initial row address and initial column address are 640 and 0, represent with S3; The 4th group of initial row address and initial column address are 640 and 256, represent with S4.
The luminance component of the video image of required storage divides into groups by the brightness that piece is divided into 16 * 16 sizes of 36 row * 45 row, as shown in Figure 4; The Cb chromatic component is divided into the Cb colourities grouping of 8 * 8 sizes of 36 row * 45 row by piece, and the Cr chromatic component is divided into the Cr chromatic component of 8 * 8 sizes of 36 row * 45 row by piece, as shown in Figure 5.
The initial row address and the initial column address that begin most the video image of 4 required storages are assigned as S2, S1, S4 and S3 successively, next the initial row address of the video image of required storage and initial column address are not do reference for current and successive image decoding and exported in the memory to show the image that finishes pairing that group initial row address and initial column address, as shown in figure 13.
As shown in Figure 4 brightness grouping Lx_y, for L1_1 and L1_2, for the page address of its distribution is 2, the row address of distribution is exactly the initial row address; For L1_3 and L1_4, for the page address of its distribution is 3, the row address of distribution is the initial row address; For L1_5 and L1_6, for the page address of its distribution is 0, the row address of distribution is the initial row address; For L1_7 and L1_8, for the page address of its distribution is 1, the row address of distribution is the initial row address; For L1_k, when k greater than 8 the time, then the page address of this brightness grouping is the page address that is distributed with 8 pairing those brightness groupings of remainder that remove the k gained, its row address be with 8 merchants that remove the k gained and initial row address with, for brightness grouping L3_k, its page address is identical with page address and the row address of brightness grouping L1_k with row address, for L2_k, its page address equals the brightness grouping page address that L1_k distributed and adds 2 again to the result of 4 deliverys, side-play amount with respect to the page address that L1_k distributed is 2, its row address be the brightness grouping row address that L1_k distributed with ceil (45/8) with, i.e. initial row address+6; For L4_k, its page address is identical with page address and the row address that L2_k is distributed with row address, for Lz_k, when z greater than 4 the time, its page address is with to remove k the page address that luminance component distributed of the pairing row of remainder of z gained with 4 identical, its row address for add with 4 k the row addresses that luminance component distributed that remove the pairing row of remainder of z gained with 4 except that the long-pending gained of the merchant of z gained and 6 with.
Pixel in the brightness grouping is launched integral body by row be combined into delegation, as shown in Figure 9, then be positioned at the luminance pixel point of ELinepositionL position according to order from left to right, the column address of being distributed is the initial column address, side-play amount e, floor ((ELinepositionL-1)/2) three's sum, the brightness grouping that is assigned to a row address has 4: Lx_k, Lx_ (k+1), L (x+2) _ k and L (x+2) _ (k+1) perhaps have two: Lx_k and L (x+2) _ k, then for Lx_k, the value of e is 0, and for L (x+2) _ k, the value of e is 128, for Lx_ (k+1), the value of e is 256, and for L (x+2) _ (k+1), the value of e is 384.
Be positioned at the grouping of Cb colourity and the grouping of Cr colourity of the capable u of y row, their page address equals the page address that the brightness grouping of the capable u row of y is distributed, and row address equals row address+640 that the brightness grouping of the capable u row of y is distributed.
Cb chroma pixel point in grouping of Cb colourity or the grouping of Cr colourity or Cr chroma pixel are pressed the row expansion, integral body be in line Cb pixel or Cr pixel, as shown in figure 11, then be positioned at the Cb chroma pixel point or the Cr chroma pixel point of ELinepositionC position according to order from left to right, the column address of being distributed is Initcol_C1+floor ((ELinepositionC-1)/2), the colourity grouping that is assigned in the same row address has 8: Cbx_y, Cbx_ (y+1), Cb (x+2) _ y, Cb (x+2) _ (y+1), Crx_y, Crx_ (y+1), Cr (x+2) _ y and Cr (x+2) _ (y+1), perhaps there are 4: Cbx_y, Cb (x+2) _ y, Crx_y and Cr (x+2) _ y, for Cbx_y, Initcol_C1 equals the initial column address, for Crx_y, Initcol_C1 equals initial column address+32, for Cb (x+2) _ y, Initcol_C1 equals initial column address+64, for Cr (x+2) _ y, Initcol_C1 equals initial column address+96, for Cbx_ (y+1), Initcol_C1 equals initial column address+128, for Crx_ (y+1), Initcol_C1 equals initial column address+160, for Cb (x+2) _ (y+1), Initcol_C1 equals initial column address+192, for Cr (x+2) _ (y+1), Initcol_C1 equals initial column address+224.
Embodiment 4: high definition encoder 6 frame storage schemes
Used memory is the DDR2SDRAM of the MT47H64M16 of Micron company model, and the data/address bus bit wide of this memory is 16, and branch number of pages Banknum equals 8; The resolution of video image is 1920 * 1088, and sample format is 4:2:0; P frame coding between continuous two P frames, perhaps has two B frames at most with reference to 2 two field pictures at most between P frame and the I frame; Video processor allows original image and reconstructed image to share memory space, and they can cover in memory space mutually; Handled video sequence is a frame sequence.
Data/address bus bit wide by memory can get: PPU equals 2, and the situation that PPU pixel takies address bus as shown in figure 12.
Between the required reference picture number of P frame compression, continuous two P frames, the perhaps number of the B frame of depositing between P frame and the I frame and video processor depositing requirement and can get original image and reconstructed image: the video image totalframes Totalspace of required storage equals 6.Set 6 groups of initial row addresses and initial column address in memory: the 1st group of initial row address and initial column address are respectively 0 and 0, represent with S1 for this reason; The 2nd group of initial row address and initial column address are 144 and 0, represent with S2; The 3rd group of initial row address and initial column address are 288 and 0, represent with S3; The 4th group of initial row address and initial column address are 432 and 0, represent with S4; The 5th group of initial row address and initial column address are 576 and 0, represent with S5; The 6th group of initial row address and initial column address are 720 and 0, represent with S6.
The luminance component of the video image of required storage divides into groups by the brightness that piece is divided into 16 * 16 sizes of 68 row * 120 row, as shown in figure 14; The Cb chromatic component is divided into the Cb colourities grouping of 8 * 8 sizes of 68 row * 120 row by piece, and the Cr chromatic component is divided into the Cr chromatic component of 8 * 8 sizes of 68 row * 120 row by piece, as shown in figure 15.
The initial row address of the original image of required storage and initial column address, in the starting stage of Video processing, initial row address and initial column address that preceding 6 width of cloth original images are distributed are followed successively by S1, S2, S3, S4, S5 and S6; When the situation of no frame-skipping, if the encoded B frame that finishes is arranged in the memory, the initial row address of the original image of required storage and initial column address are pairing that group initial row address and initial column address of this B frame, i frame or p frame that reference no longer is provided for current and next code are arranged in the memory else if, then the initial row address of the original image of required storage and initial column address are this i frame or p frame pairing that group initial row address and initial column address, if there is the situation of frame-skipping, the initial row address of the original image of required storage and initial column address are initial row address and the initial column addresses that width of cloth original image that need skip is distributed, the initial row address of the reconstructed image of required storage and initial column address are this reconstructed image un-encoded, original image before the reconstruction process pairing that group initial row address and initial column address, the mapping relations of video image and 6 groups of initial row addresses and initial column address as shown in figure 10.
As shown in figure 14 brightness grouping Lx_y, for L1_1, L1_2, L1_3 and L1_4, for the page address of its distribution is 0, the row address of distribution is exactly the initial row address; For L1_5, L1_6, L1_7 and L1_8, for the page address of its distribution is 1, the row address of distribution is the initial row address; For L1_9, L1_10, L1_11 and L1_12, for the page address of its distribution is 2, the row address of distribution is the initial row address; For L1_13, L1_14, L1_15 and L1_16, for the page address of its distribution is 3, the row address of distribution is the initial row address; For L1_17, L1_18, L1_19 and L1_20, for the page address of its distribution is 4, the row address of distribution is the initial row address; For L1_21, L1_22, L1_23 and L1_24, for the page address of its distribution is 5, the row address of distribution is the initial row address; For L1_25, L1_26, L1_27 and L1_28, for the page address of its distribution is 6, the row address of distribution is the initial row address; For L1_29, L1_30, L1_31 and L1_32, for the page address of its distribution is 7, the row address of distribution is the initial row address; For L1_k, when k greater than 32 the time, then the page address of this brightness grouping is the page address that is distributed with 32 pairing those brightness groupings of remainder that remove the k gained, its row address be with 32 merchants that remove the k gained and initial row address with, for brightness grouping L5_k, its page address is identical with page address and the row address of brightness grouping L1_k with row address, for L2_k, its page address equals the brightness grouping page address that L1_k distributed and adds 1 again to the result of 4 deliverys, side-play amount with respect to the page address of L1_k is 1, its row address be the brightness grouping row address that L1_k distributed with ceil (120/32) with, i.e. initial row address+4; For L3_k, its page address equals the brightness grouping page address that L2_k distributed and adds 1 again to the result of 4 deliverys, is 1 with respect to the page address side-play amount of L2_k, and its row address is brightness grouping row address+4 that L2_k distributed; For L4_k, its page address equals the brightness grouping page address that L3_k distributed and adds 1 again to the result of 4 deliverys, is 1 with respect to the side-play amount of the page address of L3_k, and its row address is brightness grouping row address+4 that L3_k distributed; For L6_k, its page address is identical with page address and the row address that L2_k is distributed with row address; For L7_k, its page address is identical with page address and the row address that L3_k is distributed with row address; For L8_k, its page address is identical with page address and the row address that L4_k is distributed with row address; For Lz_k, when z greater than 8 the time, its page address is with to remove k the page address that luminance component distributed of the pairing row of remainder of z gained with 8 identical, its row address for add with 8 k the row addresses that luminance component distributed that remove the pairing row of remainder of z gained with 8 except that the long-pending gained of the merchant of z gained and 4 with.
Pixel in the brightness grouping is launched integral body by row be combined into delegation, as shown in Figure 9.Then be positioned at the luminance pixel point of ELinepositionL position according to order from left to right, the column address of being distributed is the initial column address, side-play amount e, floor ((ELinepositionL-1)/2) three's sum, the brightness grouping that is assigned to a row address has 8: Lx_k, Lx_ (k+1), Lx_ (k+2), Lx_ (k+3), L (x+4) _ k, L (x+4) _ (k+1), L (x+4) _ (k+2) and L (x+4) _ (k+3), perhaps there are 4: Lx_k, Lx_ (k+1), Lx_ (k+2) and Lx_ (k+3), then for Lx_k, the value of e is 0, and for Lx_ (k+1), the value of e is 128, for Lx_ (k+2), the value of e is 256, and for Lx_ (k+3), the value of e is 384, for L (x+1) _ k, the value of e is 512, and for L (x+1) _ (k+1), the value of e is 640, for L (x+1) _ (k+2), the value of e is 768, and for L (x+1) _ (k+3), the value of e is 896.
Be positioned at the grouping of Cb colourity and the grouping of Cr colourity of the capable u row of y, their page address is identical with the page address that the brightness grouping that is positioned at the capable u row of y is distributed, for initial row address and initial column address is the video image of S1, S3, S5, be positioned at the grouping of Cb colourity and the grouping of Cr colourity of the capable u of y row, their page address equals to be positioned at page address+864 that the brightness grouping of the capable u row of y is distributed; For initial row address and initial column address is the video image of S2, S4, S6, is positioned at the grouping of Cb colourity and the grouping of Cr colourity of the capable u of y row, and their page address equals to be positioned at page address+720 that the brightness grouping of the capable u row of y is distributed.
Cb chroma pixel point in Cb colourity grouping or the grouping of Cr colourity or Cr chroma pixel are pressed the row expansion, integral body be in line Cb pixel or Cr pixel, as shown in figure 11.Then be positioned at the Cb chroma pixel point or the Cr chroma pixel point of ELinepositionC position according to order from left to right, the column address of being distributed is Initcol_C1+floor ((ELinepositionC-1)/2), the colourity grouping that is assigned in the same row address has 16: Cbx_y, Cbx_ (y+1), Cbx_ (y+2), Cbx_ (y+3), Cb (x+4) _ y, Cb (x+4) _ (y+1), Cb (x+4) _ (y+2), Cb (x+4) _ (y+3), Crx_y, Crx_ (y+1), Crx_ (y+2), Crx_ (y+3), Cr (x+4) _ y, Cr (x+4) _ (y+1), Cr (x+4) _ (y+2) and Cr (x+4) _ (y+3), perhaps there are 8: Cbx_y, Cbx_ (y+1), Cbx_ (y+2), Cbx_ (y+3), Crx_y, Crx_ (y+1), Crx_ (y+2) and Crx_ (y+3), when the initial row address and the initial column address of the video image at current chroma component place are S1, when S3 or S5, for Cbx_y, Initcol_C1 equals the initial column address, for Crx_y, Initcol_C1 equals initial column address+32, for Cbx_ (y+1), Initcol_C1 equals initial column address+64, for Crx_ (y+1), Initcol_C1 equals initial column address+96, for Cbx_ (y+2), Initcol_C1 equals initial column address+128, for Crx_ (y+2), Initcol_C1 equals initial column address+160, for Cbx_ (y+3), Initcol_C1 equals initial column address+192, for Crx_ (y+3), Initcol_C1 equals initial column address+224, for Cb (x+4) _ y, Initcol_C1 equals initial column address+256, for Cr (x+4) _ y, Initcol_C1 equals initial column address+288, for Cb (x+4) _ (y+1), Initcol_C1 equals initial column address+320, for Cr (x+4) _ (y+1), Initcol_C1 equals initial column address+352, for Cb (x+4) _ (y+2), Initcol_C1 equals initial column address+384, for Cr (x+4) _ (y+2), Initcol_C1 equals initial column address+416, for Cb (x+4) _ (y+3), InitcoL_C1 equals initial column address+448, for Cr (x+4) _ (y+3), Initcol_C1 equals initial column address+480; When the initial row address and the initial column address of the video image at current chroma component place are S2, when S4 or S6, for Cbx_y, Initcol_C1 equals 512, for Crx_y, Initcol_C1 equals 544, for Cbx_ (y+1), Initcol_C1 equals 576, for Crx_ (y+1), Initcol_C1 equals 608, and for Cbx_ (y+2), Initcol_C1 equals 640, for Crx_ (y+2), Initcol_C1 equals 672, and for Cbx_ (y+3), Initcol_C1 equals 704, for Crx_ (y+3), Initcol_C1 equals 736, and for Cb (x+4) _ y, Initcol_C1 equals 768, for Cr (x+4) _ y, Initcol_C1 equals 800, and for Cb (x+4) _ (y+1), Initcol_C1 equals 832, for Cr (x+4) _ (y+1), Initcol_C1 equals 864, and for Cb (x+4) _ (y+2), Initcol_C1 equals 896, for Cr (x+4) _ (y+2), Initcol_C1 equals 928, and for Cb (x+4) _ (y+3), Initcol_C1 equals 960, for Cr (x+4) _ (y+3), Initcol_C1 equals 992.
Claims (5)
1. the mapping method of video processor video data and memory storage space is characterized in that, comprises following six steps:
The pixel number PPU that a, each address location of setting memory are deposited; Set Totalspace group initial row address and initial column address; Described Totalspace group initial row address is corresponding with the totalframes of the video image of required storage with the initial column address, the corresponding group address space in each group initial row address and initial column address; Luminance component, Cb chromatic component and the Cr chromatic component of the video image of required storage are divided according to row and a kind of dividing mode of piece in dividing is divided into corresponding brightness grouping, the grouping of Cb colourity and the grouping of Cr colourity;
B, in Totalspace group initial row address of setting and initial column address, select one group of initial row address and initial column address as initial row address and initial column address when the video image of the required storage that advance into memory;
C, the page address and the row address that distribute brightness to divide into groups;
D, the column address of distributing each the luminance pixel point in the brightness grouping;
E, according to the page address and the row address of brightness grouping, obtain page address and row address that grouping of corresponding C b colourity and Cr colourity are divided into groups;
F, the column address of distributing chroma pixel point in grouping of Cb colourity and the grouping of Cr colourity.
2. the mapping method of video processor video data as claimed in claim 1 and memory storage space, it is characterized in that the pixel number PPU that described address location is deposited is determined that by the memory data bus bit wide PPU pixel in each address location takies the data/address bus bit wide of address location in order; Described Totalspace group initial row address is corresponding with the totalframes of the video image of required storage with the initial column address, the corresponding group address space in each group initial row address and initial column address.
3. the mapping method of video processor video data as claimed in claim 1 and memory storage space is characterized in that described row is divided and piece is divided into:
Row is divided: the luminance component of the video image of required storage is divided into the capable brightness grouping of LiH by row, the Cb chromatic component of the video image of required storage is divided into the capable Cb colourity grouping of LiH/2 by row, the Cr chromatic component of the video image of required storage is divided into the capable Cr colourity grouping of LiH/2 by row;
Piece is divided: with the luminance component of the video image of required storage be divided into McH capable * the brightness grouping of McV row 16 * 16 size, with the Cb chromatic component of the video image of required storage be divided into McH capable * the Cb colourity grouping of McV row 8 * 8 size, with the Cr chromatic component of the video image of required storage be divided into McH capable * the Cr colourity grouping of McV row 8 * 8 size.
4. the mapping method of video processor video data as claimed in claim 1 and memory storage space is characterized in that the column address of each luminance pixel point in the described distribution brightness grouping, and its method is:
When luminance component is divided according to the dividing mode of row division, then be positioned at the luminance pixel point of LinepositionL position in the brightness grouping by order from left to right, the column address of the memory cell of being distributed is the initial column address, side-play amount h, floor ((LinepositionL-1)/PPU) three sum, h is the integer more than or equal to 0, is assigned to the different brightness groupings in the same row address, has different side-play amount h;
When luminance component is divided according to the dividing mode of piece division, luminance pixel in the brightness grouping is pressed row to launch, the integral body pixel that is in line, then be positioned at the luminance pixel point of ELinepositionL position according to order from left to right, the column address of being distributed is the initial column address, side-play amount e, floor ((ELinepositionL-1)/PPU) three sum, e is the integer more than or equal to 0, is assigned to brightness groupings different in the same row address, has different side-play amount e.
5. the mapping method of video processor video data as claimed in claim 1 and memory storage space, it is characterized in that described page address and row address according to the brightness grouping, obtain the page address and the row address of grouping of corresponding C b colourity and the grouping of Cr colourity, its method is:
When the dividing mode of dividing according to row when Cb chromatic component and Cr chromatic component is divided, the side-play amount that alph is arranged between the page address that from top to bottom page address and from top to bottom 2*p-1 the brightness in luminance component of p Cb colourity grouping divides into groups to be distributed in the Cb chromatic component, the side-play amount that beta is arranged between the row address that from top to bottom row address and from top to bottom 2*p-1 the brightness in luminance component of p Cb colourity grouping divides into groups to be distributed in the Cb chromatic component, the side-play amount that alph is arranged between the page address that from top to bottom page address and from top to bottom 2*p the brightness in luminance component of p Cr colourity grouping divides into groups to be distributed in the Cr chromatic component, the side-play amount that beta is arranged between the row address that from top to bottom row address and from top to bottom 2*p the brightness in luminance component of p Cr colourity grouping divides into groups to be distributed in the Cr chromatic component, or: the side-play amount that alph is arranged between the page address that from top to bottom page address and from top to bottom 2*p-1 the brightness in luminance component of p Cr colourity grouping divides into groups to be distributed in the Cr chromatic component, the side-play amount that beta is arranged between the row address that from top to bottom row address and from top to bottom 2*p-1 the brightness in luminance component of p Cr colourity grouping divides into groups to be distributed in the Cr chromatic component, the side-play amount that alph is arranged between the page address that from top to bottom page address and from top to bottom 2*p the brightness grouping in luminance component of p Cb colourity grouping distributed in the Cb chromatic component has the side-play amount of beta between row address that from top to bottom p Cb colourity is divided into groups in the Cb chromatic component and from top to bottom 2*p brightness divides into groups to be distributed in luminance component the row address;
When the dividing mode of dividing according to piece when Cb chromatic component and Cr chromatic component is divided, be positioned at the grouping of Cb colourity and the grouping of Cr colourity of the capable u row of y, their page address is identical with the page address that the brightness grouping that is positioned at the capable u row of y is distributed, and the row address that their row address divides into groups to be distributed with respect to the brightness of the capable u row of y has the side-play amount of gama.
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