CN101304314B - Methods of encrypting and decrypting data and bus system using the methods - Google Patents

Abstract

A method for encrypting and decrypting data and a bus system using the method are provided. The method of encrypting data includes: performing an operation on data to be transmitted through the bus with a key stream generated from a predetermined key to encrypt the data; transmitting the encrypted data to a predetermined module through the bus; When the encrypted data is sent on the bus, the synchronous signal which is logic high is sent to the predetermined module. Therefore, the speed of encryption is increased and encryption can be easily realized, so that the security of data received from the bus can be improved.

Description

Method for encrypting and decrypting data and bus system using the method

This application claims priority from Korean Patent Application No. 10-2007-0044699 filed with the Korean Intellectual Property Office on May 8, 2007, the disclosure of which is hereby incorporated by reference in its entirety.

Technical field

The method and bus system according to the invention involve encryption and decryption of data.

Background technique

According to the method of operating the key, the encryption system can be divided into public key encryption system and private key encryption system. In a public key encryption system, all users have a publicly available public key and their own private or secret key. The public key is used to encrypt the file and the private key is used to decrypt the encrypted file when the individual stores the file. On the other hand, in a private key encryption system, encryption and decryption (decoding) are performed simultaneously. Private key encryption systems can be divided into block cipher systems and stream cipher systems.

A block cipher system divides a given plaintext into blocks with a fixed length (64 bits or 128 bits), and performs encryption in units of blocks. A stream cipher system performs an exclusive OR (XOR) operation on the keystream resulting from a secret key and the plaintext to produce the encrypted text, rather than breaking the plaintext into blocks. In general, stream ciphers are faster than block ciphers.

FIG. 1 is a block diagram of a prior art stream cipher system.

Referring to FIG. 1 , the stream cipher system includes a central processing unit (CPU) 11 , a cache 12 , a memory controller 13 , an encryption/decryption unit 14 , an operation unit 15 and an external memory 16 .

First, the operation of encrypting data sent from the CPU 11 to the bus will be described. When a request for reading/writing data is made from the CPU 11, since the generated data is unencrypted plain text data, it is necessary to encrypt the data to send the data through the bus. When the CPU 11 requests to read/write data, the encryption/decryption unit 14 detects the request. Here, the key stream generation unit 141 included in the encryption/decryption unit 14 is synchronized with a clock signal (ie, from a rising edge and/or a falling edge of the clock signal), and generates a key stream corresponding to the size of data. Here, for example, the size of the data may be represented as word count, wherein the number of lines, words, letters is counted from bytes or input data. In the operation unit 15, an XOR operation is performed on the key stream and data that are synchronized with each other, so as to be mapped one-to-one in units of bytes to encrypt the data. Therefore, encrypted data can be sent to the outside through the bus.

Next, decrypting data that has been encrypted and sent over the bus in order to make the CPU

11 Identify operations on the data. The encrypted data sent from the external memory 16 via the bus is sent to the CPU 11 through the memory controller 13 and the cache memory 12. However, the CPU 11 cannot recognize encrypted data, and thus requires decryption processing. When encrypted data is transmitted from the external memory 16 through the bus, the encryption/decryption unit 14 detects the transmission. Here, the key stream generation unit 141 included in the encryption/decryption unit 14 synchronizes with a clock signal, and generates a key stream. In the operation unit 15, an XOR operation is performed on the key stream synchronized with each other and the encrypted data, respectively, so as to be one-to-one mapped in units of bytes to decrypt the encrypted data. The decrypted data is input to the CPU 11.

Here, the area including the CPU 11, the cache memory 12, the memory controller 13, the encryption/decryption unit 14, and the operation unit 15 can be referred to as a trusted area, and all modules except the trusted area, that is, the external memory 16, can be Called an untrusted zone. Data sent through the bus in the untrusted area may be exposed to the outside through tapping. Here, the opening means that data sent through the bus is exposed to the outside through other lines. Data is protected because the inside of the system on chip (SoC) or single chip is called a trusted region. However, when different modules are attached to one board, it is difficult to protect data transmitted between different modules since data transmitted through a bus on the board may be exposed through an opening.

Contents of invention

The present invention provides a method of encrypting data by which data can be securely sent to each of a plurality of different modules connected by a bus.

The invention also provides a method of decrypting data by which data can be securely sent to each of a plurality of different modules connected by a bus.

The present invention also provides a bus system by which data can be securely transmitted to each of a plurality of different modules connected by the bus, and performance degradation when transmitting encrypted or decrypted data is reduced.

According to one aspect of the present invention, there is provided a method of encrypting data, comprising: (a) performing an operation on data to be sent through a bus with a key stream generated from a predetermined key to encrypt the data; (b) ) sending encrypted data to a predetermined module through the bus; (c) sending a synchronization signal to a predetermined module when sending the encrypted data through the bus.

The method for encrypting data may further include: performing an exclusive OR (XOR) operation on the data and the key stream to encrypt the data.

The method of encrypting data may further include generating a key stream based on a seed including a predetermined key and additional information, wherein the seed is commonly applied during decryption of the encrypted data in the module receiving the encrypted data.

The method of encrypting data may further include: generating a key stream to be synchronized with a clock signal of the bus.

The method of encrypting data may further include: synchronizing the synchronization signal with a clock signal of the bus.

The method of encrypting data may further include: broadcasting a synchronization signal to at least two predetermined modules.

The method of encrypting data may further include: transmitting a synchronization signal through each of the plurality of dedicated lines of the at least two predetermined modules.

The method of encrypting data may further include sending a synchronization signal to the bus through the control of the controller of the bus.

The method of encrypting data may further include: transmitting a synchronization signal to at least one of the plurality of groups, wherein the plurality of groups includes at least two predetermined modules.

According to another aspect of the present invention, there is provided a computer-readable recording medium having recorded thereon a computer program for performing a method of encrypting data, the method comprising: (a) using a keystream generated from a predetermined key Perform operations on data to be sent through the bus to encrypt the data; (b) send encrypted data to a predetermined module through the bus; (c) send a synchronization signal to a predetermined module when sending encrypted data through the bus module.

According to another aspect of the present invention, there is provided a method for decrypting data, comprising: (a) receiving encrypted data from a predetermined module through a bus; (b) receiving a synchronization signal, wherein, when sending encrypted data through a bus The synchronization signal is logic high; (c) when the synchronization signal is logic high, performing an operation on the encrypted data using a keystream generated from a predetermined key.

The method of decrypting data may further include synchronizing the synchronization signal with a clock signal of the bus.

The method of decrypting data may further include: performing an exclusive OR (XOR) operation on the encrypted data and the key stream to decrypt the encrypted data.

According to another aspect of the present invention, there is provided a computer-readable recording medium having recorded thereon a computer program for performing a method of decrypting data, the method comprising: (a) receiving encrypted data from a predetermined module through a bus; (b) receiving a synchronization signal, wherein the synchronization signal is logic high when the encrypted data is sent over the bus; (c) when the synchronization signal is logic high, encrypting the encrypted data with a key stream generated from a predetermined key perform an action.

According to another aspect of the present invention, there is provided a bus system comprising at least two modules connected to the bus, wherein each module comprises a module core and a wrapper (wrapper) for interfacing the module core with the bus, the wrapper The device encrypts the first data signal generated from the module core to transmit the first encrypted data signal through the bus, and when transmitting the first encrypted data signal through the bus, outputs a first synchronization signal of logic high; in addition , when the second data signal is sent through the bus, the wrapper decrypts the second data signal received from the bus according to the logic high second synchronization signal, and provides the decrypted second data signal to the module core.

The wrapper may include: a stream cipher transmitter that generates a key stream from a predetermined key when generating a first data signal from the module core; a stream cipher receiver that generates a key stream according to a second synchronization when receiving a second data signal from the bus Signal to generate a keystream.

The keystream may be generated from a seed including a predetermined key and additional information, and the seed may be commonly applied to each module.

The wrapper may further include: a first operation unit for performing an exclusive OR (XOR) operation on the key stream and the first data signal to generate a first encrypted data signal; a second operation unit for performing an exclusive OR (XOR) operation on the key stream and the second data signal The signals are XORed to generate a decrypted second data signal.

The system may further include a first synchronization signal and a second synchronization signal transmitted through each of the plurality of dedicated lines of the module.

Description of drawings

The above and other aspects of the invention will become more apparent by describing in detail exemplary embodiments of the invention with reference to the accompanying drawings, in which:

Fig. 1 is the block diagram of the stream cipher system of prior art;

2 is a block diagram of a bus system configured in 1:1 according to an exemplary embodiment of the present invention;

3 is a block diagram illustrating in detail a data transmission operation in a bus system according to an exemplary embodiment of the present invention;

4 is a block diagram schematically showing a wrapper (wrapper) included in a bus system according to an exemplary embodiment of the present invention;

5 is a block diagram of a bus system configured in N:N according to an exemplary embodiment of the present invention;

6 is a block diagram illustrating in detail a method for encrypting and decrypting data in a bus system according to an exemplary embodiment of the present invention;

7 is a flowchart illustrating a method of encrypting data according to an exemplary embodiment of the present invention;

FIG. 8 is a flowchart illustrating a method of decrypting data according to an exemplary embodiment of the present invention.

Detailed ways

Example embodiments will be described more fully hereinafter with reference to the accompanying drawings, in which example embodiments are shown. However, this invention may be embodied in many different forms and should not be construed as limited to the exemplary embodiments set forth herein; The concept is fully conveyed to those skilled in the art. In the drawings, like reference numerals denote like components, and the size and thickness of layers and regions are exaggerated for clarity. Also, the terms used herein are defined according to the functions of the present invention. Therefore, terminology may vary according to user or operator and usage. That is, the terms used here must be understood based on the descriptions here.

FIG. 2 is a block diagram of a bus system in a 1:1 configuration according to an embodiment of the present invention.

Referring to FIG. 2 , a bus system in a 1:1 configuration according to an exemplary embodiment of the present invention includes: a first module core 21 , a first wrapper 22 , a second module core 23 , a second wrapper 24 and a bus 25 . Each of the first module core 21 and the second module core 23 independently may be one of a central processing unit (CPU), a peripheral component interconnect (PCI), and a universal asynchronous receiver/transmitter (UART).

The first wrapper 22 converts the output signal of the first module core 21 according to the transmission specification of the bus 25 , and monitors the control signal and data signal received from the bus 25 , so as to interface the first module core 21 with the bus 25 . Furthermore, the first wrapper 22 includes a first stream cipher transmitter (TxSc) 221 and a first stream cipher receiver (Rx Sc) 222.

The second wrapper 24 converts the output signal of the second module core 23 according to the transmission specification of the bus 25 , and monitors the control signal and data signal received from the bus 25 , so as to interface the second module core 23 with the bus 25 . Furthermore, the second wrapper 24 includes a second stream cipher receiver (RxSc) 241 and a second stream cipher transmitter (Tx Sc) 242.

The first stream cipher transmitter 221 and the second stream cipher transmitter 242 encrypt data to be transmitted via the bus 25 . More specifically, the first stream cipher transmitter 221 and the second stream cipher transmitter 242 generate a key stream from a seed (seed) including a predetermined key and additional information (for example, an initialization vector), and perform an operation on the generated key stream An operation is performed on data to be sent via the bus 25, thereby encrypting the data. For example, the first stream cipher transmitter 221 and the second stream cipher transmitter 242 may perform an XOR operation on the generated key stream and data to be transmitted via the bus 25, thereby encrypting the data.

The first stream cipher receiver 222 and the second stream cipher receiver 241 decrypt encrypted data received from the bus 25 . More specifically, the first stream cipher receiver 222 and the second stream cipher receiver 241 generate a key stream from a seed including a predetermined key and additional information, and compare the generated key stream and the encrypted data received from the bus 25 Perform an operation to decrypt the data. For example, the first stream cipher receiver 222 and the second stream cipher receiver 241 may perform an XOR operation on the generated key stream and encrypted data received from the bus 25, thereby decrypting the data.

In this case, the first stream cipher transmitter 221 and the second stream cipher transmitter 242 and the first stream cipher receiver 222 and the second stream cipher receiver 241 may have a common seed. More specifically, the same seed may be supplied to the first stream cipher transmitter 221 , the first stream cipher receiver 222 , the second stream cipher receiver 241 and the second stream cipher transmitter 242 when the power is turned on. Therefore, the first stream cipher transmitter 221 , the first stream cipher receiver 222 , the second stream cipher receiver 241 and the second stream cipher transmitter 242 can generate the same key stream. However, the order of key streams used by the synchronization signals of each pair of the first stream cipher transmitter 221 and the second stream cipher receiver 241 pair and the pair of the first stream cipher receiver 222 and the second stream cipher transmitter 242 can be determined by Change. The synchronization signal will be described with reference to FIG. 3 .

Each of the first stream cipher transmitter 221, the first stream cipher receiver 222, the second stream cipher receiver 241, and the second stream cipher transmitter 242 may use Route Coloniale 4 (RC4). RC4 is an encryption algorithm in stream form, which changes the length of the key through byte operations, and supports very fast encryption speed (compared with block encryption algorithms). However, this is only an exemplary embodiment of the present invention, and the first stream cipher transmitter 221, the first stream cipher receiver 222, the second stream cipher receiver 241 and the second stream cipher transmitter 242 can use other algorithms, which are of great significance to those skilled in the art. It is obvious to those of ordinary skill.

FIG. 3 is a block diagram illustrating in detail a data transmission operation in a bus system according to an exemplary embodiment of the present invention.

Referring to FIG. 3 , a bus system in a 1:1 configuration according to an exemplary embodiment of the present invention includes a first module wrapper 31 , a second module wrapper 32 and a bus 33 . The first module wrapper 31 includes a stream cipher transmitter (Tx Sc) 311, and the second module wrapper 32 includes a stream cipher receiver (Rx Sc) 321.

When data is input, the first module wrapper 31 encrypts the data into encrypted data E_DATA in the stream cipher transmitter 311 and transmits the encrypted data E_DATA to the second module wrapper 32 through the bus 33 . When the encrypted data E_DATA is received by the second module wrapper 32, the second module wrapper 32 decrypts the encrypted data E_DATA in the stream cipher receiver 321, and provides the decrypted data to the 32 modules (not shown).

In this case, when the encrypted data E_DATA is transmitted through the bus 33 , the first module wrapper 31 generates a synchronization signal synchronized with a clock signal (not shown) of the bus 33 . Depending on the encrypted data E_DATA, the synchronization signal is switched between logic high and logic low. For example, the sync signal may be switched to logic "high" only when encrypted data E_DATA is provided to the bus, and may be switched to logic "low" when encrypted data E_DATA is not provided to the bus.

The synchronization signal generated from the first module wrapper 31 is supplied to the stream cipher receiver 321 included in the second module wrapper 32 . In an exemplary embodiment of the present invention, the synchronization signal may be supplied to the second module wrapper 32 through a dedicated line. Since the signal transmitted through the bus 33 should conform to the bus specification, the synchronization signal is transmitted through a separate dedicated line (not shown) instead of the bus 33, so that the specification of the bus does not need to be changed, thereby improving compatibility. In another exemplary embodiment of the present invention, the synchronization signal may be controlled by the bus controller to be sent through the bus 33 . Also, in another exemplary embodiment of the present invention, instead of generating a synchronization signal, the first module wrapper 31 may synchronize with the second module wrapper 32 by using a control signal of the bus 33 . In this case, however, implementation in such a configuration may be complicated.

The stream cipher receiver 321 included in the second module wrapper 32 simultaneously receives the encrypted data E_DATA from the bus 33 and the synchronization signal generated from the first module wrapper 31 . The stream cipher receiver 321 generates a key stream according to the synchronization signal, and performs an operation on the encrypted data E_DATA and the key stream, thereby decrypting the data.

FIG. 4 is a block diagram schematically showing an example of a wrapper included in a bus system according to an exemplary embodiment of the present invention.

Referring to FIG. 4 , the wrapper 40 includes a stream cipher transmitter (Tx Sc) 41 and a stream cipher receiver (RxSc) 42. The stream cipher transmitter (Tx Sc) 41 encrypts the first data signal into a first encrypted data signal E_DATA1, and provides the first encrypted data signal E_DATA1 to the bus. The stream cipher receiver 42 decrypts the second encrypted data signal E_DATA2 received from the bus.

The wrapper 40 sends the first synchronization signal switching between logic high and logic low according to the first encrypted data signal E_DATA1 to another module through a separate dedicated line instead of a bus. Furthermore, the wrapper 40 receives a second synchronization signal switching between logic high and logic low according to the second encrypted data signal E_DATA2 from another module through a separate dedicated line (instead of a bus). In other words, wrapper 40 may have two separate dedicated lines in addition to the bus. When multiple different modules are each connected in a 1:1 configuration, the wrapper 40 can have two dedicated lines, and when each of the different modules is connected in a 1:N configuration, the wrapper 40 can have 2N dedicated lines Wire. Here, N is a natural number greater than 1.

FIG. 5 is a block diagram of a bus system in an N:N configuration according to an exemplary embodiment of the present invention.

With reference to Fig. 5, the bus system with N:N configuration according to the exemplary embodiment of the present invention includes: CPU51, PCI 53, UART 55 and bus 59. Furthermore, the bus system configured in N:N may also include further modules 57 . Here, the CPU 51, PCI 53, and UART 55 are just examples of modules connected to the bus 59, and may be other modules or any modules developed in the future.

The CPU 51 is the core device of the computer system, controls processing such as interpreting instructions, manipulating data, and comparing, and also includes a CPU wrapper 52 to interface with a bus 59. The CPU wrapper 52 may include a first stream cipher transmitter 521 and a first stream cipher receiver 522 .

PCI 53 is an interconnection system in a device that plugs into an expansion slot that is placed close to the microprocessor for high-speed operation, PCI 53 also includes a PCI wrapper 54 to interface with a bus 59 . The PCI wrapper 54 may include a second stream cipher transmitter 541 and a second stream cipher receiver 542 .

The UART 55 is the module that handles the computer's asynchronous serial communications, usually in the form of a microchip, and also includes a UART wrapper 56 to interface with the bus 59. The UART wrapper 56 may also include a third stream cipher transmitter 561 and a third stream cipher receiver 562 .

Other modules 57 may be modules developed in the future and also include wrapper 58 to interface with bus 59 . The wrapper 58 may include a fourth stream cipher transmitter 581 and a fourth stream cipher receiver 582 .

Since the bus system in FIG. 5 includes four modules, N is 4, and the bus system in FIG. 5 is configured in 4:4. Here, when independently operating each of the stream cipher transmitter and the stream cipher receiver, the modules of the bus system can be 4×3 pairs (ie, N×(N-1)), requiring 2×4×3 ( That is, 2×N×(N−1)) stream cipher transmitters/receivers, so the configuration of the bus system may be complicated.

However, in an exemplary embodiment of the present invention, stream cipher transmitters/receivers share a common seed, and thus encryption and decryption can be performed with only 2×4 (ie, 2×N) stream cipher transmitters/receivers. As described above, since the seed here includes a predetermined key and additional information (for example, an initialization vector IV), the stream cipher transmitter/receiver generates a key stream based on the seed. That is, the first to fourth stream cipher transmitters 521, 541, 561, and 581 and the first to fourth stream cipher receivers 522, 542, 562, and 582 share a common seed, and therefore, can be obtained by using only 8 The unit simply implements a bus system in an N:N configuration.

In this case, one module can broadcast a sync signal to all modules. For example, CPU wrapper 52 may broadcast a synchronization signal such that the synchronization signal is sent to PCI wrapper 54 , UART wrapper 56 , and wrapper 58 . However, this is only an example of the present invention, the plurality of modules may be divided into at least two groups, and the synchronization signal may be sent to at least one of the at least two groups. For example, since the PCI 53 and UART 55 are referred to as the first group and the other modules are referred to as the second group, the CPU wrapper 52 may only send synchronization signals to the PCI wrapper 54 and the UART wrappers included in the first group Device 56.

In an exemplary embodiment of the present invention, the synchronization signal may be a 1-bit signal. Since the bus system of FIG. 5 includes 4 modules, there are 2×4 (i.e., 2×N) stream cipher transmitters and receivers; however, 4×3 (i.e., N×(N−1)) are required synchronization signal. Therefore, typically 4x3 (ie, Nx(N-1)) bits of overhead bits are generated.

FIG. 6 is a block diagram illustrating in detail a method of encrypting and decrypting data in a bus system according to an exemplary embodiment of the present invention.

Referring to FIG. 6 , a bus system according to an exemplary embodiment of the present invention includes a module core 61 and a wrapper 62 . The wrapper 62 includes a stream cipher transmitter (Tx Sc) 621 and a stream cipher receiver (Rx Sc) 622. In addition, the wrapper 62 may further include a first operating unit 623 and a second operating unit 634 .

The module core 61 may be any module such as CPU or PCI. The module core 61 can request to read/write data, and the data requested to be read/written is plain text data PD without encryption. Data generated from the module core 61 should be sent to the target module through the bus; however, the data may be exposed to the outside from the bus. Therefore, plaintext data PD is encrypted into ciphertext data CD to be sent via the bus.

Hereinafter, the operation of the wrapper 62 will be described by dividing it into an encryption operation and a decryption operation.

First, during encryption, the wrapper 62 detects the plain text data PD1 input from the module core 61, and the stream cipher transmitter 621 included in the wrapper 62 generates a key stream to be synchronized with the clock signal of the bus. As described above, the stream cipher transmitter 621 generates a key stream from a seed including a predetermined key and additional information. Here, the generated key stream can be a random number and can be changed in different ways.

The first operation unit 623 included in the wrapper 62 performs an operation on the generated key stream and the plaintext data PD1 to generate encrypted data, that is, ciphertext data CD1. Here, in an exemplary embodiment of the present invention, the first operation unit 623 may perform an operation on the generated key stream and plain text data PD1 to generate cipher text data CD1.

The wrapper 62 generates a synchronization signal which is logic "high" when the ciphertext data CD1 is transmitted through the bus while transmitting the ciphertext data CD1 through the bus. In other words, the synchronization signal switches between logic high and logic low according to the ciphertext data CD1, and should be synchronized with the clock signal of the bus. Here, the sync signal is switched to logic “low” when the frame of data in the bus is truncated in the middle of the frame due to delay, and also switched to logic “high” when the data is sent again. Therefore, it is possible to generate a key stream that is precisely synchronized with the ciphertext data CD1 received by the stream cipher receiver of the target module. In another exemplary embodiment, wrapper 62 may send synchronization signals to other modules. In this case, the wrapper 62 may broadcast the synchronization signal or divide the modules into groups to send the synchronization signal to some groups.

Next, during decryption, the wrapper 62 detects the encrypted data received from the bus, ie, the ciphertext data CD2. Furthermore, the stream cipher receiver 622 included in the wrapper 62 receives the synchronization signal, and generates a key stream based on the synchronization signal. In this case, the seed on which the key stream is generated is the same as the stream cipher transmitter/receiver of the stream cipher transmitter 621 and other modules. The synchronization signal is provided by the module that generates the ciphertext data CD2, and switches between logic high and logic low according to the ciphertext data CD2. In another exemplary embodiment of the present invention, wrapper 62 may receive the synchronization signal from other modules.

The stream cipher receiver 622 included in the wrapper 62 performs an operation on the generated key stream and ciphertext data CD2, and generates decrypted ciphertext data CD2 (ie, plaintext data) as a result. Here, in an exemplary embodiment of the present invention, the stream cipher receiver 622 may perform an XOR operation on the generated key stream and the ciphertext data CD2, and generate the plaintext data PD2.

FIG. 7 is a flowchart illustrating a method of encrypting data according to an exemplary embodiment of the present invention.

Referring to FIG. 7 , a method of encrypting data according to an exemplary embodiment of the present invention includes time-series operations performed in the bus system of FIG. 6 . Therefore, even if any description is omitted below, the description of the bus system of FIG. 6 is applicable to the encryption method according to the exemplary embodiment of the present invention shown in FIG. 7 .

Referring to FIG. 7, in operation 71, when data is generated in a module that transmits data, a wrapper connected to the module performs an operation on the data to be transmitted through the bus using a key stream generated from a predetermined key, thereby performing an operation on the data. encryption. In an exemplary embodiment of the present invention, an XOR operation may be performed on data to be transmitted through the bus and a key stream to encrypt the data. Here, a key stream is generated based on a seed including a predetermined key and additional information, and the key stream may be synchronized with a clock signal of the bus. Here, the additional information may be expressed as an initialization vector.

In operation 72, the wrapper sends the encrypted data to the predetermined module through the bus. In an exemplary embodiment of the present invention, there may be at least two predetermined modules.

In operation 73, when the encrypted data is transmitted through the bus, a synchronization signal of logic high is transmitted to a predetermined module. Here, the synchronization signal may be synchronized with the clock signal of the bus. In an exemplary embodiment of the present invention, there may be at least two predetermined modules, and a synchronization signal may be broadcasted. Here, the synchronization signal may be transmitted through respective dedicated lines of at least two modules, or may be transmitted through the control of the controller of the bus. In another exemplary embodiment of the present invention, there may be at least two predetermined modules, the at least two predetermined modules may be divided into groups, and a synchronization signal may be transmitted to at least one group.

FIG. 8 is a flowchart illustrating a method of decrypting data according to an exemplary embodiment of the present invention.

Referring to FIG. 8 , a method of decrypting data according to an exemplary embodiment of the present invention includes time-series operations performed in the bus system of FIG. 6 . Therefore, even if any description is omitted below, the description of the bus system of FIG. 6 is applicable to the decryption method according to the current exemplary embodiment of the present invention shown in FIG. 8 .

Referring to FIG. 8, in operation 81, a wrapper connected to a module receiving data receives encrypted data from a predetermined module through a bus.

At operation 82, the wrapper receives a logic high sync signal when the encrypted data is sent over the bus. Here, the synchronization signal may be synchronized with the clock signal of the bus.

In operation 83, when the synchronization signal is logic high, the wrapper performs an operation on the encrypted data using a key stream generated from a predetermined key, thereby decrypting the data. In an embodiment of the present invention, an XOR operation may be performed on the key stream and the encrypted data to decrypt the encrypted data.

The present invention is not limited to the exemplary embodiments described above, and those skilled in the art can make appropriate modifications.

The present invention can also be embodied as computer readable codes on a computer readable recording medium. The computer readable recording medium is any data storage device that can store data which can be thereafter read by a computer system. Examples of the computer-readable recording medium include: read-only memory (ROM), random-access memory (RAM), CD-ROM, magnetic tape, hard disk, floppy disk, flash memory, optical data storage device, and carrier wave (such as via the Internet) data transmission). The computer readable recording medium can also be distributed over network coupled computer systems so that the computer readable code is stored and executed in a distributed fashion.

According to the present invention, an operation is performed on data to be transmitted through a bus with a key stream generated from a predetermined key to encrypt the data, and the encrypted data is transmitted to a predetermined module through the bus. In addition, a synchronization signal is provided to a predetermined module to decrypt data with reference to the synchronization signal, which is logic high when the encrypted data is transmitted through the bus. Therefore, the security of data sent over the bus can be improved.

Furthermore, according to the present invention, when the power is turned on, a synchronization signal is broadcasted and a common seed is shared, so the number of stream cipher transmitters/receivers can be reduced, thereby realizing a simple bus system. Furthermore, security can be maintained even when a new module is attached outside the trusted area, so the bus can easily expand the system. Therefore, when at least one individual module is mounted on the outside of the chip, when various modules are mounted on the board, when dedicated lines are used, and when in an open bus system, data encryption and The method of decryption can be effectively used.

While the invention has been particularly shown and described with reference to exemplary embodiments thereof, it will be understood by those skilled in the art that changes in form and details may be made without departing from the spirit and scope of the invention as defined by the claims. Make various changes.

Claims (16)

1. A method of encrypting data, said method comprising: (a) performing an operation on data to be sent over the bus with a key stream generated from a predetermined key to encrypt the data; (b) Send the encrypted data to the predetermined module through the bus; (c) when the encrypted data is sent to the predetermined module through the bus, send a synchronization signal switched to logic high, Wherein, in step (c), the synchronization signal is broadcast to at least two predetermined modules. 2. The method of claim 1, wherein the data is encrypted by performing an XOR operation on the data and the key stream. 3. The method of claim 2, wherein the keystream is generated based on a seed comprising a predetermined key and additional information, wherein the seed is commonly applied during decryption of the encrypted data in the module receiving the encrypted data . 4. The method of claim 2, wherein the key stream is generated to be synchronized with a clock signal of the bus. 5. The method of claim 1, wherein the synchronization signal is synchronized with a clock signal of the bus. 6. The method of claim 1, wherein in step (c), a synchronization signal is transmitted through each of the plurality of dedicated lines of the at least two predetermined modules. 7. The method of claim 1, wherein in step (c), the synchronization signal is sent to the bus by a controller of the bus. 8. The method of claim 5, wherein the at least two predetermined modules are divided into groups, and the synchronization signal is transmitted to at least one group. 9. A method of decrypting data comprising: (a) receiving encrypted data from the encryption module via the bus; (b) receiving a sync signal that is logic high when encrypted data is sent over the bus; (c) when the sync signal is logic high, perform an operation on the encrypted data using the keystream generated from the predetermined key, Wherein, in step (b), the synchronization signal is broadcast to at least two predetermined modules by the encryption module. 10. The method of claim 9, wherein the synchronization signal is synchronized with a clock signal of the bus. 11. The method of claim 9, wherein in step (c), an exclusive OR operation is performed on the encrypted data and the key stream to decrypt the encrypted data. 12. A bus system comprising at least two modules connected to the bus, wherein each module comprises a module core and a wrapper for interfacing the module core with the bus, wherein: The wrapper encrypts a first data signal generated from the module core to send the first encrypted data signal over the bus, and when said first encrypted data signal is sent over the bus, the output switches to a first synchronous logic high Signal; When the second data signal is sent through the bus, the wrapper decrypts the second data signal received from the bus according to the second synchronization signal switched to logic high, and provides the decrypted second data signal to the module core, Wherein, the first synchronization signal is broadcast to at least two modules that need to decrypt the first encrypted data signal, and the second synchronization signal is broadcast to at least two modules that need to decrypt the second data signal. 13. The system of claim 12, wherein the wrapper comprises: A stream cipher transmitter, when generating the first data signal from the module core, generates a key stream from a predetermined key; The stream cipher receiver, when receiving the second data signal from the bus, generates a key stream according to the second synchronization signal. 14. The system of claim 13, wherein the keystream is generated from a seed comprising a predetermined key and additional information, the seed being commonly applied to each module. 15. The system of claim 13, wherein the wrapper further comprises: The first operation unit performs an XOR operation on the key stream and the first data signal to generate a first encrypted data signal; The second operation unit executes an XOR operation on the key stream and the second data signal to generate a decrypted second data signal. 16. The system of claim 12, wherein the first synchronization signal and the second synchronization signal are transmitted through each of the plurality of dedicated lines of the at least two modules.

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