CN101295979A - FPGA logical block based on part partial interconnection structure - Google Patents
FPGA logical block based on part partial interconnection structure Download PDFInfo
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- CN101295979A CN101295979A CNA2007100987013A CN200710098701A CN101295979A CN 101295979 A CN101295979 A CN 101295979A CN A2007100987013 A CNA2007100987013 A CN A2007100987013A CN 200710098701 A CN200710098701 A CN 200710098701A CN 101295979 A CN101295979 A CN 101295979A
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Abstract
The invention discloses an FPGA logic block based on a partially local interconnection structure, which is characterized in that the FPGA logic block comprises 8 logical units which are connected by adopting special carry chains; the logical unit comprises 12 ports which insludes 5 data input ports, 3 input control ports, 1 clock input port and 3 output ports and 42 ports which includes 2 global input ports, 24 input ports and 16 output ports; the interior of the logic block adopts the partially local interconnection structure and the inner local interconnection of the logic block is evenly distributed; the input and output ports of the logic block are evenly distributed around the rectangular logic block and the input and output ports of the logical unit are evenly connected to the ports around the logic block; in addition, connecting units in the logic block adopt secondary multiplexers.
Description
Technical field
The present invention relates to a kind of fpga logic piece, more specifically be meant a kind of fpga logic piece based on part partial interconnection structure.
Background technology
The user-programmable of field programmable gate array (FPGA) and low development cost make it become a kind of important technology of realizing modern circuit and system.Interconnection resource is a very important part among the FPGA, and reason is that interconnection resource has taken the chip area of FPGA about 84%～92%, wherein the local interlinkage resource occupation of logical block inside the chip area of FPGA about 26%～46%.Therefore, the quality of the local interlinkage structure of logical block inside directly has influence on the performance of fpga chip.
In the design of FPGA, the local interlinkage of general logical block inside adopts complete ways of connecting, promptly allows each input (output) port of logical block can both be connected to all logical block input (output) ports.This highdensity connectedness makes wiring be more prone to, but has but increased the expense for area greatly.Therefore the structure of part partial interconnection is adopted in the logical block of a lot of commercial FPGA inside, such as the Stratix family chip of Altera.In the Stratix family chip, the input port of each logical block can be connected to logical block input port and the logical block output port of half, has formed 50% degree of communication.Experimental data shows that this structure has reduced about 7% area, and wiring delay has only increased 1%.
Present different FPGA manufacturer has adopted the logical block of different structure in logical block inside, because the difference of logical block design, the local interlinkage structure of logical block inside also has very big difference.Each port of logical block all has different logic behaviours, and the logic port of different qualities has different demands to interconnection resource.Therefore in the design part partial interconnection structure, need set different connectednesses according to the difference of port identity, some port also needs to carry out special design, thereby the inner local interlinkage resources effective of assurance logical block is utilized.
Adopt part partial interconnection structure to reduce the area of logical block, but increased the difficulty that auto-placement tool wiring and logical mappings instrument are packed logical block.Traditional logical block packing algorithm is not considered the distribution of logical block internal wiring resources effective based on complete local interlinkage structure.Adopt complete Matching Algorithm to realize the distribution of logical block internal wiring resource, the time complexity of software is too high, is not suitable for packing in the middle of the realization of algorithm.Adopt the approximate data of greedy strategy, can greatly reduce time complexity, relatively be adapted at packing in the algorithm realizing.But greedy strategy greatly depends on the appropriate design of intraconnection structure.Therefore it is extremely important to design the part partial interconnection structure that is fit to greedy strategy.
Summary of the invention
The objective of the invention is to, a kind of fpga logic piece based on part partial interconnection structure is provided, it is compared with the logic-block structure of complete local interlinkage, has taken littler chip area.
A kind of fpga logic piece based on part partial interconnection structure of the present invention is characterized in that, comprising:
8 logical blocks adopt special-purpose carry chain to connect between this logical block; This logical block comprises 12 ports, and these 12 ports comprise 5 data input ports, 3 control input end mouths, 1 input end of clock mouth, 3 output ports;
42 ports, these 42 ports comprise 2 overall input ports, 24 input ports and 16 output ports;
The inner part partial interconnection structure that adopts of this logical block;
The inner local interlinkage of this logical block is equally distributed, and the logical block input/output port is evenly distributed on around the rectangle logical block, and the input/output port of logical block is connected to the port around the logical block equably;
The linkage unit of logical block inside adopts the secondary multiplexer.
Wherein the local interlinkage of this logical block inside is:
Logical block overall situation input port is connected with logical block input end of clock mouth;
The logical block input port is connected with the logical block input port;
The logical block output port is connected with the logical block output port;
The logical block output port is connected with logical block data input port feedback;
The local interlinkage that described logical block overall situation input port is connected with logical block input end of clock mouth is to adopt complete connection mode, and promptly the clock port of each logical block is connected to all logical block overall situation input ports; Other local interlinkage adopts the part interconnection pattern.
Wherein the degree of communication of 5 of this logical block data input ports, 3 control input end mouths, 1 the input end of clock mouth input port in the logical block port is respectively 0.5,0.5,0.5,0.25,0.25,0.25,0.25,0.25,0.25.
Wherein 3 of logical block output ports are 0.5 to the degree of communication of logical block output port.
Wherein 3 of logical block output ports are respectively 0.25,0.5,0.5 to the degree of communication of logical block data input port.
Wherein said secondary multiplexer uses the NMOS transfer tube as switch element, and under SMIC 0.13 CMOS process conditions, the grid width of NMOS transfer tube is 0.13 micron.
Description of drawings
For further specify that concrete technology contents of the present invention describes in detail below in conjunction with embodiment and accompanying drawing as after, wherein:
Shown in Fig. 1 is logical block port distribution figure.
Shown in Fig. 2 is logical unit structure figure.
Shown in Fig. 3 is the interconnection network (control and clock port interconnection structure regulate preceding) of logical block input port to the logical block input port.
Shown in Fig. 4 is the interconnection network (control and clock port interconnection structure regulate back) of logical block input port to the logical block input port.
Shown in Fig. 5 is the carry chain interconnection network.
Shown in Fig. 6 is secondary multiplexer topology diagram.
Shown in Fig. 7 is the influence tendency chart of logical block input port number to the FPGA area.
Embodiment
See also Fig. 1, Fig. 2 and shown in Figure 3, a kind of fpga logic piece based on part partial interconnection structure of the present invention comprises:
8 logical blocks 43 (among Fig. 3) adopt special-purpose carry chain to connect between this logical block 43; This logical block 43 comprises 12 ports, and these 12 ports comprise 47,1 input end of clock mouth CK of 46,3 control input end mouths of 5 data input ports, 3 output ports 48;
42 ports 42 (among Fig. 1), these 42 port ones 0 comprise 2 overall input ports, 24 input ports and 16 output ports;
The inner part partial interconnection structure that adopts of this logical block;
The inner local interlinkage of this logical block is equally distributed, and the logical block input/output port is evenly distributed on around the rectangle logical block, and the input/output port of logical block 43 is connected to the port 42 around the logical block equably;
Wherein the local interlinkage of this logical block inside is:
Logical block overall situation input port is connected (among Fig. 2) with logical block 43 input end of clock mouth CK;
The logical block input port is connected with logical block 43 inputs 49;
The logical block output port is connected with logical block 43 outputs 48;
The logical block output port is connected with logical block 43 data-in ports 46 feedbacks;
The local interlinkage that described logical block overall situation input port is connected with logical block 43 input end of clock mouth CK is to adopt complete connection mode, and promptly the clock port CK of each logical block 43 is connected to all logical block overall situation input ports; Other local interlinkage adopts the part interconnection pattern.
Wherein the degree of communication of the input port of 47,1 input end of clock mouth CK of 46,3 control input end mouths of 5 of this logical block 43 data input ports in the logical block port 42 is respectively 0.5,0.5,0.5,0.25,0.25,0.25,0.25,0.25,0.25.
Wherein 3 of logical block 43 output ports 4 are 0.5 to the degree of communication of logical block output port.
Wherein 3 of logical block 43 output ports 48 are respectively 0.25,0.5,0.5 to the degree of communication of logical block data input port 46.
The linkage unit of logical block inside adopts secondary multiplexer 50.
Wherein said secondary multiplexer 50 uses NMOS transfer tube 51 as switch element, and under SMIC 0.13 CMOS process conditions, the grid width of NMOS transfer tube 51 is 0.13 micron.
Hereinafter, by reference accompanying drawing and form, example of the present invention will be described in detail.But the present invention can be implemented with many different forms, should not be defined in example given here, this example to provide in order to make the disclosure be completely with complete, and pass on thought of the present invention all sidedly to those skilled in the art.
With reference to Fig. 1, be dispersed with 42 ports 42 around the logical block, comprising 2 overall input ports, 24 input ports and 16 output ports.Wherein input/output port is evenly distributed on around the rectangle logical block.Equally distributed design can the logic of Equilibrium piece to around the demand of wiring channel, avoid the local congestion of wiring channel.
With reference to Fig. 2, the logical block 43 that adopts in the logical block is made up of two three input look-up tables 44 and a trigger 45.Two look-up tables 44 both can work alone, and also can merge becomes one four input look-up table.Logical block 43 comprises data-in port A0, A1, A2, A3, B, control input end mouth CE, SR, REV, input end of clock CK, output port XB, XF, XQ.
The local interlinkage of logical block inside is divided into four parts:
(1), being connected between logical block overall situation input port and the logical block 43 clock port CK;
(2), being connected between logical block input port and logical block 43 input ports 49;
(3), being connected between logical block output port and logical block 43 output ports 48;
(4), the logical block output port is connected with feedback between logical block 43 data-in ports 46;
Local interlinkage (1) adopts complete connection mode, and promptly the clock port CK of each logical block 43 is connected to all logical block overall situation input ports.Aforesaid local interlinkage (2) (3) (4) adopts the part interconnection pattern.Connection Density between the local interlinkage structure middle port is called as degree of communication.In the connection mode, each port is 100% to the degree of communication of other ports fully.Logical block 43 input port A0, A1, A2, A3, B, CK, CE, SR, REV are respectively 0.5,0.5,0.5,0.25,0.25,0.25,0.25,0.25,0.25 to the degree of communication of logical block input port.Logical block 43 output port XB, XF, XQ are 0.5 to the degree of communication of logical block output port.Logical block 43 output port XB, XF, XQ are respectively 0.25,0.5,0.5 to the degree of communication of logical block 43 data-in ports 46.
With reference to Fig. 3, logical block comprises 8 logical blocks 43, logical block 43 input ports 49 are equally distributed to the part partial interconnection of logical block input port, the input/output port of logical block 43 is connected to the port around the logical block equably, the equally distributed mode of the same employing of part interconnection of other types.Equally distributed design has guaranteed that the input/output signal of logical block 43 can increase the degree of freedom of wiring from turnover around the logical block.Equally distributed design has simultaneously reduced based on partial to some logical block port of the logical block packing algorithm of greedy strategy, has increased the availability of logical block port 42.
The number of logical block input/output port draws according to following analysis.Because the existence of carry chain, the input/output port of logical block has the restriction of minimal amount.Length is that the carry chain of 8 logical blocks 43 uses 20 logical block input ports and 16 logical block output ports at most.Therefore the minimal amount of logical block input/output port is respectively 20 and 16.In order to guarantee that input/output port can be evenly distributed in (with reference to Fig. 1) around the logical block, the number of logical block input/output port should be set at 4 multiple.With reference to Fig. 7, when logical block input port number is 24, the area minimum of FPGA, so the number of logical block input port is defined as 24.Wherein the area of FPGA is the average area (according to channel width that minimum require calculate) of 30 reference circuits through drawing after the wiring according to ITC ' 99, reference be SMIC 0.13 CMOS technology, the degree of communication of logical block all of the port all is set at 0.5.Adopt same analysis can determine that the best output port number of logical block is 16, promptly minimum output port number, this is that minimum output port can obtain minimum FPGA area because there is not sharing characteristic in the output port of logical block.The number of logical block overall situation input port is set at and at most only allows to use two different global clocks, experiment to show that this arrangement is reasonably in 2, one logical blocks, is very little because the logical block in the same logical block adopts the probability of different clocks.
With reference to table 1, the utilization rate of logical block 43 each ports has very big difference.Table 1 is the statistics of 30 reference circuits through drawing after the logical mappings according to ITC ' 99, does not wherein comprise the connection that overall signal is shared.Find that according to statistics logical block 43 data-in ports 46 utilization rates are considerably beyond control and clock port.The utilization rate of A0, A1, A2 is the highest in logical block 43 data-in ports 46, and the utilization rate of A3, B is less relatively.The CE utilization rate is the highest among logical block 43 control ports 47 and the clock port CK, and other port utilizations are all very low.Therefore when analyzing each input port degree of communication, should suitably reduce the degree of communication of the low port of utilization rate.The utilization rate of the relative XF of XB, XQ is very low in the output port 48 of logical block 43, according to the method for front, should reduce the degree of communication of XB.But experiment shows that the packing algorithm based on greedy strategy can obtain best result under the identical situation of each output port degree of communication, therefore when selecting each output port degree of communication, their value is consistent.For the feedback interconnection between the logical block in the logical block 43, as can be seen from Table 1, there be not the connection of XB to B, should cancel in the feedback interconnection XB to the connection of B.Cancel the feedback that all are connected to control port 47 and clock port CK, because this feedback seldom occurs in side circuit.The feedback that is connected to XB and XF in the same logical block 43 belongs to combination circulation (combinational cycle), also is cancelled in feedback interconnection.
The degree of communication of logical block 43 each ports draws according to experimental analysis.Its analytical method is similar to the analytical method of logical block input port number.Adopt ITC ' 99 reference circuits, analyze the influence of connectivity pair chip area and critical path delay, therefrom choose optimum value.
With reference to Fig. 4, on the basis of Fig. 3, the interconnection structure of logical block 43 control ports 47 and clock port CK is regulated.Make full use of the sharing characteristic of control and clock signal, reduced the number of logical block input port.43 every type control port 47 and clock port CK have distributed the logical block input port of a special use for logical block, are respectively: logic port 0-＞CE, logic port 1-＞SR, logic port 2-＞REV, logic port 3-＞CK.The reservation private port is connected with logical block 43 data-in ports 46, the cancellation private port with non-under being connected of type control port 47 and clock port CK, and increase extra connection with guarantee this port be connected to all its under the control port 47 or the clock port CK of type.For example, 43 control port CE have distributed the logical block input port 0 of a special use for logical block, interconnection structure between logical block input port 0 and logical block 43 data-in ports 46 remains unchanged, being connected of SR, the REV of cancellation logical block input port 0 and all logical blocks 43, CK port, increase the extra CE port that assurance logical block input port 0 is connected to all logical blocks 43 that connects.
With reference to Fig. 5, CO between the logical block 43 and CI port are connected to each other by special-purpose carry chain.The CO port of each logical block 43 directly links to each other with the CI port of the logical block 43 of adjacent upside.The CO port of chip top logical block 43 directly links to each other with the CI port of bottom, adjacent right side logical block 43.Special-purpose carry chain connects the adjacent logical block 43 of permission and is cascaded, and has accelerated the connection between the logical block, and has saved the local interlinkage resource of logical block inside.
With reference to Fig. 6, use secondary multiplexer 50 as its linkage unit in the inner local interlinkage structure of logical block.Use NMOS transfer tube 51 as switch element, under SMIC 0.13 CMOS process conditions, the grid width of NMOS transfer tube 51 is 0.13 micron.Use SPICE that the sequential time delay of different progression multiplexers 50 is analyzed, consider that simultaneously device area, result show that secondary multiplexer 50 has best combination property.
Though described the present invention in detail with reference to exemplary embodiment, those those of ordinary skill in the art will understand, and under the situation that does not break away from appended claim, can make various variations in form and details at this point.
Claims (6)
1. the fpga logic piece based on part partial interconnection structure is characterized in that, comprising:
8 logical blocks adopt special-purpose carry chain to connect between this logical block; This logical block comprises 12 ports, and these 12 ports comprise 5 data input ports, 3 control input end mouths, 1 input end of clock mouth, 3 output ports;
42 ports, these 42 ports comprise 2 overall input ports, 24 input ports and 16 output ports;
The inner part partial interconnection structure that adopts of this logical block;
The inner local interlinkage of this logical block is equally distributed, and the logical block input/output port is evenly distributed on around the rectangle logical block, and the input/output port of logical block is connected to the port around the logical block equably;
The linkage unit of logical block inside adopts the secondary multiplexer.
2. the fpga logic piece based on part partial interconnection structure as claimed in claim 1 is characterized in that wherein the local interlinkage of this logical block inside is:
Logical block overall situation input port is connected with logical block input end of clock mouth;
The logical block input port is connected with the logical block input port;
The logical block output port is connected with the logical block output port;
The logical block output port is connected with logical block data input port feedback;
The local interlinkage that described logical block overall situation input port is connected with logical block input end of clock mouth is to adopt complete connection mode, and promptly the clock port of each logical block is connected to all logical block overall situation input ports; Other local interlinkage adopts the part interconnection pattern.
3. the fpga logic piece based on part partial interconnection structure as claimed in claim 1, it is characterized in that wherein the degree of communication of 5 of this logical block data input ports, 3 control input end mouths, 1 the input end of clock mouth input port in the logical block port is respectively 0.5,0.5,0.5,0.25,0.25,0.25,0.25,0.25,0.25.
4. the fpga logic piece based on part partial interconnection structure as claimed in claim 1 is characterized in that, wherein 3 of logical block output ports are 0.5 to the degree of communication of logical block output port.
5. the fpga logic piece based on part partial interconnection structure as claimed in claim 1 is characterized in that, wherein 3 of logical block output ports are respectively 0.25,0.5,0.5 to the degree of communication of logical block data input port.
6. the fpga logic piece based on part partial interconnection structure as claimed in claim 1, it is characterized in that, wherein said secondary multiplexer uses the NMOS transfer tube as switch element, and under SMIC 0.13CMOS process conditions, the grid width of NMOS transfer tube is 0.13 micron.
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Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102116841A (en) * | 2011-01-04 | 2011-07-06 | 复旦大学 | Method for evaluating FPGA (Field Programmable Gata Array) interconnection structure based on quantization of model |
| CN102176673A (en) * | 2011-02-25 | 2011-09-07 | 中国科学院半导体研究所 | LUT4 (look up table), logical unit of FPGA (field programmed gate array) and logical block of FPGA |
| CN105634468A (en) * | 2014-10-30 | 2016-06-01 | 京微雅格（北京）科技有限公司 | FPGA layout method and macro element |
Family Cites Families (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5477165A (en) * | 1986-09-19 | 1995-12-19 | Actel Corporation | Programmable logic module and architecture for field programmable gate array device |
| US5394033A (en) * | 1993-09-01 | 1995-02-28 | Lattice Semiconductor Corporation | Structure and method for implementing hierarchical routing pools in a programmable logic circuit |
| US5977791A (en) * | 1996-04-15 | 1999-11-02 | Altera Corporation | Embedded memory block with FIFO mode for programmable logic device |
| US6911704B2 (en) * | 2003-10-14 | 2005-06-28 | Advanced Micro Devices, Inc. | Memory cell array with staggered local inter-connect structure |
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Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102116841A (en) * | 2011-01-04 | 2011-07-06 | 复旦大学 | Method for evaluating FPGA (Field Programmable Gata Array) interconnection structure based on quantization of model |
| CN102116841B (en) * | 2011-01-04 | 2014-09-03 | 复旦大学 | Method for evaluating FPGA (Field Programmable Gata Array) interconnection structure based on quantization of model |
| CN102176673A (en) * | 2011-02-25 | 2011-09-07 | 中国科学院半导体研究所 | LUT4 (look up table), logical unit of FPGA (field programmed gate array) and logical block of FPGA |
| CN102176673B (en) * | 2011-02-25 | 2013-03-27 | 中国科学院半导体研究所 | LUT4 (look up table), logical unit of FPGA (field programmed gate array) and logical block of FPGA |
| CN105634468A (en) * | 2014-10-30 | 2016-06-01 | 京微雅格（北京）科技有限公司 | FPGA layout method and macro element |
| CN105634468B (en) * | 2014-10-30 | 2018-11-06 | 京微雅格（北京）科技有限公司 | A kind of wiring method and macroelement of FPGA |
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