CN101295651A - Semiconductor device and its manufacturing method - Google Patents
Semiconductor device and its manufacturing method Download PDFInfo
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- CN101295651A CN101295651A CNA2007101047522A CN200710104752A CN101295651A CN 101295651 A CN101295651 A CN 101295651A CN A2007101047522 A CNA2007101047522 A CN A2007101047522A CN 200710104752 A CN200710104752 A CN 200710104752A CN 101295651 A CN101295651 A CN 101295651A
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/93—Batch processes
- H01L2224/94—Batch processes at wafer-level, i.e. with connecting carried out on a wafer comprising a plurality of undiced individual devices
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
- H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
- H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
- H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
- H01L2225/06503—Stacked arrangements of devices
- H01L2225/06555—Geometry of the stack, e.g. form of the devices, geometry to facilitate stacking
- H01L2225/06562—Geometry of the stack, e.g. form of the devices, geometry to facilitate stacking at least one device in the stack being rotated or offset
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Abstract
A semiconductor device and a manufacture method thereof provide a wafer which is provided with a plurality of chips; a plurality of welding pads are arranged on the passive surfaces of each chip; first metal layers that are electrically connected with each other are formed between the welding pads of neighboring chips after confirming the quality of each chip; cutting is carried out between each chip for separating each chip so as to connect and arrange the excellent chips on a bearing plate the surface of which is provided with a plurality of conductive lines by an interval mode; the chips are covered at one end of the conductive lines; besides, the conductive lines are exposed on the clearances of the chips; then dielectric layers are filled between the clearances of the chips; besides, a plurality of cuts which expose the conductive line part are formed corresponding to the dielectric layers surrounding each chip; second metal layers are formed on the cuts of the dielectric layers and the first metal layers so as to electrically connect the welding blocks of each chip to the conductive lines by the first metal layers and the second metal layers; besides, cutting is carried out along the dielectric layers between the chips and the bearing plate is removed so as to separate the chips and lead the conductive lines to be exposed on the non-passive surfaces of the chips.
Description
Technical field
The present invention relates to a kind of semiconductor device and method for making thereof, particularly relate to a kind of semiconductor device and method for making thereof for vertical stacking.
Background technology
Because communication, network, and the becoming more and more important of various Portable (Portable) electronic product such as computer and the compact trend of peripheral product thereof, and described electronic product develops towards multi-functional and high performance direction, to satisfy the package requirements of the high integration of semiconductor package part (Integration) and microminiaturized (Miniaturization), and for asking the performance (ability) that promotes single semiconductor package part and capacity (capacity) to meet miniaturization of electronic products, the trend of big capacity and high speed, prior art is with semiconductor package part multi-chip moduleization (Multichip Module; MCM) form presents, to connect the chip of putting more than at least two on the substrate (as substrate or lead frame) of single packaging part.
See also Fig. 1, promptly show the multi-chip semiconductor package that a prior art is arranged in the horizontal interval mode.As shown in the figure, this semiconductor package part includes a substrate 100; One first chip 110 has relative active surface 110a and non-active surface 110b, and its non-active surface 110b gluing is to this substrate 100, and with first lead 120 the active surface 110a of this first chip 110 is electrically connected to this substrate 100; And one second chip 140, have relative active surface 140a and non-active surface 140b, its non-active surface 140b gluing is to this substrate 100 and the distance certain with this first street, with second lead 150 the active surface 140a of this second chip 140 is electrically connected to this substrate 100 again.
The major defect of above-mentioned prior art multi-chip semiconductor package is to avoiding the lead false touch of chip chamber, must come respectively this chip of gluing with certain interval, so if need a plurality of chip of gluing then to need to lay large-area chip connecting area territory (Die Attachment Area) to be installed with the chip of requirement on substrate, this measure will cause the increase of cost and can't satisfy compact demand.
See also Fig. 2, be to show prior art such as United States Patent (USP) the 6th, 538, No. 331 exposure are spliced first chip 210 and second chip 240 on substrate 200 with folded crystal type (Stacked), while is this relative lower floor of chip that splices chip off normal (off-set) segment distance respectively, sets bonding wire 220,250 respectively to this substrate 200 to make things convenient for this first and second chip 210,240.
Though the technology that the method can be more aforementioned be arranged the multicore sheet in the horizontal interval mode is saved substrate space, but it still must utilize wire soldering technology to electrically connect chip and substrate, make between chip and substrate and to electrically connect quality and be subject to the line length influence of bonding wire and cause electrically not good, simultaneously because those chips must be offset a segment distance when piling up, and add that bonding wire is provided with the influence in space, still may cause chip-stacked area excessive and can't hold more multicore sheet.
For this reason, U.S. Pat 6,642,081,5,270,261 and 6,809,421 disclose and a kind ofly to utilize the silicon through electrode (Through Silicon Via, TSV) technology is able to vertical stacking for a plurality of semiconductor chips and electrically connects mutually.But its manufacture process too complexity and cost is too high, therefore is short of the industry practical value.
In addition, United States Patent (USP) the 5th, 716,759,6,040,235,5,455,455,6,646,289,6,777,767 grades then disclose and a kind ofly go up relatively, lower surface is provided with the chip of conducting wire, and it is the self-contained non-active surface formation of the wafer cutting notch that a plurality of chips are arranged, and utilize sputter (sputtering) technology to reshuffle layer (Redistribution Layer with circuit, RDL) mode forms extremely electrically conducting of non-active surface of chip active surface weld pad, but it is owing to be from the non-active surface of this wafer (back side) formation cutting notch relation, so be difficult for aligning to the tram, cause follow-up place on line deviation can't correctly reach effective electric connection chip active surface and non-active surface, even damage chip; In addition, (Redistribution Layer, RDL) technology cause the manufacture process cost to increase and the complexity raising because of repeatedly using circuit to reshuffle layer in this manufacture process; Moreover, because of this manufacture process is directly to carry out, therefore not considering chip defective products problem on a wafer, even if so will cause having the defective products chip in this wafer, still must continue to carry out manufacture process, cause waste of material and cost to increase problem.
Be with, how to solve above-mentioned prior art semiconductor device problem, and develop and a kind ofly do not increase area and can effectively in packaging part, integrate more the multicore sheet to promote electrical functionality, it is electrically not good to avoid using wire soldering technology to cause simultaneously, with too complexity and cost are too high because of using silicon through electrode (TSV) and repeatedly using sputter manufacture process that technology causes, and directly on wafer, make institute and do not consider problems such as chip non-defective unit, real in desiring most ardently the problem of solution at present.
Summary of the invention
The shortcoming of background technology the purpose of this invention is to provide a kind of semiconductor device and method for making thereof in view of the above, is able under the situation that does not increase area, integrates more chip in packaging part.
Another object of the present invention provides a kind of semiconductor device and method for making thereof, thereby can easier mode make, and avoids repeatedly using sputter manufacture process that operation causes too complexity and the too high problem of cost.
A further object of the present invention provides a kind of semiconductor device and method for making thereof, and it can supply a plurality of semiconductor chip vertical stackings and electric connection, avoids using wire soldering technology to cause electrically not good problem.
Another object of the present invention provides a kind of semiconductor device and method for making thereof, and it can supply a plurality of semiconductor chip vertical stackings and electric connection, avoids using silicon through electrode (TSV) to cause manufacture process too complexity and the too high problem of cost.
Another purpose of the present invention provides a kind of semiconductor device and method for making thereof, can guarantee that employed chip is the non-defective unit chip.
A multiple purpose of the present invention provides a kind of low cost and easy semiconductor device of manufacture process and method for making thereof.
Of the present invention time a purpose provides a kind of semiconductor device and method for making thereof, avoids forming the cutting notch in wafer rear and easily causes the chip problem of damaging.
For reaching above-mentioned and other purpose, the invention provides a kind of method for making of semiconductor device, comprise: a wafer with a plurality of chips is provided, this chip and wafer have relative active surface and non-active surface, respectively this chip active surface is provided with a plurality of weld pads, after tested (chip probing, CP) confirm that respectively this chip is good corrupt after, between the weld pad of adjacent chips, be formed with the first metal layer of mutual electric connection; The non-active surface of this wafer of thinning, and be attached on the film and separate respectively this chip to cut along this chip chamber respectively; Those chips that are defined as good chip are connect on the loading plate that places a surface to be provided with a plurality of conducting wires to leave the gap mode each other,, and make this conducting wire be revealed in this chip gap so that this chip covers an end of this conducting wire; In this chip gap, fill a dielectric layer, and the dielectric layer around corresponding each chip forms a plurality of openings, to expose outside this conducting wire part; On those chips and dielectric layer, cover a resistance layer, and make this resistance layer be formed with opening to expose outside respectively on this chip the first metal layer to the dielectric layer opening part; In this dielectric layer opening and this resistance layer opening, form second metal level, be electrically connected to this conducting wire by this first metal layer and second metal level for this chip pad respectively; Remove this resistance layer, and cut and remove this loading plate, use respectively this chip of separation, and make this conducting wire expose to the non-active surface of this chip, to constitute semiconductor device of the present invention along the dielectric layer of those chip chambers.
Follow-uply the semiconductor device can be utilized the conducting wire of exposing on the non-active surface of its chip to pile up and be electrically connected to second metal level on second half conductor means active surface, use the stacked structure that constitutes the multicore sheet.
Those connect the good chip (Good Die) of chip for having confirmed that places on the loading plate, and respectively this good chip connects by a following layer and places on this loading plate.This first metal layer utilizes circuit to reshuffle layer, and (Redistribution Layer, RDL) technology and forming on this wafer active surface corresponding between adjacent chips is used the weld pad that electrically connects adjacent chips.This loading plate is a metallic plate, in this dielectric layer opening and this resistance layer opening, to form second metal level that electrically connects this chip the first metal layer and conducting wire by plating mode, and then making weld pad on this chip active surface be able to be electrically connected to conducting wire on the non-active surface of this chip by this first metal layer, second metal level, this second metal level comprises copper/nickel/soldering tin material.
Can after forming second metal level and removing resistance layer, on this wafer active surface and this metal level, cover an insulating barrier again in addition, then this loading plate be removed, with form a slim chip scale semiconductor device (Chip Scale Package, CSP).Moreover, can plant conducting element in the conducting wire on the non-active surface of this chip, be electrically connected to external device (ED) or directly carry out piling up between semiconductor device for this conducting element of later use.
Moreover, when utilizing circuit to reshuffle layer (RDL) technology formation the first metal layer, this the first metal layer is extended by this weld pad and towards chip center to distribute, and be formed with in this first metal layer extension terminal and extend pad, so can on this extension pad, pile up, connect and put different electronic components for follow-up.
By aforementioned method for making, the present invention also provides a kind of semiconductor device, comprising: chip, this chip have relative active surface and non-active surface, and this active surface is provided with a plurality of weld pads, are formed with the first metal layer to the active surface edge on this weld pad; The conducting wire is formed on the non-active surface of this chip; Dielectric layer is covered in this sides of chip, and is formed with opening in this dielectric layer to manifest this conducting wire part; And second metal level, be formed on this dielectric layer opening and the first metal layer, be electrically connected to the conducting wire for chip pad by this first and second metal level.In addition, be formed with following layer again between the non-active surface of this chip and this conducting wire, and this conducting wire is located at this following layer edge relatively.
This semiconductor device includes the insulating barrier that is covered on this chip active surface and this second metal level again; And plant in the electric conducting material of this conducting wire outer surface, to form a slim chip scale semiconductor device (CSP).
That is, semiconductor device of the present invention and method for making thereof, mainly provide loading plate and a plurality of chip that is provided with the first metal layer that is electrically connected to weld pad in the active surface edge that a surface is provided with a plurality of conducting wires, those chips are connect an end that places on this loading plate and cover this conducting wire, and make the conducting wire be revealed in those chip gaps relatively, wherein those chips are to have confirmed as good chip, avoid prior art directly on wafer, to make and do not consider that chip defective products waste of material that problem causes and cost increase problem, then in those chip gaps, fill a dielectric layer, and the dielectric layer around corresponding each chip forms a plurality of openings, to expose outside this conducting wire part, and in those chips and dielectric layer surface coverage one resistance layer, and make this resistance layer be formed with opening to expose outside respectively on this chip pad the first metal layer to the dielectric layer opening part, utilize plating mode in this dielectric layer opening and this resistance layer opening, to form second metal level again, be electrically connected to this conducting wire for this chip pad by this first and second metal level, avoid prior art repeatedly to use manufacture process that sputter process causes too complexity and the too high problem of cost, remove this resistance layer afterwards, and cut and remove this loading plate along the dielectric layer of those chip chambers, use respectively this chip of separation, and make this conducting wire expose to the non-active surface of this chip, to form semiconductor device of the present invention by low cost and summary procedure.
Follow-up, one this semiconductor device can be connect and puts and be electrically connected on the chip bearing member to expose to conducting wire on the non-active surface of chip, and the conducting wire that second half conductor means utilization is exposed on the non-active surface of chip connects second metal level of putting and being electrically connected on this previous semiconductor device chips active surface, use the stacked structure that constitutes the multicore sheet, thereby can carry out vertical stacking under the area situation not increasing to pile up, to effectively integrate more multicore sheet, promote electrical functionality, avoid using wire soldering technology to cause electrically not good simultaneously and problems such as use silicon through electrode (TSV) institute's complicate fabrication process that causes and cost height.
Description of drawings
The multi-chip semiconductor package generalized section that Fig. 1 arranges in the horizontal interval mode for prior art;
Fig. 2 is a United States Patent (USP) the 6th, 538, and that is disclosed for No. 331 carries out the semiconductor package part generalized section of multi-chip stacking in folded brilliant (Stacked) mode;
Fig. 3 A to Fig. 3 G is the generalized section of semiconductor device of the present invention and method for making first embodiment thereof;
Fig. 3 D ' is a corresponding diagram 3D partial enlarged drawing;
Fig. 4 piles up schematic diagram for the semiconductor device of first embodiment of the invention;
Fig. 5 A and Fig. 5 B are the generalized section of semiconductor device of the present invention and method for making second embodiment thereof;
Fig. 6 piles up schematic diagram for the semiconductor device of second embodiment of the invention;
Fig. 7 A to Fig. 7 E is the schematic diagram of semiconductor device of the present invention and method for making the 3rd embodiment thereof; And
Fig. 8 piles up the schematic diagram of electronic component for the semiconductor device of third embodiment of the invention.
The component symbol explanation
100 substrates
110 first chips
The 110a active surface
The non-active surface of 110b
120 bonding wires
140 second chips
The 140a active surface
The non-active surface of 140b
150 bonding wires
200 substrates
210 first chips
220 bonding wires
240 second chips
250 bonding wires
30 chips
The 30a active surface
The non-active surface of 30b
300 wafers
301 weld pads
302 the first metal layers
303 gaps
304 extend pad
31 loading plates
310 conducting wires
32 films
34 following layers
35 dielectric layers
350 dielectric layer openings
36 resistance layers
360 resistance layer openings
37 second metal levels
371 bronze medals
372 nickel
373 scolding tin
38 insulating barriers
380 insulating barrier openings
39 conducting elements
40 electronic components
Embodiment
Below by particular specific embodiment explanation embodiments of the present invention, those skilled in the art can understand other advantage of the present invention and effect easily by the content that this specification disclosed.
First embodiment
See also Fig. 3 A to Fig. 3 G, be the schematic diagram of semiconductor device of the present invention and method for making first embodiment thereof.
Shown in Fig. 3 A and Fig. 3 B, one wafer 300 with a plurality of chips 30 is provided, this chip 30 and wafer 300 have relative active surface 30a and non-active surface 30b, respectively this chip active surface is provided with a plurality of weld pads 301, (chip probing after tested, CP) confirm that respectively this chip is good corrupt after, utilize circuit to reshuffle layer (RDL) technology between the weld pad of adjacent chips, to be formed with the first metal layer 302 of mutual electric connection.This first metal layer 302 for example is a welding block bottom metal layers (UBM), and its material can be titanium/copper/nickel (Ti/Cu/Ni), titanizing tungsten/gold (TiW/Au), aluminium/nickel vanadium/copper (Al/NiV/Cu), titanium/nickel vanadium/copper (Ti/NiV/Cu), titanizing tungsten/nickel (TiW/Ni), titanium/copper/copper (Ti/Cu/Cu), titanium/copper/copper/nickel (Ti/Cu/Cu/Ni) etc.
Then the non-active surface of this wafer of thinning places on the film 32 so that this wafer is connect by its non-active surface to 25-100 μ m, cuts and separates respectively this chip 30 along 30 of this chips respectively again, so that good chip 30 (Good Die) is taken out.
Shown in Fig. 3 C, with good chip 30 with its non-active surface and a following layer 34 and engaging at interval with this loading plate 31, wherein those chips 30 leave gap 303 each other, covering an end of this conducting wire 310, and make this conducting wire 310 be revealed in those chip gaps 303 relatively.The material of this following layer 34 for example is the epoxy resin (epoxy) of B stage (B-stage).
This loading plate 31 for example is the metallic plate of copper product, and to form a plurality of conducting wires 310 by plating mode in its surface, this conducting wire 310 for example is gold/nickel/gold (Au/Ni/Au), the about 0.5-3 μ of its thickness m.
Shown in Fig. 3 D and Fig. 3 D ', wherein this Fig. 3 D ' is a corresponding diagram 3D partial enlarged drawing, in the gap 303 of those chips 30, fill dielectric layer 35 just like epoxy resin (Epoxy) or pi (Polyimide), and the dielectric layer 35 around corresponding each chip 30 utilizes modes such as laser or etching to form a plurality of openings 350, to expose outside this conducting wire 310 parts.This dielectric layer opening 350 keeps one at interval with chip 30 sides, so that dielectric layer 35 is covered in this chip 30 sides, wherein this dielectric layer 35 that is covered in sides of chip mainly is the insulation usefulness for the metal level of follow-up formation.
Shown in Fig. 3 E, on those chips 30 and dielectric layer 35, cover resistance layer 36, and make this resistance layer 36 be formed with opening 360 to expose outside respectively on this chip 30 the first metal layer 302 to dielectric layer opening 350 parts just like dry film (Dry-film).
Shown in Fig. 3 F, utilize this metal material loading plate 31 and on conducting wire 310, with deposition second metal level 37 by plating mode and in this dielectric layer opening 350 and this resistance layer opening 360, be electrically connected to this conducting wire 310 by this first metal layer 302 and second metal level 37 for this chip pad 301 respectively.This second metal level 37 comprises copper (Cu) 371/ nickel (Ni) 372/ scolding tin (Solder) 373, it is that first deposited copper 371 is in this dielectric layer opening 350, and after covering the first metal layer 302 on this dielectric layer 30 and the chip active surface, continue nickel deposited 372 and scolding tin 373 on this copper 371 again.
Shown in Fig. 3 G, remove this resistance layer 36, and cut and utilize the loading plate 31 that removes this metal material as etching mode along the dielectric layer 35 of 30 of those chips, use respectively this chip 30 of separation, and make this conducting wire 310 expose to this chip 30 non-active surfaces, to constitute semiconductor device of the present invention.
By aforementioned method for making, the present invention also provides a kind of semiconductor device, includes: chip 30, this chip have relative active surface and non-active surface, and this active surface is provided with a plurality of weld pads 301, is formed with the first metal layer 302 to the active surface edge on this weld pad 301; Conducting wire 310 is formed on the non-active surface of this chip; Dielectric layer 35 is covered in this chip 30 sides, and is formed with opening 350 in this dielectric layer 35 to manifest this conducting wire part; And second metal level 37, be formed at this dielectric layer and open on 350 mouthfuls and the first metal layer 302, be electrically connected to conducting wire 310 for chip pad 01 by this first and second metal level 302,37.In addition, these chip 30 non-active surfaces and 310 of this conducting wires are formed with following layer 34 again, and this conducting wire 310 is located at this following layer 34 edges relatively.
See also Fig. 4 again, follow-uply aforementioned at least two semiconductor devices can be carried out vertical stacking, to utilize hot pressing (thermal compression) mode, and make the soldering tin material in second metal level 37 of semiconductor device chips 30 active surfaces be heat-fused in conducting wire 310 on second half conductor means chips 30 non-active surfaces, use the stacked structure that constitutes the multicore sheet.In addition, also can in this stacked structure, the filling of two semiconductor device gaps cover brilliant bottom filler (underfill) material (not shown) to strengthen this zygosity each other.
Second embodiment
See also Fig. 5 A and Fig. 5 B, be the schematic diagram of semiconductor device of the present invention and method for making second embodiment thereof.For simplifying this diagram, corresponding aforementioned same or analogous element adopts same numeral to represent in the present embodiment simultaneously.
Shown in Fig. 5 A, the semiconductor device of present embodiment and method for making thereof and previous embodiment are roughly the same, main difference is to form second metal level 37, and after removing resistance layer, cover an insulating barrier 38 on those chip 30 active surfaces and this second metal level 37, the material of this insulating barrier 38 is as epoxy resin etc.Then by etching mode loading plate is removed again, and cut to separate respectively this chip, to form slim chip scale semiconductor device (CSP) along the dielectric layer 35 in those chip gaps.
Shown in Fig. 5 B, can plant conducting element 39 in addition in the conducting wire 310 on these chip 30 non-active surfaces as soldered ball, be electrically connected to external device (ED) for this conducting element 39 of later use.
See also Fig. 6 again, also maybe the insulating barrier 38 on the aforesaid semiconductor device can be formed with the opening 380 that exposes this second metal level 37, and utilize to plant in second half conductor means to be electrically connected on second metal level 37 that exposes to insulating barrier opening 380, to form the stacked structure (package on package) of semiconductor device in the conducting element on the conducting wire 310 39.
The 3rd embodiment
See also Fig. 7 A to Fig. 7 E, be the schematic diagram of semiconductor device of the present invention and method for making the 3rd embodiment thereof.For simplifying this diagram, corresponding aforementioned same or analogous element adopts same numeral to represent in the present embodiment simultaneously.
Shown in Fig. 7 A, the semiconductor device of present embodiment and method for making thereof and previous embodiment are roughly the same, main difference is to utilize circuit to reshuffle layer (RDL) technology when forming the first metal layer 302 on chip 30 active surfaces, this the first metal layer 302 is extended by this weld pad 301 and towards chip 30 centers distribute, and be formed with extension pad 304 in these the first metal layer 30 extension terminals.
Shown in Fig. 7 B, thereafter manufacture process is that the phase class is in described in the previous embodiment, those chips 30 are connect on the loading plate 31 that places the surface to be provided with a plurality of conducting wires 310 to leave gap 303 modes each other, so that this chip 30 covers an end of this conducting wire 310, and make this conducting wire 310 be revealed in this chip gap 303.
Shown in Fig. 7 C, in those chip 30 gaps, fill a dielectric layer 35, and a plurality of openings 350 of dielectric layer 35 formation around corresponding each chip 30, to expose outside this conducting wire 310 parts.
Then on those chips 30 and dielectric layer 35, cover a resistance layer 36, and make this resistance layer 36 be formed with opening 360 to expose outside respectively on this chip 30 the first metal layer 302 to dielectric layer opening 350 parts and this extension pad 304.
Shown in Fig. 7 D, in this dielectric layer opening 350 and expose outside the first metal layer 302 of this resistance layer opening 360 and extend and form second metal level 307 that for example includes copper 371/ nickel 372/ scolding tin 373 on the pad 304, be electrically connected to this conducting wire 310 for this chip pad 301 respectively by this first metal layer 302 and second metal level 37, on the extension pad 304 of these chip active surface the first metal layer 302 terminals, be formed with second metal level 37 simultaneously.Be removable this resistance layer afterwards.
Shown in Fig. 7 E, cut and remove this loading plate 31 along the dielectric layer 35 of 30 of those chips, use respectively this chip 30 of separation, and make this conducting wire 310 expose to this chip 30 non-active surfaces, to constitute semiconductor device of the present invention.
See also Fig. 8 again, on these chip 30 active surfaces and this second metal level 37, can cover an insulating barrier 38,38 pairs of this insulating barriers should extend pad 304 positions and be formed with opening 380 to expose outside second metal level 37 on this extension pad 304, thereby for follow-up on second metal level of this extension pad, pile up to connect put different electronic component 40, and the conducting wire 310 on these chip 30 non-active surfaces plants the conducting element 39 as soldered ball, is electrically connected to external device (ED) for this conducting element 39 of later use.
Therefore, semiconductor device of the present invention and method for making thereof, mainly provide loading plate and a plurality of chip that is provided with the first metal layer that is electrically connected to weld pad in the active surface edge that a surface is provided with a plurality of conducting wires, those chips are connect an end that places on this loading plate and cover this conducting wire, and make the conducting wire be revealed in those chip gaps relatively, wherein those chips are to have confirmed as good chip, avoid prior art directly on wafer, to make and do not consider that chip defective products waste of material that problem causes and cost increase problem, then in those chip gaps, fill a dielectric layer, and the dielectric layer around corresponding each chip forms a plurality of openings, to expose outside this conducting wire part, and in those chips and dielectric layer surface coverage one resistance layer, and make this resistance layer be formed with opening to expose outside respectively on this chip pad the first metal layer to the dielectric layer opening part, utilize plating mode in this dielectric layer opening and this resistance layer opening, to form second metal level again, be electrically connected to this conducting wire for this chip pad by this first and second metal level, avoid prior art repeatedly to use manufacture process that sputter process causes too complexity and the too high problem of cost, remove this resistance layer afterwards, and cut and remove this loading plate along the dielectric layer of those chip chambers, use respectively this chip of separation, and make this conducting wire expose to the non-active surface of this chip, to form semiconductor device of the present invention by low cost and summary procedure.Follow-up, one this semiconductor device can be connect and puts and be electrically connected on the chip bearing member to expose to conducting wire on the non-active surface of chip, and the conducting wire that second half conductor means utilization is exposed on the non-active surface of chip connects second metal level of putting and being electrically connected on this previous semiconductor device chips active surface, use the stacked structure that constitutes the multicore sheet, thereby can carry out vertical stacking under the area situation not increasing to pile up, to effectively integrate more multicore sheet, promote electrical functionality, avoid using wire soldering technology to cause electrically not good simultaneously and problems such as use silicon through electrode (TSV) institute's complicate fabrication process that causes and cost height.
Above-described specific embodiment, only release characteristics of the present invention and effect in order to example, but not in order to limit the category of implementing of the present invention, do not breaking away under above-mentioned spirit of the present invention and the technology category, the disclosed content of any utilization and the equivalence finished changes and modify, the scope that all still should be the application's claims contains.
Claims (28)
1. the method for making of a semiconductor device comprises:
One wafer with a plurality of chips is provided, this chip and wafer have relative active surface and non-active surface, respectively this chip active surface is provided with a plurality of weld pads, confirm after tested that respectively this chip is good corrupt after, between the weld pad of adjacent chips, be formed with the first metal layer of mutual electric connection;
Cut and separate respectively this chip along this chip chamber respectively, so that those chips are connect on the loading plate that places a surface to be provided with a plurality of conducting wires to leave the gap mode each other, and make this chip cover an end of this conducting wire, and make this conducting wire be revealed in this chip gap;
In this chip gap, fill a dielectric layer, and the dielectric layer around corresponding each chip forms a plurality of openings, to expose outside this conducting wire part;
On those chips and dielectric layer, cover a resistance layer, and make this resistance layer be formed with opening to expose outside respectively on this chip the first metal layer to the dielectric layer opening part;
In this dielectric layer opening and this resistance layer opening, form second metal level, be electrically connected to this conducting wire by this first metal layer and second metal level for this chip pad respectively; And
Remove this resistance layer, and cut and remove this loading plate, use respectively this chip of separation, and make this conducting wire expose to the non-active surface of this chip, to constitute semiconductor device of the present invention along the dielectric layer of those chip chambers.
2. the method for making of semiconductor device according to claim 1, wherein, this loading plate is a metallic plate, to form a plurality of conducting wires by plating mode in its surface, this conducting wire is gold/nickel/gold.
3. the method for making of semiconductor device according to claim 1, wherein, this the first metal layer is to utilize circuit to reshuffle layer technology to form the welding block bottom metal layers on the wafer active surface, use the weld pad that electrically connects adjacent chips, and this wafer is that the chip through thinning and this cutting is through confirming as good chip, placing on the loading plate for connecing.
4. the method for making of semiconductor device according to claim 1, wherein, this street one following layer and engaging with this loading plate.
5. the method for making of semiconductor device according to claim 1, wherein, this dielectric layer is wherein one of epoxy resin and a pi, this resistance layer is a dry film.
6. the method for making of semiconductor device according to claim 1, wherein, dielectric layer around this chip is to utilize a laser and an etched wherein mode to form a plurality of openings, to expose outside this conducting wire part, and this dielectric layer opening and sides of chip keep one at interval, supply the insulation of the metal level of follow-up formation to use so that dielectric layer is covered in this sides of chip.
7. the method for making of semiconductor device according to claim 1, wherein, this second metal level comprises copper/nickel/scolding tin, it is the loading plate that utilizes metal material, first deposited copper is in this dielectric layer opening to pass through plating mode, and after covering this dielectric layer and the first metal layer, continue nickel deposited and scolding tin on this copper again.
8. the method for making of semiconductor device according to claim 1, wherein, by the hot pressing mode,, use the stacked structure that constitutes the multicore sheet so that second metal level of semiconductor device chips active surface is electrically connected at conducting wire on the non-active surface of second half conductor means chips.
9. the method for making of semiconductor device according to claim 8, wherein, two semiconductor device gaps are filled with again and cover brilliant bottom filler material in this stacked structure.
10. the method for making of semiconductor device according to claim 1, wherein, after forming second metal level and removing resistance layer, the multiple insulating barrier that on those chip active surfaces and this second metal level, covers, remove this loading plate again and cut, to separate respectively this chip along the dielectric layer in those chip gaps.
11. the method for making of semiconductor device according to claim 10, wherein, the conducting wire outer surface on the non-moving face of this chip has planted conducting element.
12. the method for making of semiconductor device according to claim 11, wherein, this insulating barrier is formed with the opening that exposes this second metal level, is electrically connected on second metal level that exposes to this insulating barrier opening for planting in second half conductor means in the conducting element on the conducting wire.
13. the method for making of semiconductor device according to claim 1, wherein, this first metal layer extends distribution by this weld pad towards chip center, and is formed with the extension pad in this first metal layer extension terminal.
14. the method for making of semiconductor device according to claim 13, wherein, those chips connect on the loading plate that places the surface to be provided with a plurality of conducting wires to leave the gap mode each other, in those chip gaps, to fill dielectric layer, and the dielectric layer around corresponding each chip forms a plurality of openings, on those chips and dielectric layer, cover a resistance layer again, and make this resistance layer be formed with opening exposing outside respectively on this chip the first metal layer, with in this dielectric layer opening and expose outside the first metal layer of this resistance layer opening and extend upward formation second metal level of pad to dielectric layer opening part and this extensions pad.
15. the method for making of semiconductor device according to claim 14, wherein, cover an insulating barrier on this chip active surface and this second metal level, this insulating barrier is formed with opening to expose outside second metal level on this extension pad to extending the pad position place, thereby on second metal level of this extension pad, connect and put electronic component, and the conducting wire on the non-active surface of this chip plants conducting element.
16. a semiconductor device comprises:
Chip, this chip have relative active surface and non-active surface, and this active surface is provided with a plurality of weld pads, are formed with the first metal layer to the active surface edge on this weld pad;
The conducting wire is formed on the non-active surface of this chip;
Dielectric layer is covered in this sides of chip, and is formed with opening in this dielectric layer to manifest this conducting wire part; And
Second metal level is formed on this dielectric layer opening and the first metal layer, is electrically connected to the conducting wire for chip pad by this first and second metal level.
17. semiconductor device according to claim 16 wherein, be formed with following layer again between the non-active surface of this chip and this conducting wire, and this conducting wire is located at this following layer edge relatively.
18. semiconductor device according to claim 16, wherein, this conducting wire is gold/nickel/gold, this dielectric layer is wherein one of epoxy resin and a pi, this second metal level comprises copper/nickel/scolding tin, this copper is deposited in the dielectric layer opening earlier, and covers this dielectric layer and the first metal layer, again nickel deposited and scolding tin on this copper.
19. semiconductor device according to claim 16, wherein, this dielectric layer opening and sides of chip keep one at interval, so that dielectric layer is covered in this sides of chip, and use for the insulation of second metal level.
20. semiconductor device according to claim 16, wherein, second metal level of this semiconductor device chips active surface is electrically connected at conducting wire on the non-active surface of second half conductor means chips by the hot pressing mode, uses the stacked structure that constitutes the multicore sheet.
21. semiconductor device according to claim 20, wherein, two semiconductor device gaps are filled with again and cover brilliant bottom filler material in this stacked structure.
22. semiconductor device according to claim 16 includes insulating barrier again, is to be formed on this chip active surface and this second metal level.
23. semiconductor device according to claim 22 includes conducting element again, is the conducting wire outer surface that plants on the non-active surface of this chip.
24. semiconductor device according to claim 23, wherein, this insulating barrier is formed with the opening that exposes this second metal level, is electrically connected on second metal level that exposes to this insulating barrier opening for planting in second half conductor means in the conducting element on the conducting wire.
25. semiconductor device according to claim 16, wherein, this first metal layer is reshuffled the formed welding block bottom metal layers of layer technology for utilizing circuit, and this chip is through thinning and through confirming as good chip.
26. semiconductor device according to claim 16, wherein, this first metal layer extends distribution by this weld pad towards chip center, and is formed with the extension pad in this first metal layer extension terminal.
27. semiconductor device according to claim 26 wherein, is formed with second metal level on this extension pad.
28. semiconductor device according to claim 27, wherein, cover an insulating barrier on this chip active surface and this second metal level, this insulating barrier is formed with opening to expose outside second metal level on this extension pad to extending the pad position place, thereby on second metal level of this extension pad, connect and put electronic component, and the conducting wire on the non-active surface of this chip plants conducting element.
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| CNA2007101047522A CN101295651A (en) | 2007-04-26 | 2007-04-26 | Semiconductor device and its manufacturing method |
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103199071A (en) * | 2013-03-29 | 2013-07-10 | 日月光半导体制造股份有限公司 | Stacking type packaging structure and manufacturing method thereof |
| CN105702658A (en) * | 2014-11-12 | 2016-06-22 | 矽品精密工业股份有限公司 | Semiconductor package and fabrication method thereof |
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2007
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103199071A (en) * | 2013-03-29 | 2013-07-10 | 日月光半导体制造股份有限公司 | Stacking type packaging structure and manufacturing method thereof |
| CN105702658A (en) * | 2014-11-12 | 2016-06-22 | 矽品精密工业股份有限公司 | Semiconductor package and fabrication method thereof |
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