CN101295095A - Semi-penetrating semi-reflective liquid crystal display device and manufacturing method thereof - Google Patents
Semi-penetrating semi-reflective liquid crystal display device and manufacturing method thereof Download PDFInfo
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- CN101295095A CN101295095A CNA2008101093629A CN200810109362A CN101295095A CN 101295095 A CN101295095 A CN 101295095A CN A2008101093629 A CNA2008101093629 A CN A2008101093629A CN 200810109362 A CN200810109362 A CN 200810109362A CN 101295095 A CN101295095 A CN 101295095A
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Abstract
The invention provides a transflective liquid crystal display panel and a manufacturing method thereof. The display panel comprises a substrate, a first polycrystalline silicon pattern arranged in a pixel reflecting area, a second polycrystalline silicon pattern arranged in a pixel peripheral area, insulating layers arranged on the first polycrystalline silicon pattern, the second polycrystalline silicon pattern and the substrate, a grid arranged on the insulating layer of the pixel reflecting area, a common electrode arranged on the insulating layer of the pixel peripheral area, a first interlayer dielectric layer arranged on the insulating layers, the grid and the common electrode, a reflecting electrode arranged on the first interlayer dielectric layer, a second interlayer dielectric layer arranged on the first interlayer dielectric layer and the reflecting electrode, and a penetrating electrode arranged on the second interlayer dielectric layer and electrically connected with the reflecting electrode by penetrating the opening of the second interlayer dielectric layer; a storing capacitance is formed by the second polycrystalline silicon pattern, the common electrode and the insulating layers between the second polycrystalline silicon pattern and the common electrode; the reflecting electrode is arranged above a thin film transistor so as to increase the area of the reflecting area; and the storing capacitance is arranged under a data line so as to promote the aperture ratio.
Description
Technical field
The invention relates to a kind of semi-penetrating and semi-reflective liquid crystal display panel and preparation method thereof, refer to a kind of high aperture and the simple semi-penetrating and semi-reflective liquid crystal display panel of technology and preparation method thereof especially.
Background technology
LCD is according to the source difference of illumination light, can divide into penetration, reflective, and three kinds of semi-penetration, semi-reflectives etc.Penetrating LCD needs in the back side of display panels the backlight module that is used for producing light to be set, and the light of its generation can allow the observer see that by anterior view the picture of LCD shows by display panels.Reflective liquid-crystal display is to use surround lighting as light source, and needs to be provided with in pixel region reflecting electrode; When reflective liquid-crystal display display frame, surround lighting is entered in the display panels and by reflecting electrode by the front (sightingpiston) of display panels light is reflected, and the observer can watch the picture of LCD to show by this.As for semi-penetrated semi-reflected liquid crystal display then is the LCD that has the pattern of penetrating and reflective-mode simultaneously, that is each pixel region of display panels all includes penetrating region and echo area, wherein penetrating region is to use backlight, and the echo area then is to use surround lighting as light source.
Please refer to Fig. 1.Fig. 1 is the synoptic diagram of known semi-penetrating and semi-reflective liquid crystal display panel.As shown in Figure 1, known semi-penetrating and semi-reflective liquid crystal display panel comprises substrate 10, and definition has echo area 12 and penetrating region 14 on it.Be provided with thin film transistor (TFT) in the echo area 12, it has semiconductor layer, and semiconductor layer comprises passage 16, source electrode 18, drain electrode 20, two slight doped-drain 21, gate insulator 22 and grid 24, wherein source electrode 18 and drain electrode 20 are arranged at the both sides of passage 16 respectively, two slight doped-drain 21 be arranged at respectively between source electrode 18 and the passage 16 and drain electrode 20 and passage 16 between, gate insulator 22 is covered on passage 16, source electrode 18 and the drain electrode 20, and grid 24 is arranged on the gate insulator 22 and respective channel 16.
Be coated with first interlayer dielectric layer 26 on gate insulator 22 and the grid 24, and first interlayer dielectric layer 26 gate insulator 22 corresponding with its below have two openings, expose source electrode 18 respectively and drain 20.First interlayer dielectric layer 26 is provided with data line 28 and drain electrode connection gasket 30, and wherein data line 28 is inserted in the opening of source electrode 18 tops and electrically connected with source electrode 18 by this, and drain electrode connection gasket 30 is then inserted drain electrode 20 top openings and electrically connected with drain electrode 20 by this.In echo area 12, be coated with second interlayer dielectric layer 32 on first interlayer dielectric layer 26, data line 28 and the drain electrode connection gasket 30, and second interlayer dielectric layer 32 has opening, expose drain electrode connection gasket 30.Second interlayer dielectric layer 32 and first interlayer dielectric layer 26 are provided with through electrode 34, wherein through electrode 34 is overlapped on the drain electrode connection gasket 30 by the opening of second interlayer dielectric layer 32, electrically connect with drain electrode 20 by this, and through electrode 34 extends to penetrating region 14.In addition, on the through electrode 34 of echo area 12, be coated with a reflecting electrode 36, and electrically connect with drain electrode 20 by through electrode 34 and drain electrode connection gasket 30.
Yet known semi-penetrating and semi-reflective liquid crystal display panel has following shortcoming.At first, known semi-penetrating and semi-reflective liquid crystal display panel must utilize at least eight road lithography process, define the pattern of semiconductor layer, source/drain, slight doped-drain, grid, first interlayer dielectric layer, data line and drain electrode connection gasket, second interlayer dielectric layer, through electrode and reflecting electrode respectively, so technology is comparatively complicated.In addition, because the echo area is provided with second interlayer dielectric layer, and penetrating region is not provided with second interlayer dielectric layer, make echo area and penetrating region have difference in height, and this difference in height easily causes the rub degree of difficulty of (rubbing) alignment pattern of follow-up brush, and in follow-up liquid crystal process, also can cause the degree of difficulty that liquid crystal gap (Cell Gap) is highly controlled and gap (spacer) is arranged.
Summary of the invention
One of purpose of the present invention is to propose a kind of semi-penetrating and semi-reflective liquid crystal display panel and preparation method thereof, to simplify the technology and the structure thereof of semi-penetrating and semi-reflective liquid crystal display panel.
For reaching above-mentioned purpose, the present invention proposes a kind of semi-penetrating and semi-reflective liquid crystal display panel, comprising: substrate, polysilicon layer, insulation course, ground floor metal, first interlayer dielectric layer, second layer metal, second interlayer dielectric layer, and through electrode.Substrate comprises echo area, penetrating region and surrounding zone.Polysilicon layer is arranged on the substrate, and polysilicon layer comprises that first poly-silicon pattern is arranged at the echo area, and second poly-silicon pattern is arranged at the surrounding zone, and wherein first poly-silicon pattern comprises passage, and source electrode and drain electrode are positioned at the both sides of passage.Insulation course is arranged on polysilicon layer and the substrate.The ground floor metal is arranged on the insulation course, and the ground floor metal comprises the grid respective channel, and common electrode is to should second poly-silicon pattern, and wherein second poly-silicon pattern, common electrode and insulation course therebetween constitute storage capacitors.First interlayer dielectric layer is arranged on insulation course and the ground floor metal, and first interlayer dielectric layer has two openings, exposes source electrode and drain electrode respectively.Second layer metal is arranged on first interlayer dielectric layer, second layer metal comprises reflecting electrode and data line, wherein reflecting electrode is arranged at the echo area and sees through the corresponding opening that drains of first interlayer dielectric layer and electrically connects with drain electrode, data line is arranged at the surrounding zone and extends to the echo area, and data line sees through the opening and the source electrode electric connection of the corresponding source electrode of first interlayer dielectric layer in the echo area.Second interlayer dielectric layer is arranged on first interlayer dielectric layer and the second layer metal, and second interlayer dielectric layer has an opening and exposes the part second layer metal.Through electrode is arranged on second interlayer dielectric layer, and through electrode is arranged at penetrating region and extends to the echo area and the intersection of penetrating region, and through electrode sees through opening and the reflecting electrode and the drain electrode electric connection of second interlayer dielectric layer.
For reaching above-mentioned purpose, the present invention provides a kind of method of making semi-penetrating and semi-reflective liquid crystal display panel in addition, comprising: substrate is provided, and on substrate, define the echo area, penetrating region and surrounding zone; On substrate, form polysilicon layer, and utilize the first road lithography process to form first poly-silicon pattern in the echo area, and form second poly-silicon pattern in the surrounding zone; Utilize the second road lithography process in first poly-silicon pattern, to form passage, and form source electrode and drain electrode, and on first poly-silicon pattern, second poly-silicon pattern and substrate, form insulation course in the both sides of passage; On insulation course, form the ground floor metal, and utilize the 3rd road lithography process to form the grid respective channel in the echo area, and in corresponding second poly-silicon pattern of surrounding zone formation common electrode, wherein passage, source electrode, drain electrode, insulation course and grid constitute a thin film transistor (TFT), and second poly-silicon pattern, common electrode and insulation course therebetween constitute storage capacitors; On insulation course and ground floor metal, form first interlayer dielectric layer, and utilize the 4th road lithography process in first interlayer dielectric layer, to form two openings, expose source electrode and drain electrode respectively; On first interlayer dielectric layer, form second layer metal, and utilize the 5th road lithography process to form reflecting electrode in the echo area, and in surrounding zone formation data line, and make data line partly extend to the echo area, wherein this reflecting electrode sees through the opening of the corresponding drain electrode of first interlayer dielectric layer and drains and electrically connects, and data line sees through the opening and the source electrode electric connection of the corresponding source electrode of first interlayer dielectric layer in the echo area; On first interlayer dielectric layer and second layer metal, form second interlayer dielectric layer, and utilize the 6th road lithography process in this second interlayer dielectric layer, to form an opening, expose the part second layer metal; And on second interlayer dielectric layer, form transparency conducting layer, and utilize the 7th road lithography process to form through electrode, through electrode is arranged at penetrating region and extends to the echo area and the intersection of penetrating region, and through electrode sees through opening and the reflecting electrode and the drain electrode electric connection of second interlayer dielectric layer.
Because method of the present invention only need be utilized seven road lithography process, can produce semi-penetrating and semi-reflective liquid crystal display panel, therefore can simplify technology.In addition, reflecting electrode of the present invention is arranged at the top of thin film transistor (TFT), therefore can increase the area of echo area.Moreover storage capacitors is arranged at the below of data line, therefore can promote aperture opening ratio.
Description of drawings
Fig. 1 is the synoptic diagram of known semi-penetrating and semi-reflective liquid crystal display panel.
Fig. 2 to Figure 17 is the method synoptic diagram of a preferred embodiment of making semi-penetrating and semi-reflective liquid crystal display panel of the present invention.
Figure 18 and Figure 19 are the top view and the diagrammatic cross-section of the semi-penetrating and semi-reflective liquid crystal display panel of another preferred embodiment of the present invention.
Figure 20 and Figure 21 are the top view and the diagrammatic cross-section of the semi-penetrating and semi-reflective liquid crystal display panel of the another preferred embodiment of the present invention.
Figure 22 is the synoptic diagram of periphery circuit region of the present invention.
Drawing reference numeral:
10 substrates, 12 echo areas
14 penetrating regions, 16 passages
20 drain electrodes of 18 source electrodes
21 slight doped-drain 22 gate insulators
24 grids, 26 first interlayer dielectric layers
28 data lines, 30 drain electrode connection gaskets
32 second interlayer dielectric layers, 34 through electrodes
36 reflecting electrodes, 50 substrates
51 cushions, 52 echo areas
54 penetrating regions, 56 surrounding zones
58 first poly-silicon patterns, 60 second poly-silicon patterns
62 passages, 63 slight doped-drain
66 drain electrodes of 64 source electrodes
68 insulation courses, 70 sweep traces
72 grids, 74 common electrodes
76 first interlayer dielectric layer 76A inorganic dielectric layer
The organic dielectric layer 76C of 76B sensitization contoured surface
76D opening 77 intermediate tone masks
78 reflecting electrode 78A reflecting electrode contoured surface
80 data lines, 82 second interlayer dielectric layers
82A opening 84 through electrodes
84A slit 86 transparent conductive patterns
86A slit 90CMOS transistor
92NMOS transistor 94PMOS transistor
Embodiment
For making those skilled in the art can further understand the present invention, hereinafter the spy enumerates several preferred embodiments of the present invention, and cooperate appended graphic, describe in detail constitution content of the present invention and the effect desiring to reach.
Please refer to Fig. 2 to Figure 17.Fig. 2 to Figure 17 is the method synoptic diagram of a preferred embodiment of making semi-penetrating and semi-reflective liquid crystal display panel of the present invention.For ease of explanation, only show a pixel region in graphic, and Fig. 2, Fig. 4, Fig. 6, Fig. 8, Figure 10, Figure 12, Figure 14 and Figure 16 are the top view of pixel region, and Fig. 3, Fig. 5, Fig. 7, Fig. 9, Figure 11, Figure 13, Figure 15 and Figure 17 are the diagrammatic cross-section of pixel region along hatching line AA ' and BB '.As Fig. 2 and shown in Figure 3, substrate 50 at first is provided, and on substrate 50, define echo area 52, penetrating region 54 and surrounding zone 56.Then optionally on substrate 50, form a cushion 51 (Fig. 2 does not show) earlier.Subsequently, on substrate 50, form polysilicon layer again, low-temperature polycrystalline silicon layer for example, and utilize the first road lithography process to cooperate etching technics 52 to form first poly-silicon pattern 58 in the echo area, and 56 form second poly-silicon pattern 60 in the surrounding zone, wherein first poly-silicon pattern 58 is used to make the semiconductor layer of thin film transistor (TFT), and second poly-silicon pattern 60 is as the bottom electrode of storage capacitors, and first poly-silicon pattern 58 and second poly-silicon pattern 60 are electric connection in present embodiment, but are not limited thereto.
As Fig. 4 and shown in Figure 5, utilize the second road lithography process to cooperate high concentration ion cloth to plant technology subsequently and carry out implanting ions in first poly-silicon pattern 58 and second poly-silicon pattern 60, wherein the mask pattern that part first poly-silicon pattern 58 forms by photoresistance in the second road lithography process (figure does not show) is stopped that formation is not mixed, the not doped region of first poly-silicon pattern 58 forms passage 62 by this, the doped region of passage 62 both sides then forms source electrode 64 and drain electrode 66, and second poly-silicon pattern 60 also can because of doping tool electric conductivity with bottom electrode as storage capacitors.The thin film transistor (TFT) of present embodiment can be N type or P type, so high concentration ion cloth is planted the admixture that uses and can optionally be P type or N type.Thin film transistor (TFT) that what deserves to be explained is present embodiment in addition designs for bigrid, so the layout of passage 62 is as shown in Figure 4, however application of the present invention be not limited thereto, and also can be the design of general single grid.
As Fig. 6 and shown in Figure 7, on first poly-silicon pattern 58, second poly-silicon pattern 60 and substrate 50, form insulation course 68 (Fig. 6 does not show) subsequently, wherein the insulation course 68 in passage 62 tops is the usefulness as gate insulator.In first poly-silicon pattern 58, form passage 62, and the step that forms source electrode 64 and drain electrode 66 in the both sides of passage 62, be not limited to prior to carrying out before the step that on first poly-silicon pattern 58, second poly-silicon pattern 60 and substrate 50, forms insulation course 68.In other words, also can on first poly-silicon pattern 58, second poly-silicon pattern 60 and substrate 50, after the formation insulation course 68, in first poly-silicon pattern 58, form passage 62 again, and form source electrode 64 and drain 66 earlier in the both sides of passage 62.Then on insulation course 68, form the ground floor metal again, and 52 formation sweep traces 70, grid 72 electrically connect and respective channel 62 with sweep trace 70 in the echo area to utilize one the 3rd road lithography process to cooperate etching technics, and 56 form common electrodes 74 corresponding second poly-silicon patterns 60 in the surrounding zone, wherein common electrode 74 also is the top electrode of storage capacitors, so second poly-silicon pattern 60, the common electrode 74 of surrounding zone 56 and be positioned at second poly-silicon pattern 60 and the insulation course of 74 of common electrodes 68 constitutes storage capacitors.
As Fig. 8 and shown in Figure 9, then carry out low concentration implanting ions technology, to form slight doped-drain 63.In the present embodiment, because the undersized of grid 72 in passage 62, therefore can directly be utilized grid 72 to form slight doped-drain 63 as shade by being doped in passage 62 both sides, and needn't use extra mask.
As Figure 10 and shown in Figure 11, then on insulation course 68 and ground floor metal, form first interlayer dielectric layer 76 (Figure 10 does not show), and in the echo area 52 first interlayer dielectric layer 76 forms contoured surface, in first interlayer dielectric layer 76 and following pairing insulation course 68 thereof, form two openings again, expose source electrode 64 and drain electrode 66 respectively.In present embodiment, first interlayer dielectric layer 76 includes for example silicon nitride of inorganic dielectric layer 76A, and the organic dielectric layer 76B of sensitization with sensitometric characteristic.In addition, in the present embodiment, the contoured surface 76C of first interlayer dielectric layer 76 and opening 76D use shadow tone (halftone) mask 77 by the 4th road lithography process and cooperate etching technics to form, its practice is as described below: at first carry out the 4th road lithography process, utilize intermediate tone mask 77 control exposures, make the zone of the organic dielectric layer 76B of the corresponding sensitization of semi-opaque region 77A of intermediate tone mask at desire formation contoured surface 76C, and the corresponding desire of the full photic zone 77B that makes intermediate tone mask forms the zone of opening 76D, thus because the regional exposure amount of desire formation contoured surface 76C is less, therefore behind exposure imaging, only can cause the effect of contoured surface 76C in the surface of the organic dielectric layer 76B of sensitization formation micro pattern, and on the other hand since desire she to form the exposure in zone of opening 76D bigger, the organic dielectric layer 76B of sensitization that therefore should the zone can all be removed behind exposure imaging and form opening 76D.Then carry out etching technics again, by opening 76D etching inorganic dielectric layer 76A and insulation course 68, until exposing source electrode 64 and drain electrode 66.
Present embodiment system utilizes intermediate tone mask to form the rough surperficial 76C of fluctuating and the opening 76D of first interlayer dielectric layer 76, is not limited to this and can utilizes alternate manner to reach yet the present invention makes the mode of contoured surface 76C and opening 76D.For instance, form contoured surface 76C and can utilize different masks to be formed respectively with the step of opening 76D, perhaps contoured surface 76C can utilize laser technology to be formed, and uses the exposure imaging mode to form and be not limited thereto.
As Figure 12 and shown in Figure 13, then on first interlayer dielectric layer 76, form a second layer metal (figure does not show), and utilize the 5th road lithography process to cooperate etching technics in echo area 52, to form reflecting electrode 78, and in surrounding zone 56, form data line 80, and make data line 80 parts extend to echo area 52, wherein reflecting electrode 78 is through the opening and drain electrode 66 electric connections of the 76 corresponding drain electrodes 66 of first interlayer dielectric layer, and 52 opening and the source electrodes 64 that then see through first interlayer dielectric layer, 76 corresponding source electrodes 64 electrically connect data line 80 in the echo area.In addition, because first interlayer dielectric layer 76 has contoured surface 76C in echo area 52, therefore the reflecting electrode 78 that therefore stacks thereon also has contoured surface 78A, and can allow reflection ray assemble, and reaches the effect that improves reflectivity.
As Figure 14 and shown in Figure 15, on first interlayer dielectric layer 76 and second layer metal, form second interlayer dielectric layer 82 subsequently, and utilize the 6th road lithography process to cooperate etching technics in second interlayer dielectric layer 82, to form an opening 82A, expose part second layer metal (edge of reflecting electrode 78).As Figure 16 and shown in Figure 17, on second interlayer dielectric layer 82, form a transparency conducting layer (figure does not show) at last, and utilize one the 7th road lithography process to cooperate etching technics to form through electrode 84, wherein through electrode 84 is arranged in the penetrating region 54 and extends to the intersection of echo area 52 and penetrating region 54, and through electrode 84 can see through opening and the reflecting electrode 78 of second interlayer dielectric layer 82 and 66 electric connections that drain by this.In addition, in present embodiment, through electrode 84 trims substantially with data line 80 and overlapping (as Figure 16 and shown in Figure 17), can avoid producing stray capacitance by this, but the present invention is not as limit, and through electrode 84 also can not overlap with data line 80 and not trim, or is different relative positions.
Above-mentioned for the present invention makes the preferred embodiment of the method and the structure thereof of semi-penetrating and semi-reflective liquid crystal display panel, however semi-penetrating and semi-reflective liquid crystal display panel of the present invention is not limited to this, and other different enforcement sample attitude can be arranged.Please refer to Figure 18 to Figure 21.Figure 18 and Figure 19 are the top view and the diagrammatic cross-section of the semi-penetrating and semi-reflective liquid crystal display panel of another preferred embodiment of the present invention, and Figure 20 and Figure 21 are the top view and the diagrammatic cross-section of the semi-penetrating and semi-reflective liquid crystal display panel of the another preferred embodiment of the present invention, wherein for ease of comparing the similarities and differences of each embodiment, in various embodiments of the present invention, similar elements is used same numeral, and no longer adds to give unnecessary details.
As Figure 18 and shown in Figure 19, different with previous embodiment be in, the semi-penetrating and semi-reflective liquid crystal display panel of present embodiment has the transparent conductive patterns 86 of float (floating) in addition, be positioned at the surface of second interlayer dielectric layer 82 of echo area 52, wherein transparent conductive patterns 86 is same transparency conducting layer with through electrode 84, and need not increase additional technique by the definition of the 7th road lithography process, but transparent conductive patterns 86 does not electrically connect with through electrode 84, and the effect of transparent conductive patterns 86 is to make echo area 52 consistent with the character of surface of penetrating region 54, for example highly consistent, to reduce the rub degree of difficulty of alignment pattern of follow-up brush.
As Figure 20 and shown in Figure 21, different with previous embodiment be in, the through electrode 84 of the semi-penetrating and semi-reflective liquid crystal display panel of present embodiment has many slit 84A, and transparent conductive patterns 86 also optionally has many slit 86A.The slit 84A of through electrode 84 and the slit 86A of transparent conductive patterns 86 all can define in the 7th road lithography process in the lump, need not increase additional technique, and the slit 86A of the slit 84A of through electrode 84 and transparent conductive patterns 86 can make liquid crystal molecule towards the different directions orientation, and is applied in the liquid crystal display panel with wide visual angle.
Please refer to Figure 22.Figure 22 is the synoptic diagram of periphery circuit region of the present invention.As shown in figure 22, the making of the control element of the periphery circuit region of present embodiment can with the process integration of the thin film transistor (TFT) of pixel region, and control element is that the CMOS transistor 90 that a nmos pass transistor 92 and PMOS transistor 94 are formed constitutes in present embodiment, yet application of the present invention is not limited to this, the also visual circuit design of control element and be single nmos pass transistor or single PMOS transistor.
In sum, method of the present invention only need use seven road lithography process can produce semi-penetrating and semi-reflective liquid crystal display panel, and is the design of single liquid crystal gap (single cell gap), therefore has the advantage of work simplification.In addition, first interlayer dielectric layer of the present invention comprises inorganic dielectric layer and organic dielectric layer, can reduce the coupling of lead crossover region (ground floor metal and second layer metal), reduce stray capacitance, and the organic dielectric layer of sensitization can pass through exposure imaging mode define pattern, so can reduce the burden of deposition and etching technics.Therefore moreover reflecting electrode is arranged at the top of thin film transistor (TFT), only is arranged at the practice in the capacitive region compared to known reflecting electrode, can increase the area of echo area.In addition, storage capacitors is arranged at the below of data line, therefore can promote aperture opening ratio.
The above only is preferred embodiment of the present invention, and all equalizations of doing according to claim of the present invention change and modify, and all should belong to covering scope of the present invention.
Claims (22)
1. a semi-penetrating and semi-reflective liquid crystal display panel is characterized in that, described semi-penetrating and semi-reflective liquid crystal display panel comprises:
One substrate comprises an echo area, a penetrating region and a surrounding zone;
One polysilicon layer, be arranged on the described substrate, described polysilicon layer comprises that one first poly-silicon pattern is arranged at described echo area, and one second poly-silicon pattern be arranged at described surrounding zone, wherein said first poly-silicon pattern comprises a passage, and one source pole and a drain electrode are positioned at the both sides of described passage;
One insulation course is arranged on described polysilicon layer and the described substrate;
One ground floor metal, be arranged on the described insulation course, described ground floor metal comprises the corresponding described passage of a grid, and corresponding described second poly-silicon pattern of a common electrode, and wherein said second poly-silicon pattern, described common electrode and described insulation course therebetween constitute a storage capacitors;
One first interlayer dielectric layer is arranged on described insulation course and the described ground floor metal, and described first interlayer dielectric layer has two openings, exposes described source electrode and described drain electrode respectively;
One second layer metal, be arranged on described first interlayer dielectric layer, described second layer metal comprises a reflecting electrode and a data line, wherein said reflecting electrode is arranged at described echo area and sees through the described opening and the described drain electrode electric connection of the corresponding described drain electrode of described first interlayer dielectric layer, described data line is arranged at described surrounding zone and extends to described echo area, and described data line sees through the described opening and the electric connection of described source electrode of the corresponding described source electrode of described first interlayer dielectric layer in described echo area;
One second interlayer dielectric layer is arranged on described first interlayer dielectric layer and the described second layer metal, and described second interlayer dielectric layer has an opening and exposes the described second layer metal of part; And
One through electrode, be arranged on described second interlayer dielectric layer, described through electrode is arranged at described penetrating region and extends to the intersection of described echo area and described penetrating region, and described through electrode sees through described opening and the described reflecting electrode and the described drain electrode electric connection of described second interlayer dielectric layer.
2. semi-penetrating and semi-reflective liquid crystal display panel as claimed in claim 1 is characterized in that, described first interlayer dielectric layer comprises an inorganic dielectric layer and the organic dielectric layer of a sensitization.
3. semi-penetrating and semi-reflective liquid crystal display panel as claimed in claim 1 is characterized in that, described second interlayer dielectric layer is the organic dielectric layer of a sensitization.
4. semi-penetrating and semi-reflective liquid crystal display panel as claimed in claim 1, it is characterized in that, described first interlayer dielectric layer has a fluctuating surface in described echo area, the described reflecting electrode that is arranged at by this on described first interlayer dielectric layer has a fluctuating surface.
5. semi-penetrating and semi-reflective liquid crystal display panel as claimed in claim 1 is characterized in that through electrode comprises the transparency conducting layer of floating in addition, is arranged at the surface of described second interlayer dielectric layer of described echo area.
6. semi-penetrating and semi-reflective liquid crystal display panel as claimed in claim 5 is characterized in that, the described transparency conducting layer of through electrode has many slits.
7. semi-penetrating and semi-reflective liquid crystal display panel as claimed in claim 1 is characterized in that described through electrode has many slits.
8. semi-penetrating and semi-reflective liquid crystal display panel as claimed in claim 1 is characterized in that, described through electrode and described data line trim substantially or do not overlap.
9. semi-penetrating and semi-reflective liquid crystal display panel as claimed in claim 1 is characterized in that, is provided with a cushion between described substrate and described polysilicon layer.
10. a method of making semi-penetrating and semi-reflective liquid crystal display panel is characterized in that, described method comprises:
One substrate is provided, and on described substrate, define an echo area, a penetrating region and a surrounding zone;
On described substrate, form a polysilicon layer, and utilize one first road lithography process to form one first poly-silicon pattern in described echo area, and form one second poly-silicon pattern in described surrounding zone;
Utilize one second road lithography process in described first poly-silicon pattern, to form a passage, and form an one source pole and a drain electrode in the both sides of described passage;
On described first poly-silicon pattern, described second poly-silicon pattern and described substrate, form an insulation course;
On described insulation course, form a ground floor metal, and utilize one the 3rd road lithography process to form the corresponding described passage of a grid in described echo area, and form corresponding described second poly-silicon pattern of a common electrode in described surrounding zone, wherein said passage, described source electrode, described drain electrode, described insulation course and described grid constitute a thin film transistor (TFT), and described second poly-silicon pattern, described common electrode and described insulation course therebetween constitute a storage capacitors;
On described insulation course and described ground floor metal, form one first interlayer dielectric layer, and utilize one the 4th road lithography process in described first interlayer dielectric layer, to form two openings, expose described source electrode and described drain electrode respectively;
On described first interlayer dielectric layer, form a second layer metal, and utilize one the 5th road lithography process to form a reflecting electrode in described echo area, and form a data line in described surrounding zone, and make described data line partly extend to described echo area, described opening and described drain electrode that wherein said reflecting electrode sees through the corresponding described drain electrode of described first interlayer dielectric layer electrically connect, and described opening and the described source electrode through the corresponding described source electrode of described first interlayer dielectric layer electrically connects and described data line is in described echo area;
On described first interlayer dielectric layer and described second layer metal, form one second interlayer dielectric layer, and utilize one the 6th road lithography process in described second interlayer dielectric layer, to form an opening, expose the described second layer metal of part; And
On described second interlayer dielectric layer, form a transparency conducting layer, and utilize one the 7th road lithography process to form a through electrode, described through electrode is arranged at described penetrating region and extends to the intersection of described echo area and described penetrating region, and described through electrode sees through described opening and the described reflecting electrode and the described drain electrode electric connection of described second interlayer dielectric layer.
11. method as claimed in claim 10 is characterized in that, the step that forms described first interlayer dielectric layer comprises:
Form an inorganic dielectric layer; And
On described inorganic dielectric layer, form the organic dielectric layer dielectric layer of a sensitization.
12. method as claimed in claim 11, it is characterized in that, utilizing described the 4th road lithography process in described first interlayer dielectric layer, to form in the step of described two openings, comprising that the organic dielectric layer of the described sensitization that utilizes a shadow tone mask to make described echo area in the lump forms a fluctuating surface.
13. method as claimed in claim 11 is characterized in that, described method comprises that in addition the organic dielectric layer of the described sensitization that utilizes another mask to make described echo area forms a fluctuating surface.
14. method as claimed in claim 10 is characterized in that, described method comprises that in addition described first interlayer dielectric layer that utilizes a laser technology to make described echo area forms a fluctuating surface.
15. method as claimed in claim 10 is characterized in that, in the step that forms described through electrode, other is included in and forms a transparent conductive patterns of floating in the described echo area.
16. method as claimed in claim 15 is characterized in that, in the step that forms described transparent conductive patterns, other is included in and forms many slits in the described transparent conductive patterns.
17. method as claimed in claim 10 is characterized in that, in the step that forms described through electrode, other is included in and forms many slits in the described through electrode.
18. method as claimed in claim 10 is characterized in that, described method comprises that in addition formation one cushion is between described substrate and described polysilicon layer.
19. method as claimed in claim 10, it is characterized in that, utilize the described second road lithography process in described first poly-silicon pattern, to form described passage, and the step that forms described source electrode and described drain electrode in the both sides of described passage, be prior on described first poly-silicon pattern, described second poly-silicon pattern and described substrate, forming the step of described insulation course.
20. method as claimed in claim 10, it is characterized in that, on described first poly-silicon pattern, described second poly-silicon pattern and described substrate, form the step of described insulation course, be prior to utilizing the described second road lithography process in described first poly-silicon pattern, to form described passage, and the step that forms described source electrode and described drain electrode in the both sides of described passage.
21. method as claimed in claim 10 is characterized in that, described substrate comprises a periphery circuit region in addition, and described method is contained in the step of making described thin film transistor (TFT) at least one control element of integration and making in described periphery circuit region in addition.
22. method as claimed in claim 21 is characterized in that, described control element comprises a nmos pass transistor, a PMOS transistor or a CMOS transistor.
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| Application Number | Priority Date | Filing Date | Title |
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| CN2008101093629A CN101295095B (en) | 2008-06-02 | 2008-06-02 | Semi-penetrating semi-reflective liquid crystal display device and manufacturing method thereof |
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| CN101661176A (en) * | 2008-08-29 | 2010-03-03 | 精工爱普生株式会社 | Liquid crystal device and projector |
| CN103278971A (en) * | 2012-10-10 | 2013-09-04 | 上海天马微电子有限公司 | Thin film transistor array substrate and manufacturing method thereof |
| CN104465652A (en) * | 2014-12-05 | 2015-03-25 | 上海天马微电子有限公司 | Array substrate, display device and manufacturing method of array substrate |
| CN104965358A (en) * | 2015-07-14 | 2015-10-07 | 深圳市华星光电技术有限公司 | Reflecting type TFT array panel, preparing method thereof and liquid crystal display |
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| US6459463B2 (en) * | 1997-06-14 | 2002-10-01 | L.G. Philips Lcd Co., Ltd. | Reflective liquid crystal display having a bent shape and method of manufacturing thereof |
| JP4023217B2 (en) * | 2002-05-24 | 2007-12-19 | セイコーエプソン株式会社 | Transflective liquid crystal device and electronic device using the same |
| CN1567422A (en) * | 2003-06-17 | 2005-01-19 | 统宝光电股份有限公司 | Low-leakage current thin film transistor circuit |
| CN100499140C (en) * | 2007-03-30 | 2009-06-10 | 友达光电股份有限公司 | Pixel structure and its production |
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| CN101661176A (en) * | 2008-08-29 | 2010-03-03 | 精工爱普生株式会社 | Liquid crystal device and projector |
| CN101661176B (en) * | 2008-08-29 | 2014-04-09 | 精工爱普生株式会社 | Liquid crystal device and projector |
| CN103278971A (en) * | 2012-10-10 | 2013-09-04 | 上海天马微电子有限公司 | Thin film transistor array substrate and manufacturing method thereof |
| CN104465652A (en) * | 2014-12-05 | 2015-03-25 | 上海天马微电子有限公司 | Array substrate, display device and manufacturing method of array substrate |
| CN104465652B (en) * | 2014-12-05 | 2018-09-18 | 上海天马微电子有限公司 | A kind of array substrate, the production method of display device and array substrate |
| CN104965358A (en) * | 2015-07-14 | 2015-10-07 | 深圳市华星光电技术有限公司 | Reflecting type TFT array panel, preparing method thereof and liquid crystal display |
| CN111092110A (en) * | 2019-07-05 | 2020-05-01 | 友达光电股份有限公司 | Pixel structure and display device |
| CN111092110B (en) * | 2019-07-05 | 2022-05-10 | 友达光电股份有限公司 | Pixel structure and display device |
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