CN101290739B

CN101290739B - Deviation eliminating device, IC chip and drive IC

Info

Publication number: CN101290739B
Application number: CN2008100829245A
Authority: CN
Inventors: 樋口钢儿
Original assignee: Oki Electric Industry Co Ltd
Current assignee: Lapis Semiconductor Co Ltd
Priority date: 2007-04-19
Filing date: 2008-03-07
Publication date: 2013-04-03
Anticipated expiration: 2028-03-07
Also published as: US8139053B2; CN101290739A; JP5179775B2; US20080303577A1; JP2008268473A

Abstract

The invention provides a deviation elimination device, IC chip and driving IC, capable of eliminating a deviation even a capacitance element or a resistance element is connected with external of an operational amplifier, and further performing signal output during the deviation elimination, comprising IC chips (602, 610) including several output circuits (428, 628) (other IC chips are also existed) with a function of deviation elimination. The several output circuits (428, 628) are performed with N divisions (N is a natural number) when eliminating the deviation, and a first standard output circuit (424) generates a REFIO signal (standard signal) for deviation elimination. Then, one of the division units is selected (regarding the IC chip as a unit), and the standard signal used by deviation elimination and generated by divided units is used as a standard signal for deviation elimination of other units.

Description

Deviation eliminating device, IC chip and drive IC

Technical field

The present invention relates to for take according to the amplifier of the output signal of input signal output regulation as object, eliminate deviation eliminating device, IC chip and the drive IC of the deviation of this amplifier.

Background technology

In the past, by increasing the transistorized gate area that consists of amplifier (operational amplifier), reduce the visible level of manufacture deviation, suppressed the deviation of operational amplifier.

Therefore, as eliminating the relevant prior art of circuit with deviation, proposed not increase the transistorized gate area of operational amplifier and the technology (with reference to patent documentation 1) of eliminating the deviation of operational amplifier.

In detail, when voltage was imported into input terminal, each on-off element switched, thereby accumulated the voltage that has deviation in capacity cell.Afterwards, each on-off element switches, thereby applies feedback according to the voltage that is accumulated in the capacity cell, so that the grid voltage of operational amplifier is identical value, thereby has eliminated the deviation of operational amplifier.

[patent documentation 1] TOHKEMY 2001-292041 communique

Yet, in the feedback element of capacity cell that be used for to set magnification or resistive element etc. and situation that the outside of operational amplifier is connected, the deviation that is caused by this electric capacity and resistance value is necessary to carry out the correction of magnification, and it is difficult tackling in existing deviation elimination circuit.

And, eliminate in the circuit in existing deviation, eliminate in deviation and can not carry out signal output in the action.In other words, must set deviation and eliminate pattern, thereby cause the decline of operating efficiency.

Summary of the invention

The present invention makes in view of the above fact, also can easily eliminate deviation even the purpose of this invention is to provide in a kind of feedback element at capacity cell or resistive element etc. and the situation that the outside of amplifier master formation section is connected, and can carry out simultaneously deviation and eliminate action and usually deviation eliminating device, IC chip and the drive IC of signal output action.

Inventing 1 described invention is a kind of deviation eliminating device, and it is crossed over a plurality of drive IC that drive display device and consists of, and it is characterized in that each above-mentioned drive IC has: than the output circuit that shows that data output number is Duoed; The reference voltage generating unit; And be arranged on storage part in each above-mentioned output circuit, when moving, the above-mentioned output circuit corresponding with above-mentioned demonstration data output number is to above-mentioned display unit output and the output that shows that data are corresponding, at least one party in the remaining above-mentioned output circuit compares output and the said reference voltage generating unit of above-mentioned output circuit, the value corresponding with the departure of above-mentioned output circuit is stored in the above-mentioned storage part, eliminate successively the deviation of above-mentioned output circuit, the reference voltage generating unit of each above-mentioned drive IC connects via the o pads of each above-mentioned drive IC.

Invent 2 described inventions, it is characterized in that, this deviation eliminating device has a plurality of output circuits for drive unit, be used for to have the device that deviation is eliminated function in action for each output circuit, above-mentioned a plurality of output circuits are carried out N to be cut apart, wherein N is natural number, each side is had generate the reference voltage generating unit that deviation is eliminated the reference voltage of usefulness, select a plurality of units of above-mentioned cutting unit, the above-mentioned deviation that said reference voltage generating unit by selected above-mentioned a plurality of units is generated is eliminated the whole short circuits of reference voltage of usefulness, and the deviation that becomes other all circuit is eliminated the reference voltage of usefulness.

Inventing 7 described inventions is a kind of IC chips, it has a plurality of output circuits, it is characterized in that, above-mentioned IC chip has deviation and eliminates function, when carrying out this deviation elimination, above-mentioned a plurality of output circuits is carried out N cut apart, wherein N is natural number, generate deviation for each side and eliminate the reference voltage generation unit, select this to cut apart in the unit 1, the deviation that the unit that utilization has been carried out cutting apart generates is eliminated with reference voltage and is eliminated reference voltage as the deviation of other unit.

Inventing 8 described inventions is a kind of IC chips, it has a plurality of output circuits, it is characterized in that above-mentioned IC chip has deviation and eliminates function, when carrying out this deviation elimination, above-mentioned a plurality of output circuits are carried out N to be cut apart, wherein N is natural number, generates deviation for each side and eliminates the reference voltage generation unit, selects this to cut apart a plurality of in the unit, the deviation that a plurality of units that make utilization carry out cutting apart generate is eliminated with the whole short circuits of reference voltage, eliminates reference voltage as the deviation of other unit.

Inventing 13 described inventions is a kind of drive IC, and it is a drive IC that drives in a plurality of drive IC of display device, it is characterized in that this drive IC has: than showing that data export the output circuit that number is Duoed; The reference voltage generating unit, its data according to usefulness relatively generate reference voltage; Storage part, it is arranged in each above-mentioned output circuit; Comparer, its output and said reference voltage with above-mentioned output circuit is compared; Switch element, it is arranged between said reference voltage generating unit and the above-mentioned comparer; The 10th pad, it is transfused to the signal of the above-mentioned switch element of control; And the 12nd pad, its with above-mentioned switch element be connected the node that comparer is connected and connect, when moving, the above-mentioned output circuit corresponding with above-mentioned demonstration data output number is to above-mentioned display device output and the output that shows that data are corresponding, at least one party in the remaining above-mentioned output circuit compares output and the said reference voltage of above-mentioned output circuit, the value corresponding with the departure of above-mentioned output circuit is stored in the above-mentioned storage part, carries out successively the elimination of the deviation voltage of above-mentioned output circuit.

As described above, according to the present invention, obtain following excellent results, even that is: can provide in the feedback element of capacity cell or resistive element etc. and situation that the outside of amplifier master formation section is connected and also can easily eliminate deviation, and can carry out simultaneously deviation and eliminate action and usually deviation eliminating device, IC chip and the drive IC of signal output action.

Description of drawings

Fig. 1 is that the liquid crystal display drive circuit according to basic mode is the whole summary construction diagram of driving circuit.

Fig. 2 is the structural drawing according to the output circuit in the driving circuit of basic mode.

Fig. 3 is the variation according to the output circuit of the Fig. 2 in the driving circuit of basic mode.

Fig. 4 is the structural drawing according to the 1st driving circuit of the 1st embodiment.

Fig. 5 is the structural drawing according to the 2nd driving circuit of the 2nd embodiment.

Fig. 6 is the structural drawing according to the 3rd driving circuit of the 3rd embodiment.

Fig. 7 is the structural drawing according to the layout of the 2IC of the 2nd embodiment of Fig. 5.

Symbol description

16: output circuit (1)～output circuit (n+1) (output circuit); 20: output select circuit (1)～output select circuit (n) (selected cell); 30: decision circuit (comparing unit); 210: operational amplifier (amplifier); 220,226: capacity cell (feedback element); 222: condenser network (feedback element); 230: gain-adjusted latch (storage part, storage unit, deviation are eliminated the unit); 340: latch cicuit (storage part, storage unit, deviation are eliminated the unit); RA1, RA2, RA3, RA4: resistive element (feedback element); RB1, RB2, RB3, RB4: resistive element (feedback element); 420: output select circuit (1)～output select circuit (n) (selected cell); 424: the 1 benchmark output circuits (reference voltage generating unit); 426: operational amplifier (amplifier); 428: output circuit (1)～output circuit (n+1) (output circuit); 430: decision circuit (comparing unit); 534: the 2 benchmark output circuits (reference voltage generating unit); 536: operational amplifier (amplifier); 624: the 3 benchmark output circuits (reference voltage generating unit); 626: operational amplifier (amplifier); 628: output circuit (1)～output circuit (n+1) (output circuit); 630: decision circuit (comparing unit); 658: switch (switch element).

Embodiment

Fig. 1 is that the liquid crystal display drive circuit according to basic mode is the whole summary construction diagram of driving circuit 10.

Fig. 1 is the driving circuit 10 according to basic mode, is the one-piece construction of driving circuit that drives the driver of LCD.And the liquid crystal drive that is used for driving LCD has a plurality of operational amplifiers with integrated circuit (output circuit 16).

Driving circuit 10 has: output circuit (1) 16～output circuit (n+1) 16 (being generically and collectively referred to as output circuit 16), output select circuit (1) 20～output select circuit (n) 20 (being generically and collectively referred to as output select circuit 20), lead-out terminal (1) 12～lead-out terminal (n) 12 (being generically and collectively referred to as lead-out terminal 12), and decision circuit 30 (wherein, n is natural number).

And decision circuit 30 has comparer 34 and judges output circuit 42.

In addition, a plurality of output circuits 16 also can arrange more than 2 than a plurality of output select circuits more than 20, and are not only to arrange 1 more, thereby in this case, a plurality of output select circuit 20 changes are also selected corresponding output circuit 16.And, a plurality of lead-out terminals 12 be connected such as display panels etc.And in Fig. 1, numerous and diverse for fear of figure omits diagram to the input terminal of the input signal of output circuit 16 inputs.

Fig. 2 is the structural drawing according to the output circuit 16 in the driving circuit 10 of basic mode.

Output circuit 16 has: operational amplifier 210, and capacity cell 220, switch 214, input end subgroup 200, the capacitor type D/A conversion circuit is (hereinafter referred to as CDAC.) 202, condenser network 222, and gain-adjusted electric capacity latch 230.

In addition, all output circuits 16 are same structures, and capacity cell is a kind of of feedback element.

CDAC 202 constitutes and comprises a plurality of switches 204 and a plurality of capacity cell 206.

Condenser network 222 constitutes and comprises a plurality of switches 224 and a plurality of capacity cell 226.

Input end subgroup 200 is a plurality of input terminals of supplied with digital signal, exists by everybody.

In CDAC 202, in accordance with regulations everybody of a terminal of each input switch 204 and capacity cell 206 is connected in series, and the input switch 204 that is connected in series and capacity cell 206 figure place in accordance with regulations have been connected in parallel a plurality of.And in CDAC 202, the another terminal of these capacity cells 206 is that the 4th signal wire 208 of simulating signal (output signal) is connected with the output voltage of output CDAC 202 all.

And in operational amplifier 210, an input is connected with the 4th signal wire 208, and another input is connected with the 5th signal wire 212, and an efferent is connected with a signal wire 14.

And an end of capacity cell 220 is connected with a signal wire 14, and the other end of capacity cell 220 is connected with the 4th signal wire 208, via the 4th signal wire 208, is connected with the input feedback that the outgoing side of CDAC 202 is connected with operational amplifier.

And in condenser network 222, switch 224 and capacity cell 226 are serially connected in respectively many groups.

In addition, with the latch 230 interior quantity latch cicuits suitable with switch 224 quantity that exist, this latch cicuit output is used for the signal of the on/off of gauge tap 224 at gain-adjusted electric capacity.The so-called gain-adjusted electric capacity that is built in uses a plurality of latch cicuits in the latch 230 corresponding one to one with a plurality of switch 224 difference, owing to be connected with 1 switch 224 from 1 latch cicuit, thereby in fact the 6th signal wire 232 exists a plurality of by the quantity of a plurality of switches 224.And, comprise latch control circuit (omitting diagram) in latch 230 at gain-adjusted electric capacity, this latch control circuit control is built in the on/off that gain-adjusted electric capacity is used a plurality of latch cicuits in the latch 230, utilize this latch control circuit, to remain in a plurality of latch cicuits via the judgement output signal that 40 inputs of the 3rd signal wire come, control a plurality of switches 224.

Below, the effect according to the output circuit 16 of the driving circuit 10 of basic mode is described.

At first, the switch 214 in the output circuit (1) 16 is connected, the switch 214 in output circuit (2) 16～output circuits (n+1) 16 is in addition all disconnected.

At this moment, the control of switch 214 is also controlled with the latch control circuit in the latch 230 by being built in gain-adjusted electric capacity.In addition, also be built-in with the data storage section (for example latch cicuit) that storage control waits (for example value corresponding with departure) in latch 230 at gain-adjusted electric capacity.

And, output select circuit 20 makes output circuit (2) 16 be connected with lead-out terminal (1) 12, output circuit (3) 16 is connected with lead-out terminal (2) 12, below connect equally, switch, until output circuit (n+1) 16 is connected on the lead-out terminal (n) 12.

Under this connection status, carry out the deviation of output circuit (1) 16 and eliminate action.In detail, at first, the switch 224 in condenser network 222 is all switched to latch 230 under the state of off-state by gain-adjusted electric capacity, has been determined that by the capacity cell 220 as feedback capacity the operational amplifier 210 of gain is exported output signal.The output signal of this output is imported into decision circuit 30 via a signal wire 14 and switch 214 by another signal wire 18.Then, the output signal that is input to decision circuit 30 is imported into comparer 34, the difference that comparer 34 is compared and obtained according to the reference voltage that occurs in the voltage that occurs and the signal that sends via the 1st signal wire 32 in the output signal that will send via another signal wire 18 outputs to output signal and to judge output circuit 42 via the 2nd signal wire 36.Therefore, judge that output circuit 42 is according to the signal of inputting, with judgement output signal timing output to the in accordance with regulations 3 signal wires 40 of result of determination.

The judgement output signal of exporting from decision circuit 30 is imported into each output circuit 16 via the 3rd signal wire 40.Then, input has the output circuit (1) 16 of judging output signal will be stored in via the judgement output signal that the 3rd signal wire 40 is exported from decision circuit 30 gain-adjusted electric capacity with in the storage part of latch 230.

At this moment, gain-adjusted electric capacity makes any one party of the switch 224 of condenser network 222 connect with latch 230.Decision circuit 30 under this state will be stored in via the judgement output signal that the 3rd signal wire 40 is exported from decision circuit 30 gain-adjusted electric capacity again with in the storage part of latch 230.

Repeat successively these actions, gain-adjusted electric capacity makes any one party of the switch 224 of condenser network 222 continue to connect successively with latch 230, append one by one the electric capacity of condenser network 222.

Then, decision circuit 30 repeats following action at every turn, that is: the reference voltage that occurs in the voltage that occurs and the signal that sends via the 1st signal wire 32 in the output signal that will send via another signal wire 18 is compared, this comparative result as judging that output signal feeds back to output circuit 16 via the 3rd signal wire 40.

Therefore, when in decision circuit 30, when the reference voltage that occurs in the signal that the voltage ratio that occurs in the output signal of sending via another signal wire 18 is sent via the 1st signal wire 32 was low, the deviation of output circuit (1) 16 was eliminated and is finished.

Then, when the deviation of output circuit (1) 16 was eliminated end, the switch 214 of output circuit (1) 16 disconnected, and then the switch 214 of output circuit (2) 16 is connected.And output select circuit (1) 20 and output circuit (2) 16 are connected 1 with lead-out terminal) 12 be connected.According to this connection status, carry out as mentioned above the deviation of output circuit (2) 16 and eliminate action.

Each output circuit 16 at output circuit 16 carries out the deviation elimination like this, and when the deviation elimination action of output circuit (n+1) 16 also finished, the deviation of repeatedly output circuit 16 was eliminated action again.

And the latch cicuit more than switching, deviation elimination action and output circuit 16 carry out the control of deviation elimination and are controlled with the latch control circuit of latch 230 by gain-adjusted electric capacity.

In addition, the timing of eliminating action in the deviation of not carrying out as mentioned above exists in the situation of several output circuits 16, in each output circuit 16 that does not carry out deviation elimination action, the digital signal (input signal) that will be input to the regulation figure place of input end subgroup 200 by CDAC 202 converts simulating signal (output signal) to.Afterwards, this simulating signal is imported into an input of operational amplifier 210 via the 4th signal wire 208, according to the reference voltage that is input to another input of operational amplifier 210 via the 5th signal wire 212, according to the parallel amplification of carrying out the simulating signal of inputting of electric capacity that is accumulated in capacity cell 220 and the condenser network 222.

Fig. 3 is the variation according to the output circuit 16 of the Fig. 2 in the driving circuit 10 of basic mode.

In output circuit 16, be formed with operational amplifier, this operational amplifier comprises differential transistor, i.e. paired 1N type field-effect transistor (hereinafter referred to as the 1st nmos pass transistor) 302 and 2N type field-effect transistor (hereinafter referred to as the 2nd nmos pass transistor) 304.

And, in output circuit 16, be formed with operational amplifier, this operational amplifier comprises current mirror (current mirror) circuit, i.e. paired 1P type field-effect transistor (hereinafter referred to as the 1PMOS transistor) 330 and 2P type field-effect transistor (hereinafter referred to as the 2nd PMOS transistor) 332.

And, in output circuit 16, output circuit 16 is made of following part, that is: resistive element RA1, RA2, RA3, RA4 ... (being generically and collectively referred to as resistive element RA system), resistive element RB 1, RB2, RB3, RB4 ... (being generically and collectively referred to as resistive element RB system), switch 310,214, and latch cicuit 340.In addition, resistive element all is a kind of of feedback element, and the structure of latch cicuit 340 is identical with latch 230 with the gain-adjusted electric capacity of Fig. 2.

And, output circuit 16 is made of following part, that is: 3P type field-effect transistor (hereinafter referred to as the 3rd PMOS transistor) 338,3N type field-effect transistor (hereinafter referred to as the 3rd nmos pass transistor) 350, and 4N type field-effect transistor (hereinafter referred to as the 4th nmos pass transistor) 352.

And, in output circuit 16, between the 1st nmos pass transistor 302 and node 306, be connected with resistive element RA1, between the 2nd nmos pass transistor 304 and node 306, be connected with resistive element RB1.

And, in output circuit 16, between the 1st nmos pass transistor 302 and node 306, be connected in parallel to respectively many group resistive element RA2, RA3, RA4 ... with switch 310 (resistive element and switch are connected in series respectively one by one).Equally, between the 2nd nmos pass transistor 304 and node 306, be connected in parallel to respectively many group resistive element RB2, RB3, RB4 ... with switch 310 (resistive element and switch are connected in series respectively one by one).

And, in output circuit 16, each drain electrode of the 1st nmos pass transistor 302 and the 2nd nmos pass transistor 304 is connected with the 1st connecting line 334 with 2P type field-effect transistor (hereinafter referred to as the 2nd PMOS transistor) 332 via 1P type field-effect transistor (hereinafter referred to as the 1st PMOS transistor) 330.

And in output circuit 16, the 2nd tie point 336 of the 1st nmos pass transistor 302 and the 1st PMOS transistor 330 is connected with the grid of 3P type field-effect transistor (hereinafter referred to as the 3rd PMOS transistor) 338.

And in output circuit 16, the drain electrode of the 3rd PMOS transistor 338 is connected with the grid of the 2nd nmos pass transistor 304, and is connected with a signal wire 14 as the output of output circuit 16.This signal wire 14 is connected with switch 214, and another signal wire 18 of switch 214 is connected with decision circuit 30.

And, in output circuit 16, with a plurality of resistive element RA2, RA3, RA4 ... with a plurality of resistive element RB2, RB3, RB4 ... the switch 310 that connects respectively is connected with the outgoing side of latch cicuit 340 via the 10th signal wire 342.

Below, the effect according to the output circuit 16 of Fig. 3 of basic mode is described.

At first, the output circuit (1) 16 that is configured in the 1st grade is connected its inner switch 214, and the switch 214 in output circuit (2) 16～output circuits (n+1) 16 is in addition all disconnected.And output select circuit 20 is the same with basic mode, and output circuit (2) 16 is connected with lead-out terminal (1) 12, below, the same connection, switch, until output circuit (n+1) 16 is connected on the lead-out terminal (n) 12.

The control of the switch 214 of this moment is also controlled by the latch control circuit that is built in the latch cicuit 340.In addition, the control of latch control circuit is carried out and the action identical according to the latch control circuit of the basic mode of Fig. 2.And, latch cicuit 340 control and resistive element RA2, RA3, RA4 ... with resistive element RB2, RB3, RB4 ... the on/off of the switch 310 that connects.And, the same with latch 230 with the gain-adjusted electric capacity of Fig. 2, in latch cicuit 340, also be built-in with the data storage section that storage is controlled etc.

Supply voltage (hereinafter referred to as VDD) is provided for the 1st connecting line 334.And the 3rd nmos pass transistor 350 that is connected with node 306 is applied in bias voltage and forms current source via the 11st signal wire 354 with the grid separately of the 4th nmos pass transistor 352 that the drain electrode with the 3rd PMOS transistor 338 is connected.

Under this state, carry out the deviation of output circuit (1) 16 and eliminate action.In detail, at first, make with resistive element RA2, RA3, RA4 ... the switch 310 that connects respectively all is in on-state, make with resistive element RB2, RB3, RB4 ... the switch 310 that connects respectively all is in off-state.

Then, under this state, carry out the output of output circuit (1) 16.In detail, determined that by resistive element RB1 the output circuit (1) 16 of Fig. 3 of gain exports output signal.

In addition, this output circuit 16 can also be replaced as operational amplifier, an input as INPUT is transfused to via the 12nd signal wire 320, another input of expression reference voltage is transfused to via the grid part of nmos pass transistor 304, and its output is output via a signal wire 14 or another signal wire 18.

Since connect the 1st nmos pass transistor 302 resistive element RA2, RA3, RA4 ... combined resistance be connected in parallel with the resistive element RB1 that is connected the 2nd nmos pass transistor 304, thereby resistive element RA2, RA3, RA4 ... combined resistance less than resistive element RB1.

Here, when when the 1st nmos pass transistor 302 flows through the electric current of identical value with the 2nd nmos pass transistor 304, it is larger than the source electrode of the 1st nmos pass transistor 302 and the voltage between the node 306 that the voltage between the source electrode of the 2nd nmos pass transistor 304 and the node 306 becomes.

Therefore, when the grid voltage of the 1st nmos pass transistor 302 and the 2nd nmos pass transistor 304 was in identical respectively agonic state, the output voltage of output circuit 16 was stable under the high state of the input voltage of the 12nd signal wire 320 that is compared to input (INPUT).

Under this state, the output signal that is input to decision circuit 30 is imported into comparer 34.And the reference voltage that occurs in the voltage that occurs and the signal that sends via the 1st signal wire 32 in the output signal that comparer 34 will send via switch 214 and another signal wire 18 is compared.

And comparator circuit 30 is according to the difference after relatively, output signal outputed to via the 2nd signal wire 36 judge output circuit 42.Then, in the high situation of reference voltage that the voltage ratio that occurs as output signal via switch 214 and another signal wire 18 is inputted via the 1st signal wire 32, from judging that output circuit 42 is the judgement output signal of its result of determination timing output to the 3 signal wires 40 in accordance with regulations.The judgement output signal of exporting via the 3rd signal wire 40 is provided for the judgement output signal that the storage portion stores of the latch cicuit 340 of each output circuit 16, the 1 output circuit (1) 16 is exported via the 3rd signal wire 40.

Then, resistive element RA2 is being controlled at off-state, is making under the state of output voltage slight reduction of output circuit 16, with the above-mentioned the same acts of determination of carrying out.When the acts of determination that is through with based on the off-state of resistive element RA2, the switch of the switch 310 that is connected with resistive element RA system is all disconnected, then make resistive element RB2, RB3 ... become successively on-state with the resistive element of resistive element RB system.Therebetween, the output voltage of output circuit 16 descends gradually, merge with the departure of operational amplifier, when the input voltage to 320 inputs of the 12nd signal wire as input (INPUT) equated with the output voltage of exporting from another signal wire 14, the deviation in the output circuit (1) 16 was eliminated release.

When the deviation in the output circuit (1) 16 was eliminated release, its inner switch 214 was switched to off-state, and output circuit (2) the 16 interior switches 214 that then are provided in next stage are switched to on-state.In addition, when carrying out this switching, according to the storage part in the latch cicuit 340 that is built in output circuit (1) 16, utilize the latch control circuit of the on/off of a plurality of latch cicuits of control, when deviation was eliminated release, the switch 214 that it is inner switched to off-state.And, next also following action is controlled: according to the storage part that is built in the latch cicuit 340 in the output circuit (2) 16, utilize the latch control circuit of the on/off of a plurality of latch cicuits of control, output circuit (2) the 16 interior switches 214 that are provided in next stage are switched to on-state.

And the change action of output select circuit 20 also carries out with the 1st embodiment the samely, and the output of output circuit (1) 16 is connected to lead-out terminal (1) 12.Afterwards, the deviation of carrying out successively in next stage or next stage output circuit (2) 16～output circuits (n+1) 16 is afterwards eliminated action, when the deviation of output circuit (n+1) 16 is eliminated release, again begin to repeat deviation from output circuit (1) 16 and eliminate action.

And, switch successively the control that above latch cicuit, deviation elimination action and output circuit 16 carry out the deviation elimination by the latch control circuit of latch cicuit 340.

Fig. 4 is the structural drawing of the 1st driving circuit 400 of the 1st embodiment.

The 1st driving circuit 400 is arranged on the substrate, by the formations such as IC chip (omitting diagram) beyond the 1st IC 410, electronic unit (omitting diagram) and the 1st IC 410.

The 1st IC 410 comprises: the 1st pad 412, the 2nd pad 414, the 3rd pad 416, signal segmentation circuit 438, the 1st benchmark output circuit 424, output circuit (1) 428～output circuit (n+1) 428 (being generically and collectively referred to as output circuit 428), output select circuit (1) 420～output select circuit (n) 420 (being generically and collectively referred to as output select circuit 420), lead-out terminal (1) 422～lead-out terminal (n) 422 (being generically and collectively referred to as lead-out terminal 422), and decision circuit 430.

The 1st benchmark output circuit 424 constitutes and comprises operational amplifier 426 and by the feedback element that constitutes of electronic units such as resistive element and capacity cell etc.

And decision circuit 430 constitutes and is built-in with comparer 434.

In addition, lead-out terminal 422 is output pads of the 1st IC 410.

And output circuit 428 is identical with the structure of the output circuit 16 of Fig. 2 or Fig. 3.

The 7th signal wire 800 is connected with signal segmentation circuit 438 via the 3rd pad 416.The 7th signal wire 800 that is connected with signal segmentation circuit 438 via the 3rd pad 416 via node 416 (0) are connected with the splitting signal line (0) be connected with the 1st benchmark output circuit 424.And the 7th signal wire 800 that is connected with signal segmentation circuit 438 via the 3rd pad 416 is connected with output circuit (1) 428 via node 416 (1) and splitting signal line 456 (1).Below same, the 7th signal wire 800 is connected with output circuit (n+1) 428 via node 416 (n+1) and splitting signal line 456 (n+1).

The 8th signal wire 810 is connected with the 1st benchmark output circuit 424 via the 2nd pad 414, the 13rd signal wire 454 and node 414 (0).And the 8th signal wire 810 is connected with output circuit (1) 428 via the 2nd pad 414, the 13rd signal wire 454 and node 414 (1).Below same, the 8th signal wire 810 is connected with output circuit (n+1) 428 via the 2nd pad 414, the 13rd signal wire 454 and node 414 (n+1).

The 9th signal wire 820 is connected with pad 412.

The efferent of the 1st benchmark output circuit 424 is connected with pad 412 via node 458 and the 14th signal wire 442.And the efferent of the 1st benchmark output circuit 424 is connected with decision circuit 430 via node 458.

In decision circuit 430, connected the comparer 434 of decision circuit 430 of the 16th signal wire 418 and the 14th signal wire 442 at the input side of the comparer 434 of decision circuit 430 via the 17th signal wire 440 of the outgoing side of comparer 434, be connected with a plurality of output circuits 428.

Output circuit 428 is connected with decision circuit 430 via the 16th signal wire 418, and is connected with output select circuit 420 via the 15th signal wire 444.

Then, a plurality of output select circuits 420 are connected respectively one to one with a plurality of lead-out terminals 422.

Below, the effect of the 1st IC 410 of the 1st driving circuit 400 of the 1st embodiment is described.

In addition, the 1st IC 410 is for one of a plurality of drive IC that drive display device (such as LCD etc.).

Adopt the situation of the output circuit 16 of Fig. 2 to describe to output circuit 428.

Send the GMA signal from the outside via the 7th signal wire 800, the GMA signal is imported into signal segmentation circuit 438 via the 3rd pad 416, the simulating signal corresponding with the 1st benchmark output circuit 424 is imported into the 1st benchmark output circuit 424 via node 416 (0) by splitting signal line 456 (0).In addition, in signal segmentation circuit 438, by resistive element the GMA signal of inputting via the 3rd pad 416 is cut apart, make the simulating signal corresponding with each output circuit (1) 428～output circuit (n+1) 428 via node 416 (1), 416 (2) ... and splitting signal line 456 (1), 456 (2) ... and input.

And, sending VOP signal as DC voltage from the outside as reference signal via the 8th signal wire 810, the VOP signal is imported into the 1st benchmark output circuit 424 via the 2nd pad 414 and node 414 (0).After, the VOP signal of inputting via the 2nd pad 414 via node 414 (1), 414 (2) ... be input to each output circuit (1) 428～output circuit (n+1) 428.In addition, the VOP signal is the reference voltage of usefulness relatively, is the voltage about 2.5V.

Therefore, the 1st benchmark output circuit 424 is transfused to the GMA signal of inputting via signal segmentation circuit 438 and the reference signal of inputting from the outside via the 8th signal wire 810 and the 2nd pad 414 is the VOP signal, decide gain by built-in operational amplifier 426, generate the REFIO signal that the expression deviation is eliminated the reference voltage of usefulness.In addition, in the situation of Fig. 4, be the REFIO signal sets 1 unit.

And the REFIO signal of exporting from the 1st benchmark output circuit 424 is imported into decision circuit 430 via node 458.And simultaneously, the REFIO signal of exporting from the 1st benchmark output circuit 424 is sent to the outside via the 14th signal wire 442 and the 1st pad 412 by the 9th signal wire 820.In addition, the REFIO signal also is for as the reference signal of other IC etc. and the signal of inputting.

And the simulating signal that output circuit 428 also is transfused to the VOP signal and is partitioned into from the GMA signal is carried out the action identical with the effect of output circuit 16 among Fig. 2 in the inside of output circuit 428.

1 switch 214 in a plurality of output circuits 428 is connected, the switch 214 of remaining output circuit 428 is in addition all disconnected.

At this moment, the control of switch 214 is also controlled with the latch control circuit in the latch 230 and storage part by being built in gain-adjusted electric capacity.

Output circuit 428 outputs to output select circuit 420 with output signal via the 15th signal wire 444.And simultaneously, output circuit 428 outputs to decision circuit 430 with output signal via the 16th signal wire 418.

In output select circuit 420, select the either party from the output signal that 2 mutually adjacent output circuits 428 send via the 15th signal wire 444.Then, output select circuit 420 selected output signals are sent to the lead-out terminal 422 corresponding with this output select circuit 420.

In decision circuit 430, for the result of comparer 434 comparisons, send to output circuit 428 by the judgement output signal of inciting somebody to action result's as a comparison signal via the 17th signal wire 440, thereby make signal feedback.

In detail, the output signal that comparer 434 will be inputted from the 16th signal wire 418 by output circuit 428 and compare from the reference voltage that the 14th signal wire 442 is inputted, generate the judgement output signal of the signal (output voltage) of expression comparative result, this judgement output signal is sent to a plurality of output circuits 428 in the timing of regulation via the 17th signal wire 440.Therefore, make the judgement output signal as result of determination feed back to a plurality of output circuits 428, according to judging output signal, again form from the feedback circuit of output circuit 428 via the 16th signal wire 418 output signal outputs, thereby signal is fed.

Under this state, carry out the deviation of an output circuit in a plurality of output circuits 428 and eliminate action, in turn, when deviation is eliminated release, carrying out successively immediately deviation in output circuit 428 eliminates, until output circuit (n+1) 428, when deviation was eliminated release, the deviation that again repeats output circuit 428 was eliminated action.

In addition, even the timing of eliminating action in the deviation of not carrying out as mentioned above exists in the situation of some output circuits 428, also carry out the action identical with output circuit 16 among Fig. 2.

Therefore, even in the feedback elements such as capacity cell or resistive element and situation that the outside of amplifier master formation section is connected, also can easily eliminate deviation, and can carry out simultaneously deviation and eliminate action and common signal output action.Specifically, in the 1st driving circuit 400, when a plurality of output circuits 428 carry out common output action, for example, on one side can drive the output action of the driving signal of LCD, eliminate Yi Bian carry out successively deviation.And, eliminate by carrying out deviation, can obtain impartial output voltage at all lead-out terminals 422.And, by making the thinner precision that further improves deviation of capacitance level of the capacity cell 226 that gain-adjusted uses, can obtain more impartial output voltage at all lead-out terminals 422.

And, can eliminate the difference of the average output bias that is built in the operational amplifier in a plurality of output circuits 428.For the so-called operational amplifier that is built in whole output circuits 428, carry out deviation by the REFIO signal with the identical reference voltage of exporting from the 1st benchmark output circuit 424 and eliminate, thereby the relative deviation separately of 428 of a plurality of output circuits can not occur.

And, because the correction for drift system of being limited in scope, if thereby the reference voltage of the 1st benchmark output circuit 424 output compares with the output voltage of operational amplifier in being built in output circuit 428 to depart from and will exceed correcting range when larger, the deviation of the operational amplifier of output circuit 428 does not carry out that deviation eliminates can be not residual yet.So-calledly be built in operational amplifier and a plurality of output circuits 428 in the 1st benchmark output circuit 424 by identical operation manufacturing, be same structure, cause can be expected identical output voltage, thereby can not occur because the deviation that the reference voltage deviation of the 1st benchmark output circuit 424 outputs causes is eliminated insufficiency.

In addition, a plurality of output circuits 428 not only can have 1 output circuit 428 than a plurality of output select circuits more than 420, also can have 2 above output circuits 428 more.

And, output circuit 428 adopts the situation of the output circuit 16 of Fig. 3 also to adopt the situation of output circuit 16 of Fig. 2 the same with output circuit 428, can assign to describe by the operating member that the declaratives of the output circuit 16 of Fig. 2 is changed to the output circuit 16 of Fig. 3.

Therefore, even in the feedback elements such as capacity cell or resistive element and situation that the outside of amplifier master formation section is connected, also can easily eliminate deviation, and can carry out simultaneously deviation and eliminate action and common signal output action.

For example, for the deviation of the voltage follower type of being used by lcd driver, do not use capacity cell, can eliminate deviation yet.And by increasing the precision of comparer 434, and the level setting of the resistive element that is resistive element RA system and resistive element RB is thinner amplitude, can carry out the high deviation elimination of precision.And deviation of the present invention is eliminated action can carry out signal output in this action.

And, can eliminate the difference of the average output bias that is built in the operational amplifier in a plurality of output circuits 428.

And, because the correction for drift system of being limited in scope, if thereby the reference voltage of the 1st benchmark output circuit 424 output compares deviation and will exceed correcting range when larger with the output voltage of operational amplifier in being built in output circuit 428, the deviation of the operational amplifier of output circuit 428 does not carry out that deviation eliminates can be not residual yet.

Fig. 5 is the structural drawing of the 2nd driving circuit 500 of the 2nd embodiment.

The 2nd driving circuit 500 is arranged on the substrate, by the formations such as IC chip (omitting diagram) beyond the 2nd IC 510, electronic unit (omitting diagram) and the 1st IC 410.

The structure of the 1st IC 410 that the 2nd IC 510 constitutes at Fig. 4 has been appended the 4th pad 512, the 5th pad 514, the 6th pad 516 and the 2nd benchmark output circuit 534.

The 2nd benchmark output circuit 534 that appends has the structure identical with the 1st benchmark output circuit 424, and constitutes and comprise operational amplifier 536 and by the feedback element that constitutes of electronic units such as resistive element and capacity cell etc.

The annexation of the 2nd embodiment of Fig. 5 is identical with the annexation of the 1st embodiment of Fig. 4, yet has appended the connection of the 4th pad 512, the 5th pad 514, the 6th pad 516 and the 2nd benchmark output circuit 534 that append in the structure of the 1st IC 410.

The annexation of appending below is shown.

The 7th signal wire 800 is connected with the 6th pad, and the 6th pad is connected with the splitting signal line via signal segmentation circuit 438 (by node 516 (0)) and is connected with the 2nd benchmark output circuit 534.

And the 8th signal wire 810 is connected with the 5th pad 514, and the 5th pad 514 is connected with the 2nd benchmark output circuit 534 via the 19th signal wire 554.

And splitting signal line 556 is connected with the input side of the 19th signal wire 554 with the operational amplifier 536 of the 2nd benchmark output circuit 534, and the 20th signal wire 542 is connected with the outgoing side of the operational amplifier 536 of the 2nd benchmark output circuit 534.And the 20th signal wire 542 is connected with the 4th pad 512, and the 4th pad 512 is connected with the 9th signal wire 820.

More than be the annexation of appending, only append and connected the 2nd benchmark output circuit 534.

Below, the effect of the 2nd IC 510 of the 2nd driving circuit 500 of the 2nd embodiment is described.

In addition, the same with the 1st IC 410, the 2nd IC 510 is for one of a plurality of drive IC that drive display device.

The benchmark output signal that the deviation of exporting from the 1st benchmark output circuit 424 is eliminated usefulness is that the REFIO signal is also by from 534 outputs of the 2nd benchmark output circuit, the 2nd benchmark output circuit 534 is arranged on the two ends of the 2nd IC 510, and the 1st embodiment is different with the 2nd embodiment in this.

The GMA signal that sends from the 7th signal wire 800 is divided so that corresponding with the 2nd benchmark output circuit 534 (or the 1st benchmark output circuit 424) by resistive element signal segmentation circuit 438, from node 516 (0) outputting analog signals of signal segmentation circuit 438.Then, in the 2nd benchmark output circuit 534, node 516 (0) and splitting signal line 556 input simulating signals via signal segmentation circuit 438, the reference signal of inputting from the outside via the 8th signal wire 810 and the 5th pad 514 is the VOP signal, determine gain by built-in operational amplifier 536, generate the REFIO signal that the expression deviation is eliminated the reference voltage of usefulness.

And, connect and short circuit via the 9th signal wire 820 with the REFIO signal of being connected 534 outputs of the 2nd benchmark output circuit from the REFIO signal of the 1st benchmark output circuit 424 outputs.In addition, in the situation of Fig. 5 also with the REFIO signal as 1 unit, although there is the REFIO signal of a plurality of units, however all short circuits.

Therefore, the REFIO signal of exporting from the 1st benchmark output circuit 424 and the REFIO signal exported from the 2nd benchmark output circuit 534 are owing to separate in distance, thereby do not have difference and deviation fully in the characteristics of signals that produces, thereby stable reference signal can be offered each output circuit 428.

Aspect so-called the 2nd IC 510 of manufacturing, can eliminate on the 2nd IC 510 owing to distance separates the situation that produces the property difference that is caused by error.

Fig. 7 is the structural drawing according to the layout 700 of the 2IC of the 2nd embodiment of Fig. 5.

Therefore, the details drawing of the layout 700 in the situation of the 2nd IC 510 of the 2nd embodiment at Practical manufacturing Fig. 5 shown in Figure 7.

Fig. 7 illustrates the example of the layout configurations of the operational amplifier that becomes reference.

Layout 700 is that a plurality of output circuit units 710,720 consist of by the aggregate of a plurality of output circuit units.

A plurality of output circuit units 710 are made of benchmark

output circuit unit

710A, 710B and a plurality of output circuit unit 710C, and a plurality of output circuit units 720 are made of benchmark

output circuit unit

720A, 720B and a plurality of output circuit unit 720C.

Actual when carrying out ICization, as shown in Figure 7, each unit is by spread configuration arranged side by side, and each wiring waits and illustrate, but connects up or copper wiring etc. is connected up at the internal-external use aluminium of unit, and unit is connected.

In layout 700, as shown in the figure, be configured to a plurality of output circuit unit 710C by benchmark

output circuit unit

710A, 710B clamping, same, be configured to a plurality of output circuit unit 720C by benchmark

output circuit unit

720A, 720B clamping.

In addition, can be following mode: do not have benchmark

output circuit unit

710B, 720A, be connected with the output circuit unit 720C central authorities of layout 700 of output circuit unit 710C connect, and side by side configuration by benchmark

output circuit unit

710A, 720B clamping.

For example, in the 2nd IC 510 of Fig. 5, suppose that output circuit 428 has 720 raceway grooves (following raceway groove is designated as ch).

In this case, it is output circuit unit 710C that output circuit (1) 428～output circuit (360) 428 becomes the aggregate with a plurality of output circuit units, become the benchmark output circuit unit 710A of expression the 1st benchmark output circuit 424, become the benchmark output circuit unit 710B of the paired benchmark output circuit of expression the 1st benchmark output circuit 424.And, it is output circuit unit 720C that output circuit (361) 428～output circuits (720) 428 become the aggregate with a plurality of output circuit units, become the benchmark output circuit unit 720A of expression the 2nd benchmark output circuit 534, become the benchmark output circuit unit 720B of the paired benchmark output circuit of expression the 2nd benchmark output circuit 534.And the output separately of benchmark

output circuit unit

710A, 710B, 720A, 720B is routed to whole short circuits, is connected with a side of the input reference signal of output circuit unit 710C, 720C.

By coming configuration baseline

output circuit unit

710A, 710B, 720A, 720B and output circuit unit 710C, 720C by the above, can each side be connected the shortlyest, can do one's utmost to suppress the characteristic variations apart from property.

And the output separately of benchmark

output circuit unit

710A, 710B, 720A, 720B is routed to whole short circuits, thereby eliminates the characteristic variations that distance causes.Therefore, the output separately of benchmark

output circuit unit

710A, 710B, 720A, 720B is connected with a side of the input reference signal of output circuit unit 710C, 720C, thereby can relatively eliminate the deviation of output circuit unit 710C, 720C.

And, can also realize the miniaturization of IC chip, can make side by side the IC chip of same structure, thereby can also suppress by the characteristic deviation that causes apart from essential factor beyond the deviation.

In addition, the 4th pad 512, the 5th pad 514, the 6th pad 516 and the 2nd benchmark output circuit 534 such benchmark output circuits also can arrange a plurality of separately.

Fig. 6 is the structural drawing of the 3rd driving circuit 600 of the 3rd embodiment.

The 3rd driving circuit 600 is made of the 3rd IC 610 and the 4th IC 602.

The structure of the 3rd IC 610 is identical with the structure of the 1st IC 410.

In addition, the structure of the 3rd IC 610 also can be identical with the structure of the 2nd IC 510.

The structure of the structure of the structure of the 4th IC 602 and the 3rd IC 610 or the 1st IC 410 is basic identical, yet has switch 658 between the part of the node 458 of the 3rd IC 610 and the 1st benchmark output circuit 424.Off-state when this switch 658 is normal.In other words, although do not illustrate, the 3rd IC 610 has the switch identical with switch 658, and connects into and be in on-state when normal.In addition, in the situation of Fig. 6, as 1 unit, there are a plurality of IC chips in the IC chip.

In detail, the 4th IC 602 comprises: the 7th pad 612, the 8th pad 614, the 9th pad 616, signal segmentation circuit 638, the 3rd benchmark output circuit 624, output circuit (1) 628～output circuit (n+1) 628 (being generically and collectively referred to as output circuit 628), output select circuit (1) 620～output select circuit (n) 620 (being generically and collectively referred to as output select circuit 620), lead-out terminal (1) 622～lead-out terminal (n) 622 (being generically and collectively referred to as lead-out terminal 622), switch 658, and decision circuit 630.

The 3rd benchmark output circuit 624 constitutes and comprises operational amplifier 626.

Decision circuit 630 constitutes and comprises comparer 634.

And output circuit 628 is identical with the structure of the output circuit 16 of Fig. 2 or Fig. 3.In detail, the same with Fig. 4 or Fig. 5, the output circuit 16 of Fig. 2 or Fig. 3 has been carried out the IC chip, make output circuit 628 miniaturizations (miniaturization) of Fig. 6.

And the output select circuit 620 also structure with the output select circuit 20 of Fig. 1 is identical.In detail, the output select circuit 20 of Fig. 1 has been carried out the IC chip, made output select circuit 620 miniaturizations (miniaturization) of Fig. 6.

And the lead-out terminal 622 also structure with the lead-out terminal 12 of Fig. 1 is identical.In detail, the concrete condition of the lead-out terminal 622 of Fig. 6 is, the lead-out terminal 12 of Fig. 1 has been carried out the IC chip, and lead-out terminal 622 all becomes pad, is miniaturized (miniaturization).

And the decision circuit 630 also structure with the decision circuit 30 of Fig. 1 is identical.In detail, the decision circuit 30 of Fig. 1 has been carried out the IC chip, made decision circuit 630 miniaturizations (miniaturization) of Fig. 6.

The 7th signal wire 800 is connected with signal segmentation circuit 638 via the 9th pad 616.The 7th signal wire 800 that is connected with signal segmentation circuit 638 via the 9th pad 616 via node 616 (0) are connected with the splitting signal line (0) be connected with the 3rd benchmark output circuit 624.And, below same, the 7th signal wire 800 that is connected with signal segmentation circuit 638 via the 3rd pad 616 via node 616 (1), 616 (2) ... and splitting signal line 656 (1), splitting signal line 656 (1) ..., with output circuit (1) 628, output circuit (2) 628 ... connect.

The 8th signal wire 810 is connected with the 3rd benchmark output circuit 624 via the 8th pad 614, the 21st signal wire 654 and node 614 (0).And, below same, the 8th signal wire 810 via the 8th pad 614, the 21st signal wire 654 and node 614 (1), node 614 (2) ..., with output circuit (1) 628, output circuit (2) 628 ... connect.

The efferent of the 3rd benchmark output circuit 624 switch 658 of open-circuit condition when normal is connected.And the efferent of the 3rd benchmark output circuit 624 is connected with decision circuit 630 via switch 658.

Be connected with an input side of decision circuit 630 via the 9th signal wire 820, the 7th pad 612 and the 24th signal wire 624.

In decision circuit 630, at the input side of comparer 634, the 24th signal wire 642 connects with the comparer 634 of the decision circuit 630 that has been connected the 23rd signal wire 618, at the outgoing side of comparer 634, is connected with a plurality of output circuits 628 via the 25th signal wire 640.

Output circuit 628 is connected with output select circuit 620 via the 22nd signal wire 644, and is connected with another input side of decision circuit 630 via the 23rd signal wire 618.In addition, the 23rd signal wire 618 of exporting respectively from output circuit 628 is as the whole short circuits of wiring.

In detail, output circuit (1) 628 is connected with output select circuit (1) 620 via the 22nd signal wire 644, and output circuit (n+1) 628 is connected with output select circuit (n) 620 via the 22nd signal wire 644.And output circuit (2) 628～output circuits (n) 628 are connected with 2 mutual adjacent output select circuits 620 in output select circuit (1) 620～output select circuit (n) 620 via the 22nd signal wire 644.

Output select circuit 620 is connected one to one with lead-out terminal 622.

Below, the 3rd IC 610 of the 3rd embodiment of Fig. 6 and the effect of the 4th IC 602 are described.

In addition, the 3rd IC 610 and the 4th IC 602 are for the drive IC that drives display device.

The action of the 1st IC 410 of the action of the 3rd IC 610 and Fig. 4 or the 2nd IC 510 of Fig. 5 is identical, although do not illustrate, the 3rd IC 610 has the switch (switch element) identical with switch 658, is in on-state when normal.In addition, although do not illustrate, be transfused to the 10th pad of control signal of the switch of on-state when normal in the 3rd IC 610 interior existence, from the 10th pad input signal, this signal is used for controlling so that switch becomes on-state when normal.

The action of the 4th IC 602 is basically identical with the action of the 2nd IC 510 of the 1st IC 410 of Fig. 4 or Fig. 5, yet switch 658 (normal time open circuit) is arranged between the 3rd benchmark output circuit 624 and decision circuit 630, owing to do not connect, thereby the signal that the 3rd benchmark output circuit 624 generates is not passed to decision circuit 630.

In addition, switch is connected in the situation of the IC (for example, the 3rd IC 610) that the first order connects, disconnects in the situation of the latter linked IC (for example, the 4th IC 602) of the 2nd grade or the 2nd grade.

The VOP signal that provides from the outside and the signal segmentation circuit of Fig. 4, Fig. 5 and Fig. 6 438 the same the 4th IC 602 that are imported into.In detail, the VOP signal via the 8th pad 614 and node 614 (0), 614 (1), 614 (2) ... be imported into the 3rd benchmark output circuit 624 and a plurality of output circuit 628.

Signal segmentation circuit 638 carries out the action identical with the signal segmentation circuit 438 of Fig. 4, Fig. 5 and Fig. 6, at node 616 (0), node 616 (1), node 616 (2) ... by resistive element a plurality of GMA signals that come via 616 inputs of the 9th pad are cut apart.And, be imported into the 3rd benchmark output circuit 624 and each output circuit 628 with the 3rd benchmark output circuit 624 and each output circuit 628 corresponding and divided simulating signals.

The REFIO signal that the 1st benchmark output circuit 424 of the 3rd IC 610 generates is output via the 9th signal wire 820 from the 3rd IC 610 by node 458 and the 14th signal wire 442.In addition, the REFIO signal also can via with will not make illustrated switch and be connected the 1st pad 412 (the 12nd pad) that the node 458 that is connected connects with decision circuit and be output.

At the 3rd IC 610, the such switch of switch 658 that between the 1st benchmark output circuit 424 and decision circuit 430, does not have the 4th IC 602, owing to are connected connections with node via the 14th signal wire 442, thereby the REFIO signal of the 1st benchmark output circuit 424 generations directly is imported into the reference signal input side of decision circuit 430.

And the REFIO signal that the 3rd IC 610 generates is imported into the input side of decision circuit 630 via the 7th pad 612 and the 24th signal wire 642, directly is imported into the reference signal input side of the decision circuit 630 of the 4th IC 602.

In addition, the REFIO signal of the 2nd benchmark output circuit 534 generations of the REFIO signal of the 1st benchmark output circuit 424 generations and Fig. 5 also can short circuit.And switch 658 also can be diode, so that signal can not enter, also can not connect up connects and fully for open-circuit condition.

Therefore, in decision circuit 630, by with comparer 634 result relatively via the 25th signal wire 640, as a comparison result's signal is judged that namely output signal sends to output circuit 628, makes signal feedback.

In detail, the signal that comparer 634 will be inputted from the 23rd signal wire 618 by output circuit 628 and compare from the reference voltage that the 24th signal wire 642 is inputted, generate the judgement output signal of expression comparative result, this judgement output signal is sent to a plurality of output circuits 628 in the timing of regulation via the 25th signal wire 640.Therefore, make the judgement output signal as result of determination feed back to a plurality of output circuits 628, according to judging output signal, again form from output circuit 628 via the feedback circuit of the 23rd signal wire 618 with output signal output.

The IC chip of so-called generation REFIO signal has 1, and the REFIO signal that this 1 IC chip generates is shared by other a plurality of IC chips and used.For example, the 3rd driving circuit 600 has 20 IC chips such as the 3rd IC 610 and the 4th IC 602, in the situation that constitutes the LCD driving circuit, for REFIO signal that the 3rd IC 610 the is generated REFIO signal (reference signal) as the comparer 634 of the decision circuit 630 of the 4th IC 602, other 19 IC chips use as the REFIO signal of 19 IC chips comparer separately.

And output select circuit 620 is selected from 2 mutually adjacent output circuits 620 via the either party the output signal of the 22nd signal wire 644 transmissions.Then, output select circuit 620 selected output signals are sent to and this output select circuit 620 corresponding lead-out terminal 622 one to one.

And output select circuit 620 receives the output signal of sending from the 22nd signal wire 644 of output circuit 628.

Then, when action, for example, the output circuit 428 corresponding with the demonstration data of display device output number, 628 etc. is to the display device output output corresponding with the demonstration data, at least one party in the remaining output circuit 428,628 etc. compares output circuit 428,628 etc. output with reference voltage, the value corresponding with the departure of output circuit is stored in the storage part that is built in the output circuit, eliminates successively the deviation of output circuit.

In addition, a plurality of output circuits 628 not only can have 1 output circuit 628 than a plurality of output select circuits more than 620, can also have 2 above output circuits 628, thereby in this case, a plurality of output select circuits 620 can change selects corresponding output circuit 628 more.And a plurality of lead-out terminals 622 are pads of the 1st IC 410, for example, and connecting fluid LCD panel etc.And in order to reduce cost, simplification manufacturing, easy design etc., the IC chip is made, is produced in identical structure, manufacturing process, production run.And, in 1 IC chip, can constitute as shown in Figure 5 exportable a plurality of benchmark output signal.

If describe simply, then also can describe by following.

At first, the action of the 3rd IC 610 described.

When between period of output, VOP signal and GMA signal that the benchmark amplifier receives as DC voltage generate the REFIO signal.

At first, output circuit (1) 428 (can be Ch1, below, output circuit (2) 428 can be described as Ch2 ...) output be input to the comparer 434 of decision circuit 430, compare with the REFIO signal and judge.Regulate the output of Ch1 according to this result, and in comparer, output is compared and judge.Repeat this action until there is not the deviation of Ch1, next carry out Ch2, Ch3 ... adjusting with other outputs.In the IC chip beyond the 3rd IC 610, for the REFIO signal, the signal former state that generates is input to comparer in the 3rd IC 610, carries out deviation and eliminate.

In addition, use at the same time in the lcd driver of a plurality of chips, because the difference of the average output bias of chip chamber becomes key property, thereby carry out deviation and eliminate.

As mentioned above, according to the 1st embodiment and the 2nd embodiment, owing in 1 chip or all chips, be that the REFIO signal of benchmark output signal carries out the deviation elimination with identical reference voltage, thereby the relative deviation between can generating chip.

And, the operational amplifier 426 of the 1st benchmark output circuit 424 (benchmark operational amplifier) adopts the structure identical with the operational amplifier (output operational amplifier) of output circuit 428, thereby can expect to eliminate the deviation of output operational amplifier and operational amplifier self, export identical output voltage.Therefore, can not occur by the signal as benchmark is that the deviation that the deviation of voltage causes is eliminated insufficiency.

As shown in Figure 5, disposed the 1st benchmark output circuit 424 and the 2nd benchmark output circuit 534 that comprises as the operational amplifier of benchmark at the two ends of a plurality of output circuits 428 that comprise operational amplifier, thus can about offset the deviation that is caused by Place Attachment on the IC chip.

And, the output signal short circuit of at least one party in the operational amplifier 426 of the 1st benchmark output circuit 424 by making Fig. 5 and the operational amplifier 536 of the 2nd benchmark output circuit 534 is used, reduce the deviation as the operational amplifier self of the benchmark of at least one party in the operational amplifier 536 of the operational amplifier 426 of the 1st benchmark output circuit 424 of Fig. 5 and the 2nd benchmark output circuit 534, thereby can also fully obtain driving force.

Therefore, the reference voltage of at least one party output of utilization from the operational amplifier 536 of the operational amplifier 426 of the 1st benchmark output circuit 424 shown in Figure 5 and the 2nd benchmark output circuit 534 decides the precision of output voltage, can make the potential difference (PD) of the reference voltage of chip chamber can directly not become the differing from of average output bias of IC chip chamber and is output.

Express simply, can suppress the output voltage deviation (error) in the manufacturing of relative accuracy of chip chamber of reference voltage, i.e. so-called relative deviation.

And, because the correction for drift system of being limited in scope, if thereby the reference voltage of at least one party's output from the operational amplifier 536 of the operational amplifier 426 of the 1st benchmark output circuit 424 of Fig. 5 and the 2nd benchmark output circuit 534 and each operational amplifier 426,536 to compare deviation larger, the boundary that then exceeds the correction for drift scope, the deviation of IC chip chamber are not eliminated and are residual.

Therefore, on making, owing to similarly make and produce, also can suppress the deviation of deviation output voltage in addition as shown in Figure 7, can realize cost, production simplification, design easily.

And, by sharing the reference voltage of each IC chip, be connected with other chips from a plurality of reference voltage generating units more than 1, reference voltage unified (identical), thereby can eliminate deviation.

And, use at least one party in the operational amplifier 536 of the operational amplifier 426 of the 1st benchmark output circuit 424 of Fig. 5 and the 2nd benchmark output circuit 534, make its output short-circuit, thereby in the inside and outside difference that all can offset characteristic separately of IC chip.

In addition, the operational amplifier as benchmark of Fig. 6 only makes the 3rd IC 610 action, yet can also make as all actions and make its output short-circuit of the operational amplifier of the benchmark of all IC chips, makes it become the reference signal that deviation is eliminated usefulness.Perhaps, can also therefrom select and comprise the some IC chips that have as the 3rd IC 610 of the operational amplifier of benchmark, make this operational amplifier action of selecting, make its output short-circuit carry out deviation and eliminate.And the switch that comprises the such IC chip of the 4th IC602 of the switch 658 that disconnects when normal can be controlled, and can also become the state that can carry out the switching of on/off.

Claims

1. a deviation eliminating device is characterized in that, this deviation eliminating device is used for following equipment: this equipment has a plurality of output circuits for drive unit, and can have deviation elimination function for each output circuit in action,

Above-mentioned a plurality of output circuits are divided into N output circuit aggregate, wherein N is natural number, each side is had generate the reference voltage generating unit that deviation is eliminated the reference voltage of usefulness, select a plurality of output circuit aggregates in above-mentioned N the output circuit aggregate, the above-mentioned deviation that said reference voltage generating unit by selected above-mentioned a plurality of output circuit aggregates is generated is eliminated the whole short circuits of reference voltage of usefulness, and the deviation that becomes other all circuit is eliminated the reference voltage of usefulness.

2. deviation eliminating device according to claim 1 is characterized in that, this deviation eliminating device has:

A plurality of amplifiers, it comprises be used to the feedback element that carries out gain-adjusted, and exports the output signal of regulation according to input signal;

Action object, its combination by the output signal lacked than above-mentioned a plurality of amplifiers is moved;

Selected cell, it selects the needed a plurality of above-mentioned amplifiers of action of above-mentioned action object;

Comparing unit, the above-mentioned output signal of the above-mentioned amplifier that it will be not be selected by above-mentioned selected cell is compared with the reference signal as benchmark; And

Deviation is eliminated the unit, and it proofreaies and correct above-mentioned gain adjustment amount according to above-mentioned comparing unit result relatively, eliminates the deviation of above-mentioned amplifier.

3. deviation eliminating device according to claim 2 is characterized in that,

Above-mentioned deviation is eliminated the storage unit that the unit has the fluctuation number of the above-mentioned feedback element number of storage or sets number,

According to the comparative result of above-mentioned comparing unit, from said memory cells, read fluctuation number or set number, decide gain adjustment amount according to this fluctuation number of reading or setting number.

4. deviation eliminating device according to claim 3 is characterized in that, repeats the increase and decrease of above-mentioned feedback element number until output signal becomes suitable.

5. according to claim 2～and each described deviation eliminating device in the claim 4, it is characterized in that above-mentioned selected cell uses the bisection method search function, all above-mentioned amplifiers all may become the object of not selected by above-mentioned selected cell.

6. IC chip, it has a plurality of output circuits, it is characterized in that, and above-mentioned IC chip has deviation and eliminates function,

When carrying out this deviation elimination, above-mentioned a plurality of output circuits are divided into N output circuit aggregate, wherein N is natural number, generate deviation for each side and eliminate the reference voltage generation unit, select 1 output circuit aggregate in above-mentioned N the output circuit aggregate, the deviation that the output circuit aggregate that utilization has been carried out cutting apart generates is eliminated with reference voltage and is eliminated reference voltage as the deviation of other output circuit aggregates.

7. IC chip, it has a plurality of output circuits, it is characterized in that, and above-mentioned IC chip has deviation and eliminates function,

When carrying out this deviation elimination, above-mentioned a plurality of output circuits are divided into N output circuit aggregate, wherein N is natural number, generate deviation for each side and eliminate the reference voltage generation unit, select a plurality of output circuit aggregates in this N the output circuit aggregate, the deviation that a plurality of output circuit aggregates that make utilization carry out cutting apart generate is eliminated with the whole short circuits of reference voltage, eliminates reference voltage as the deviation of other output circuit aggregates.

8. according to claim 6 or IC chip claimed in claim 7, it is characterized in that this IC chip has:

9. IC chip according to claim 8 is characterized in that,

10. IC chip according to claim 9 is characterized in that, repeats the increase and decrease of above-mentioned feedback element number until output signal becomes suitable.

11. according to claim 8～and each described IC chip in the claim 10, it is characterized in that above-mentioned selected cell uses the bisection method search function, all above-mentioned amplifiers all may become the object of not selected by above-mentioned selected cell.