CN101290444B

CN101290444B - Method for driving LCD device

Info

Publication number: CN101290444B
Application number: CN2008101083133A
Authority: CN
Inventors: 白承丘; 王仓鸿; 陈忠君; 詹功一; 黎焕欣; 李忠隆
Original assignee: AU Optronics Corp
Current assignee: AU Optronics Corp
Priority date: 2008-06-06
Filing date: 2008-06-06
Publication date: 2010-07-28
Anticipated expiration: 2028-06-06
Also published as: CN101290444A

Abstract

The invention discloses a method for driving a liquid crystal display with a plurality of groups of grid lines. The method comprises the following steps that: a plurality of odd grid lines of the first group of grid lines are arranged in an ascending order in a first period of time, the first polarity data is written into a plurality of corresponding pixels by matching a first common voltage; a plurality of even grid lines of the first group of grid lines are arranged in an ascending order in a second period of time, the second polarity data is written into a plurality of corresponding pixels by matching a second common voltage; a plurality of even grid lines of the second group of grid lines are arranged in a descending order in a third period of time, the second polarity data is written into a plurality of corresponding pixels by matching a second common voltage; and a plurality of odd grid lines of the second group of grid lines are arranged in a descending order in a fourth period of time, the first polarity data is written into a plurality of corresponding pixels by matching the first common voltage. The method can evidently improve the picture quality.

Description

Drive the method for a liquid crystal indicator

Technical field

The present invention relates to a kind of method that drives liquid crystal indicator, relate in particular to a kind of staggered commutation scan pattern based on many groups gate line to drive the method for liquid crystal indicator, the moire effect (Mura effect) that is used for reducing display frame is to improve picture quality.

Background technology

Liquid crystal indicator is present widely used a kind of flat-panel screens, features such as it has, and external form is frivolous, power saving and radiationless pollution.The voltage difference that the principle of work utilization of liquid crystal indicator changes the liquid crystal layer two ends changes the ordered state of the liquid crystal molecule in the liquid crystal layer, in order to change the light transmission of liquid crystal layer, to cooperate backlight module again the light source that provided with display image.

Generally speaking, the polarity of voltage that is applied to the liquid crystal material layer two ends must reverse at set intervals, causes nonvolatil destruction in order to avoid liquid crystal material to produce polarization, also in order to avoid image remaining (Image Sticking) effect.So, just develop the type of drive that four kinds of liquid crystal indicators: frame counter-rotating (Frame Inversion), line counter-rotating (Line Inversion), pixel inversion (Pixel Inversion) and some counter-rotating (Dot Inversion).

When the mode of using the frame counter-rotating drove liquid crystal indicator, the data-signal of each frame was an identical polar, and and the data-signal of next frame be opposite polarity.The line counter-rotating comprises row counter-rotating (RowInversion) and row counter-rotatings (Column Inversion).When the mode of using the row counter-rotating drove liquid crystal indicator, the data-signal of each row and the data-signal of its adjacent lines were opposite polarity.When the mode of using the row counter-rotating drove liquid crystal indicator, the data-signal of each row and the data-signal of its adjacent column were opposite polarity.When the mode of using pixel inversion drove liquid crystal indicator, the data-signal that the data-signal of each pixel is adjacent pixel was an opposite polarity, but the data-signals red, green and blue three pixel cells in the same pixel then have identical polar.When the mode of using the some counter-rotating drove liquid crystal indicator, the data-signal that the data-signal of each pixel cell is adjacent pixel cell was an opposite polarity.Because the type of drive of pixel inversion and some counter-rotating can provide better display quality, so the type of drive of pixel inversion and some counter-rotating is the type of drive that present liquid crystal indicator more often uses.

Please refer to Fig. 1, Fig. 1 is the known liquid crystal indicator synoptic diagram based on row inversion driving pattern.As shown in Figure 1, liquid crystal indicator 100 comprises many data lines 160, many gate lines 150, many common electrode lines 180 and a plurality of pixel cell 170.For convenience of description, the liquid crystal indicator 100 of Fig. 1 only shows 160,6 common electrode lines 180 of 6 data lines, reaches 6 gate lines 150 (GL1-GL6), each bar common electrode line 180 all receives common voltage Vcom, each bar data line 160 is in order to transmit the corresponding data signal, and each bar gate line 150 is then in order to transmit corresponding signal.For example article one gate lines G L1 is in order to transmitting first grid signal SGL1, and the 6th gate lines G L6 be in order to transmit the 6th signal SGL6, and the rest may be inferred by analogy for it.Each pixel cell 170 is red pixel unit, green pixel unit or blue pixel unit.Each pixel cell 170 comprises data switch 171 and storage unit 173.By the corresponding signal that each bar gate line 150 is transmitted, the conducting cut-off state of the corresponding a plurality of data switches 171 of may command, and then control writes data-signal the write operation of corresponding stored unit 173 via data line 160.

Fig. 2 is the pixel polarity synoptic diagram of the shown N picture of the liquid crystal indicator of Fig. 1, and wherein "+" (positive polarity) expression voltage data signal subtracts common voltage Vcom for just, and "-" (negative polarity) expression voltage data signal subtracts common voltage Vcom for bearing.In N picture 200 shown in Figure 2, the odd-numbered line pixel cell all is written into the positive polarity data-signal, and the even number line pixel cell all is written into the negative polarity data-signal.Fig. 3 is that wherein transverse axis is a time shaft according to the coherent signal sequential chart of known method for driving liquid crystal display with the N picture of generation Fig. 2.In Fig. 3, the data-signal that the positive sign representative in the bracket is write is a positive polarity, and the data-signal that the negative sign representative in the bracket is write is a negative polarity.As shown in Figure 3, in known method for driving liquid crystal display, the image time that produces N picture 200 is divided into first period and second period.In first period, common voltage Vcom is set as low-voltage, and the signal of odd-numbered line gate line is enabled in regular turn to write the positive polarity data-signal to the odd-numbered line pixel cell.In second period, common voltage Vcom is set as high voltage, and the signal of even number line gate line is enabled in regular turn to write the negative polarity data-signal to the even number line pixel cell.

For example, in continuous mutually sub-period Td1, Td2 and the Td3 of first period, signal SGL1, SGL3 and SGL5 are enabled in regular turn, so can write positive polarity data-signal to first and third and five-element's pixel cell in regular turn via many data lines 160.In continuous mutually sub-period Td1, Td2 and the Td3 of second period, signal SGL2, SGL4 and SGL6 are enabled in regular turn, so can write negative polarity data-signal to the second, four and six row pixel cells in regular turn via many data lines 160.

Yet, in above-mentioned known method for driving liquid crystal display, when showing a picture, image time only was divided into for two periods, in regular turn odd-numbered line and even number line are transmitted respectively the data-signal of opposed polarity, so the leakage current of data switch can cause the data-signal of adjacent lines to have significant voltage drift difference, thereby causes picture moire effect (Mura effect) to reduce picture quality.In addition, when showing a picture, the voltage level of common voltage only switches once, so also more serious by the pixel intensity error that voltage level-shift caused of common voltage.Moreover the signal of first period and second period enables order, when being the increasing or decreasing order, causes the gradient luminance error of full frame easily, also can reduce picture quality.

Summary of the invention

For overcoming the defective of prior art, the present invention proposes a kind of method that drives liquid crystal indicator.

According to embodiments of the invention, it discloses a kind of method of driving one liquid crystal indicator, this liquid crystal indicator includes the multirow pixel, organizes gate line and many data lines more, the method comprises: in first period of first group of period, according to the first order order, a plurality of signals of many odd gates lines of first group of gate line of the gate lines of group more than enabling in regular turn; In second period of first group of period,, enable a plurality of signals of many even number gate lines of first group of gate line in regular turn according to the second order order; Yu Xiangxu is in first period of second group of period of first group of period, puts in order according to the 3rd, enables a plurality of signals of many even number gate lines of second group of gate line in regular turn; And in second period of second group of period, put in order according to the 4th, enable a plurality of signals of many odd gates lines of second group of gate line in regular turn.Wherein first period of first group of period and second period do not overlap each other, and first period of second group of period and second period do not overlap each other.

Liquid crystal display apparatus driving circuit of the present invention, many gate lines are divided into many group gate lines, enable the odd gates line or the even number gate line of each group gate line respectively in regular turn with the increasing or decreasing order, and write the positive polarity data and write the negative polarity data with high common voltage with low common voltage, no matter so be row inversion driving pattern, the pixel inversion drive pattern, or some inversion driving pattern, all can reduce the signal voltage drift difference and the reduction full frame gradient luminance error of the data-signal of adjacent lines, simultaneously also moire effect can be reduced, therefore picture quality can be significantly improved.In addition, in addition can be in order to reduce the required voltage swing of positive-negative polarity gray scale voltage of source electrode drive circuit output, can reduce the required power consumption of positive-negative polarity gray scale voltage handoff procedure, and the withstand voltage scope of element that source electrode drive circuit uses also can reduce, so liquid crystal indicator just can use low withstand voltage element to reduce cost.

Description of drawings

Fig. 1 is the known liquid crystal indicator synoptic diagram based on row inversion driving pattern.

Fig. 2 is the pixel polarity synoptic diagram of the shown N picture of the liquid crystal indicator of Fig. 1.

Fig. 3 is that wherein transverse axis is a time shaft according to the coherent signal sequential chart of known method for driving liquid crystal display with the N picture of generation Fig. 2.

Fig. 4 is for using the liquid crystal indicator synoptic diagram of the present invention's row inversion driving method.

Fig. 5 is the pixel polarity synoptic diagram of the shown M picture of the liquid crystal indicator of Fig. 4.

Fig. 6 is that wherein transverse axis is a time shaft according to the capable inversion driving method of first embodiment of the invention signal and the common voltage sequential chart with the M picture that produces Fig. 5.

Fig. 7 is that wherein transverse axis is a time shaft according to the capable inversion driving method of second embodiment of the invention signal and the common voltage sequential chart with the M picture that produces Fig. 5.

Fig. 8 is for using the liquid crystal indicator synoptic diagram of pixel inversion driving method of the present invention.

Fig. 9 is the pixel polarity synoptic diagram of the shown I picture of the liquid crystal indicator of Fig. 8.

Figure 10 is according to the sequential chart of Fig. 6 relevant write operation method list with the I picture that produces Fig. 9.

Figure 11 is according to the sequential chart of Fig. 7 relevant write operation method list with the I picture that produces Fig. 9.

Figure 12 puts the synoptic diagram of the liquid crystal indicator of inversion driving method for using the present invention.

Figure 13 is the pixel polarity synoptic diagram of the shown L picture of the liquid crystal indicator of Figure 12.

Figure 14 is according to the sequential chart of Fig. 6 relevant write operation method list with the L picture that produces Figure 13.

Figure 15 is according to the sequential chart of Fig. 7 relevant write operation method list with the L picture that produces Figure 13.

Figure 16 is for using another liquid crystal indicator synoptic diagram of the present invention's row inversion driving method.

Figure 17 is signal and a memory capacitance common voltage sequential chart of carrying out the row reverse turn operation according to the liquid crystal indicator of Figure 16, and wherein transverse axis is a time shaft.

Figure 18 is for using another liquid crystal indicator synoptic diagram of pixel inversion driving method of the present invention.

Figure 19 puts another liquid crystal indicator synoptic diagram of inversion driving method for using the present invention.

Figure 20 is for carrying out the row reverse turn operation to produce the work coherent signal sequential chart of J picture and J+1 picture according to the liquid crystal indicator of Fig. 4, and wherein transverse axis is a time shaft.

Figure 21 is for carrying out the row reverse turn operation to produce the work coherent signal sequential chart of J+2 picture and J+3 picture according to the liquid crystal indicator of Fig. 4, and wherein transverse axis is a time shaft.

Figure 22 is for carrying out the row reverse turn operation to produce the work coherent signal sequential chart of J+4 picture and J+5 picture according to the liquid crystal indicator of Fig. 4, and wherein transverse axis is a time shaft.

And the description of reference numerals in the above-mentioned accompanying drawing is as follows:

10,30,50,100,400,700,900 liquid crystal indicators

14,34,54,440,740 pixels

15,35,55,150,450,750,950 gate lines

16,36,56,160,460,760,960 data lines

18,38,58 memory capacitance common electrode lines

19,39,59 liquid crystal capacitance common electrode lines

20,40,60,170,470,770,970 pixel cells

21,41,61,171,471,771,971 data switches

23,43,63 liquid crystal capacitances

25,45,65 memory capacitance

173,473,773,973 storage unit

180,480,780,980 common electrode lines

200 N pictures

500 M pictures

800 I pictures

990 L pictures

First group of gate line of GL1-GL6

Second group of gate line of GL7-GL12

The 3rd group of gate line of GL13-GL18

SGL1-SGL18, SGLn-1-SGLn+3 signal

The Td1-Td6 sub-period

Vclc liquid crystal capacitance common voltage

The Vcom common voltage

Vcst_1-Vcst_12, Vcst_n-1-Vcst_n+2 memory capacitance common voltage

Embodiment

For making the present invention more apparent and understandable, hereinafter, elaborate especially exemplified by the embodiment conjunction with figs. according to the method for driving one liquid crystal indicator of the present invention, but the scope that the embodiment that is provided is not contained in order to restriction the present invention.

Fig. 4 is for using the liquid crystal indicator synoptic diagram of the present invention's row inversion driving method.As shown in Figure 4, liquid crystal indicator 400 comprises many data lines 460, many gate lines 450, many common electrode lines 480 and multirow pixel, and wherein many gate lines 450 are divided into many group gate lines.For convenience of description, the liquid crystal indicator 400 of Fig. 4 only shows 460,18 common electrode lines 480 of 6 data lines, reaches 18 gate lines 450 (GL1-GL18), each bar common electrode line 480 all receives common voltage Vcom, each bar data line 460 is in order to transmit the corresponding data signal, and each bar gate line 450 is then in order to transmit corresponding signal.For example article one gate lines G L1 is in order to transmitting first grid signal SGL1, and the 18 gate lines G L18 be in order to transmit the 18 signal SGL18, and the rest may be inferred by analogy for it.Article 18, gate line 450 (GL1-GL18) is divided into first group of gate lines G L1-GL6, second group of gate lines G L6-GL12, and the 3rd group of gate lines G L13-GL18.Each row pixel comprises a plurality of pixels 440, and each pixel 440 comprises three pixel cells 470.Each pixel cell 470 is red pixel unit, green pixel unit or blue pixel unit.Each pixel cell 470 comprises data switch 471 and storage unit 473.Storage unit 473 comprises at least one liquid crystal capacitance and at least one memory capacitance.

By the corresponding signal that each bar gate line 450 is transmitted, the conducting cut-off state of the corresponding a plurality of data switches 471 of may command, and then control writes data-signal the write operation of corresponding stored unit 473 via data line 460.Fig. 5 is the pixel polarity synoptic diagram of the shown M picture of the liquid crystal indicator of Fig. 4.As shown in Figure 5, M picture 500 shows that the odd-numbered line pixel cell all is written into the positive polarity data-signal, and the even number line pixel cell all is written into the negative polarity data-signal.Please refer to Fig. 6, Fig. 6 is that wherein transverse axis is a time shaft according to the capable inversion driving method of first embodiment of the invention signal and the common voltage sequential chart with the M picture that produces Fig. 5.As shown in Figure 6, in the capable inversion driving method of first embodiment of the invention, the image time that produces M picture 500 is divided into many groups period, and each group period comprises first period and second period, and first period and second period are subdivided into a plurality of sub-period Td1-Td3 and Td4-Td6 more respectively.

In sequential chart shown in Figure 6, in second period of first period of first group of period, second group of period, and first period of the 3rd group of period, common voltage Vcom is set as first voltage (low-voltage), and in first period of second period of first group of period, second group of period, and second period of the 3rd group of period, common voltage Vcom is set as second voltage (high voltage).In the write operation of a plurality of continuous sub-period Td1-Td3 mutually of first period of first group of period, enable many odd indexed gate lines G L1, GL3 of first group of gate line and a plurality of corresponding signal SGL1, SGL3 and the SGL5 of GL5 according to incremental order, and, in regular turn the positive polarity data-signal is write first and third and five-element's pixel according to a plurality of corresponding signal SGL1, the SGL3 and the SGL5 that are enabled in regular turn.

In the write operation of a plurality of continuous sub-period Td4-Td6 mutually of second period of first group of period, then enable many even number sequence number gate lines G L2, GL4 of first group of gate line and a plurality of corresponding signal SGL2, SGL4 and the SGL6 of GL6 according to incremental order, and, in regular turn the negative polarity data-signal is write second, four and six row pixels according to a plurality of corresponding signal SGL2, the SGL4 and the SGL6 that are enabled in regular turn.In the write operation of a plurality of continuous sub-period Td1-Td3 mutually of first period of second group of period, enable many even number sequence number gate lines G L12, GL10 of second group of gate line and a plurality of corresponding signal SGL12, SGL10 and the SGL8 of GL8 according to the order of successively decreasing, and, in regular turn the negative polarity data-signal is write the 12, ten and eight row pixels according to a plurality of corresponding signal SGL12, the SGL10 and the SGL8 that are enabled in regular turn.In the write operation of a plurality of continuous sub-period Td4-Td6 mutually of second period of second group of period, enable many odd indexed gate lines G L11, GL9 of second group of gate line and a plurality of corresponding signal SGL11, SGL9 and the SGL7 of GL7 according to the order of successively decreasing, and, in regular turn the positive polarity data-signal is write the 11, nine and seven row pixels according to a plurality of corresponding signal SGL11, the SGL9 and the SGL7 that are enabled in regular turn.

In the write operation of a plurality of continuous sub-period Td1-Td3 mutually of first period of the 3rd group of period, enable many odd indexed gate lines G L13, GL15 of the 3rd group of gate line and a plurality of corresponding signal SGL13, SGL15 and the SGL17 of GL17 according to incremental order, and, in regular turn the positive polarity data-signal is write the 13,15 and 17 row pixels according to a plurality of corresponding signal SGL13, the SGL15 and the SGL17 that are enabled in regular turn.In the write operation of a plurality of continuous sub-period Td4-Td6 mutually of second period of the 3rd group of period, enable many even number sequence number gate lines G L14, GL16 of the 3rd group of gate line and a plurality of corresponding signal SGL14, SGL16 and the SGL18 of GL18 according to incremental order, and, in regular turn the negative polarity data-signal is write the 14,16 and 18 row pixels according to a plurality of corresponding signal SGL14, the SGL16 and the SGL18 that are enabled in regular turn.

In the method for driving liquid crystal display of the invention described above first embodiment based on row inversion driving pattern, the signal of adjacent gate polar curve group enables order for reverse, the data-signal that is the boundary pixel unit of adjacent gate polar curve group has similar voltage drift amount, that is to say, can thereby improve by the undesirable border GTG error that the different voltage drift amounts of the data-signal of the boundary pixel unit of adjacent gate polar curve group are caused, so just can reduce group's moire (Band Mura) effect of the boundary pixel unit of adjacent gate polar curve group.Please note, in the liquid crystal indicator 400 of Fig. 4, though each group gate line comprises 6 gate lines, but method for driving liquid crystal display of the present invention is not limit the liquid crystal indicator that is used in based on the grid line groups of 6 gate lines, be the liquid crystal indicator that method for driving liquid crystal display of the present invention is applicable to any grid line groups based on many gate lines, all the other embodiment of following the present invention also in like manner analogize.In addition, the data-signal of the data-signal of each pixel cell of the M+1 picture that is produced according to the invention described above first embodiment and the respective pixel unit of M picture 500 is an opposite polarity, promptly in the driving operation of M+1 picture, first voltage of common voltage Vcom is set as high voltage, and second voltage of common voltage Vcom is set as low-voltage, and be negative polarity, and be positive polarity corresponding to the data-signal that second voltage of common voltage Vcom is write corresponding to the data-signal that first voltage of common voltage Vcom is write.

Please refer to Fig. 7, Fig. 7 is that wherein transverse axis is a time shaft according to the capable inversion driving method of second embodiment of the invention signal and the common voltage sequential chart with the M picture that produces Fig. 5.As shown in Figure 7, in the method for driving liquid crystal display of second embodiment of the invention, the image time that produces M picture 500 is divided into many groups period, and each group period comprises first period and second period, and first period and second period are subdivided into a plurality of sub-period Td1-Td3 and Td4-Td6 more respectively.In sequential chart shown in Figure 7, in first period of first period of first group of period, second group of period, and first period of the 3rd group of period, common voltage Vcom is set as first voltage (low-voltage), and in second period of second period of first group of period, second group of period, and second period of the 3rd group of period, common voltage Vcom is set as second voltage (high voltage).

In the write operation of a plurality of continuous sub-period Td1-Td3 mutually of first period of first group of period, enable many odd indexed gate lines G L1, GL3 of first group of gate line and a plurality of corresponding signal SGL1, SGL3 and the SGL5 of GL5 according to incremental order, and, in regular turn the positive polarity data-signal is write first and third and five-element's pixel according to a plurality of corresponding signal SGL1, the SGL3 and the SGL5 that are enabled in regular turn.In the write operation of a plurality of continuous sub-period Td4-Td6 mutually of second period of first group of period, then enable many even number sequence number gate lines G L2, GL4 of first group of gate line and a plurality of corresponding signal SGL2, SGL4 and the SGL6 of GL6 according to incremental order, and, in regular turn the negative polarity data-signal is write second, four and six row pixels according to a plurality of corresponding signal SGL2, the SGL4 and the SGL6 that are enabled in regular turn.

In the write operation of a plurality of continuous sub-period Td1-Td3 mutually of first period of second group of period, enable many odd indexed gate lines G L11, GL9 of second group of gate line and a plurality of corresponding signal SGL11, SGL9 and the SGL7 of GL7 according to the order of successively decreasing, and, in regular turn the positive polarity data-signal is write the 11, nine and seven row pixels according to a plurality of corresponding signal SGL11, the SGL9 and the SGL7 that are enabled in regular turn.In the write operation of a plurality of continuous sub-period Td4-Td6 mutually of second period of second group of period, enable many even number sequence number gate lines G L12, GL10 of second group of gate line and a plurality of corresponding signal SGL12, SGL10 and the SGL8 of GL8 according to the order of successively decreasing, and, in regular turn the negative polarity data-signal is write the 12, ten and eight row pixels according to a plurality of corresponding signal SGL12, the SGL10 and the SGL8 that are enabled in regular turn.

In the method for driving liquid crystal display based on row inversion driving pattern of the invention described above second embodiment, the signal of adjacent gate polar curve group enables order for oppositely, so can reduce group's moire effect of the boundary pixel unit of adjacent gate polar curve group.In like manner, the data-signal of the data-signal of each pixel cell of the M+1 picture that is produced according to the invention described above second embodiment and the respective pixel unit of M picture 500 is an opposite polarity, promptly in the driving operation of M+1 picture, first voltage of common voltage Vcom is set as high voltage, and second voltage of common voltage Vcom is set as low-voltage, and be negative polarity, and be positive polarity corresponding to the data-signal that second voltage of common voltage Vcom is write corresponding to the data-signal that first voltage of common voltage Vcom is write.

Fig. 8 is for using the liquid crystal indicator synoptic diagram of pixel inversion driving method of the present invention.As shown in Figure 8, liquid crystal indicator 700 comprises many data lines 760, many gate lines 750, many common electrode lines 780 and multirow pixel, and wherein many gate lines 750 are divided into many group gate lines.For convenience of description, the liquid crystal indicator 700 of Fig. 8 only shows 760,18 common electrode lines 780 of 6 data lines, reaches 18 gate lines 750 (GL1-GL18), each bar common electrode line 780 all receives common voltage Vcom, each bar data line 760 is in order to transmit the corresponding data signal, and each bar gate line 750 is then in order to transmit corresponding signal.Article 18, gate line 750 (GL1-GL18) is divided into first group of gate lines G L1-GL6, second group of gate lines G L6-GL12, and the 3rd group of gate lines G L13-GL18.Each row pixel comprises a plurality of pixels 740, and each pixel 740 comprises three pixel cells 770.Each pixel cell 770 is red pixel unit, green pixel unit or blue pixel unit.Each pixel cell 770 comprises data switch 771 and storage unit 773.Storage unit 773 comprises at least one liquid crystal capacitance and at least one memory capacitance.

Each data switch 771 comprises first end, second end and gate terminal, and wherein first end is coupled to respective data lines 760, the second ends and is coupled to corresponding stored electric capacity 773, and gate terminal is coupled to corresponding gate line 750.For example, in the first row pixel, the gate terminal of data switch 771 of each pixel cell 770 with a plurality of pixels 740 of odd number ordering is coupled to the first row gate lines G L1, and the gate terminal of data switch 771 of each pixel cell 770 with a plurality of pixels 740 of even number ordering is coupled to the second row gate lines G L2.In the second row pixel, the gate terminal of data switch 771 of each pixel cell 770 with a plurality of pixels 740 of odd number ordering is coupled to the second row gate lines G L2, and the gate terminal of data switch 771 of each pixel cell 770 with a plurality of pixels 740 of even number ordering is coupled to the third line gate lines G L3, and all the other are in like manner analogized.

By the corresponding signal that each bar gate line 750 is transmitted, the conducting cut-off state of the corresponding a plurality of data switches 771 of may command, and then control writes data-signal the write operation of corresponding stored unit 773 via data line 760.Fig. 9 is the pixel polarity synoptic diagram of the shown I picture of the liquid crystal indicator of Fig. 8, in I picture 800, each pixel cell 770 of a plurality of pixels 740 with odd number ordering of odd-numbered line all is written into the positive polarity data-signal with each pixel cell 770 of a plurality of pixels 740 with even number ordering of even number line, and each pixel cell 770 of a plurality of pixels 740 with odd number ordering of each pixel cell 770 of a plurality of pixels 740 with even number ordering of odd-numbered line and even number line all is written into the negative polarity data-signal.Please continue with reference to figure 6, to produce signal and the common voltage sequential chart that Fig. 9 has the I picture 800 of pixel inversion, signal and common voltage sequential chart that this Fig. 9 has the I picture 800 of pixel inversion are same as sequential chart shown in Figure 6 according to the method for driving liquid crystal display of third embodiment of the invention.

Figure 10 is according to the sequential chart of Fig. 6 relevant write operation method list with the I picture that produces Fig. 9.As Fig. 6 and shown in Figure 10, in second period of first period of first group of period, second group of period, and first period of the 3rd group of period, common voltage Vcom is set as first voltage (low-voltage), and in first period of second period of first group of period, second group of period, and second period of the 3rd group of period, common voltage Vcom is set as second voltage (high voltage).

In Fig. 6 and write operation shown in Figure 10, continuous mutually sub-period Td1-Td3 in first period of first group of period, many odd gates line GL1, GL3 that enable first group of gate line in regular turn according to putting in order of increasing progressively and a plurality of corresponding signal SGL1, SGL3 and the SGL5 of GL5, write a plurality of pixels 740 with odd number ordering of corresponding odd-numbered line pixel in order to a plurality of data-signals that will have positive polarity, and a plurality of data-signals that will have positive polarity write a plurality of pixels 740 with even number ordering of corresponding even number line pixel.For example, in the write operation of the sub-period Td2 of first period of first group of period, enable the signal SGL3 of the third line gate lines G L3, write a plurality of pixels 740 with odd number ordering of the third line pixel in order to a plurality of data-signals that will have positive polarity, and a plurality of data-signals that will have positive polarity write a plurality of pixels 740 with even number ordering of the second row pixel.

Continuous mutually sub-period Td4-Td6 in second period of first group of period, many even number gate lines G L2, GL4 that enable first group of gate line in regular turn according to putting in order of increasing progressively and a plurality of corresponding signal SGL2, SGL4 and the SGL6 of GL6, write a plurality of pixels 740 with odd number ordering of corresponding even number line pixel in order to a plurality of data-signals that will have negative polarity, and a plurality of data-signals that will have a negative polarity write a plurality of pixels 740 with even number ordering of corresponding odd-numbered line pixel.For example, in the write operation of the sub-period Td5 of second period of first group of period, enable the signal SGL4 of fourth line gate lines G L4, write a plurality of pixels 740 with odd number ordering of fourth line pixel in order to a plurality of data-signals that will have negative polarity, and a plurality of data-signals that will have a negative polarity write a plurality of pixels 740 with even number ordering of the third line pixel.

Continuous mutually sub-period Td1-Td3 in first period of second group of period, many even number gate lines G L12, GL10 that enable second group of gate line in regular turn according to putting in order of successively decreasing and a plurality of corresponding signal SGL12, SGL10 and the SGL8 of GL8, write a plurality of pixels 740 with odd number ordering of corresponding even number line pixel in order to a plurality of data-signals that will have negative polarity, and a plurality of data-signals that will have a negative polarity write a plurality of pixels 740 with even number ordering of corresponding odd-numbered line pixel.For example, in the write operation of the sub-period Td2 of first period of second group of period, enable the signal SGL10 of the tenth row gate lines G L10, write a plurality of pixels 740 with odd number ordering of the tenth row pixel in order to a plurality of data-signals that will have negative polarity, and a plurality of data-signals that will have a negative polarity write a plurality of pixels 740 with even number ordering of the 9th row pixel.

Continuous mutually sub-period Td4-Td6 in second period of second group of period, many odd gates line GL11, GL9 that enable second group of gate line in regular turn according to putting in order of successively decreasing and a plurality of corresponding signal SGL11, SGL9 and the SGL7 of GL7, write a plurality of pixels 740 with odd number ordering of corresponding odd-numbered line pixel in order to a plurality of data-signals that will have positive polarity, and a plurality of data-signals that will have positive polarity write a plurality of pixels 740 with even number ordering of corresponding even number line pixel.For example, in the write operation of the sub-period Td5 of second period of second group of period, enable the signal SGL9 of the 9th row gate lines G L9, write a plurality of pixels 740 with odd number ordering of the 9th row pixel in order to a plurality of data-signals that will have positive polarity, and a plurality of data-signals that will have positive polarity write a plurality of pixels 740 with even number ordering of the 8th row pixel.

Continuous mutually sub-period Td1-Td3 in first period of the 3rd group of period, many odd gates line GL13, GL15 that enable the 3rd group of gate line in regular turn according to putting in order of increasing progressively and a plurality of corresponding signal SGL13, SGL15 and the SGL17 of GL17, write a plurality of pixels 740 with odd number ordering of corresponding odd-numbered line pixel in order to a plurality of data-signals that will have positive polarity, and a plurality of data-signals that will have positive polarity write a plurality of pixels 740 with even number ordering of corresponding even number line pixel.Continuous mutually sub-period Td4-Td6 in second period of the 3rd group of period, many even number gate lines G L14, GL16 that enable the 3rd group of gate line in regular turn according to putting in order of increasing progressively and a plurality of corresponding signal SGL14, SGL16 and the SGL18 of GL18, write a plurality of pixels 740 with odd number ordering of corresponding even number line pixel in order to a plurality of data-signals that will have negative polarity, and a plurality of data-signals that will have a negative polarity write a plurality of pixels 740 with even number ordering of corresponding odd-numbered line pixel.

Please note, though in the write operation of the sub-period Td1 of first period of first group of period shown in Figure 10, only describe a plurality of pixels 740 that a plurality of data-signals that will have positive polarity write the first row pixel, but can comprise a plurality of pixels that a plurality of data-signals that will have positive polarity write last column pixel (even number line pixel) or secondary row pixel in addition with even number ordering with odd number ordering.In the method for driving liquid crystal display based on the pixel inversion drive pattern of the invention described above the 3rd embodiment, the signal of adjacent gate polar curve group enables order for oppositely, so can reduce group's moire effect of the boundary pixel unit of adjacent gate polar curve group.In addition, the data-signal of the data-signal of each pixel cell of the I+1 picture that is produced according to the invention described above the 3rd embodiment and the respective pixel unit of I picture 800 is an opposite polarity, promptly in the driving operation of I+1 picture, first voltage of common voltage Vcom is set as high voltage, and second voltage of common voltage Vcom is set as low-voltage, and be negative polarity, and be positive polarity corresponding to the data-signal that second voltage of common voltage Vcom is write corresponding to the data-signal that first voltage of common voltage Vcom is write.

Please continue with reference to figure 7, to produce signal and the common voltage sequential chart that Fig. 9 has the I picture 800 of pixel inversion, signal and common voltage sequential chart that this Fig. 9 has the I picture 800 of pixel inversion are same as sequential chart shown in Figure 7 according to the method for driving liquid crystal display of fourth embodiment of the invention.Figure 11 is according to the sequential chart of Fig. 7 relevant write operation method list with the I picture that produces Fig. 9.As Fig. 7 and shown in Figure 11, in first period of first period of first group of period, second group of period, and first period of the 3rd group of period, common voltage Vcom is set as first voltage (low-voltage), and in second period of second period of first group of period, second group of period, and second period of the 3rd group of period, common voltage Vcom is set as second voltage (high voltage).

In Fig. 7 and write operation shown in Figure 11, continuous mutually sub-period Td1-Td3 in first period of first group of period, many odd gates line GL1, GL3 that enable first group of gate line in regular turn according to putting in order of increasing progressively and a plurality of corresponding signal SGL1, SGL3 and the SGL5 of GL5, write a plurality of pixels 740 with odd number ordering of corresponding odd-numbered line pixel in order to a plurality of data-signals that will have positive polarity, and a plurality of data-signals that will have positive polarity write a plurality of pixels 740 with even number ordering of corresponding even number line pixel.Continuous mutually sub-period Td4-Td6 in second period of first group of period, many even number gate lines G L2, GL4 that enable first group of gate line in regular turn according to putting in order of increasing progressively and a plurality of corresponding signal SGL2, SGL4 and the SGL6 of GL6, write a plurality of pixels 740 with odd number ordering of corresponding even number line pixel in order to a plurality of data-signals that will have negative polarity, and a plurality of data-signals that will have a negative polarity write a plurality of pixels 740 with even number ordering of corresponding odd-numbered line pixel.

Continuous mutually sub-period Td1-Td3 in first period of second group of period, many odd gates line GL11, GL9 that enable second group of gate line in regular turn according to putting in order of successively decreasing and a plurality of corresponding signal SGL11, SGL9 and the SGL7 of GL7, write a plurality of pixels 740 with odd number ordering of corresponding odd-numbered line pixel in order to a plurality of data-signals that will have positive polarity, and a plurality of data-signals that will have a negative polarity write a plurality of pixels 740 with even number ordering of corresponding even number line pixel.Continuous mutually sub-period Td4-Td6 in second period of second group of period, many even number gate lines G L12, GL10 that enable second group of gate line in regular turn according to putting in order of successively decreasing and a plurality of corresponding signal SGL12, SGL10 and the SGL8 of GL8, write a plurality of pixels 740 with odd number ordering of corresponding even number line pixel in order to a plurality of data-signals that will have negative polarity, and a plurality of data-signals that will have a negative polarity write a plurality of pixels 740 with even number ordering of corresponding odd-numbered line pixel.

Please note, though in the write operation of the sub-period Td1 of first period of first group of period shown in Figure 11, only describe a plurality of pixels 740 that a plurality of data-signals that will have positive polarity write the first row pixel, but can comprise a plurality of pixels that a plurality of data-signals that will have positive polarity write last column pixel (even number line pixel) or secondary row pixel in addition with even number ordering with odd number ordering.In the method for driving liquid crystal display based on the pixel inversion drive pattern of the invention described above the 4th embodiment, the signal of adjacent gate polar curve group enables order for oppositely, so can reduce group's moire effect of the boundary pixel unit of adjacent gate polar curve group.In like manner, the data-signal of the data-signal of each pixel cell of the I+1 picture that is produced according to the invention described above the 4th embodiment and the respective pixel unit of I picture 800 is an opposite polarity, promptly in the driving operation of I+1 picture, first voltage of common voltage Vcom is set as high voltage, and second voltage of common voltage Vcom is set as low-voltage, and be negative polarity, and be positive polarity corresponding to the data-signal that second voltage of common voltage Vcom is write corresponding to the data-signal that first voltage of common voltage Vcom is write.

Figure 12 puts the synoptic diagram of the liquid crystal indicator of inversion driving method for using the present invention.As shown in figure 12, liquid crystal indicator 900 comprises many data lines 960, many gate lines 950, many common electrode lines 980 and multirow pixel cell, and wherein many gate lines 950 are divided into many group gate lines.For convenience of description, the liquid crystal indicator 900 of Figure 12 only shows 960,18 common electrode lines 980 of 6 data lines, reaches 18 gate lines 950 (GL1-GL18), each bar common electrode line 980 all receives common voltage Vcom, each bar data line 960 is in order to transmit the corresponding data signal, and each bar gate line 950 is then in order to transmit corresponding signal.Article 18, gate line 950 (GL1-GL18) is divided into first group of gate lines G L1-GL6, second group of gate lines G L6-GL12, and the 3rd group of gate lines G L13-GL18.Each row pixel cell comprises a plurality of pixel cells 970, and each pixel cell 970 is red pixel unit, green pixel unit or blue pixel unit.Each pixel cell 970 comprises data switch 971 and storage unit 973.Storage unit 973 comprises at least one liquid crystal capacitance and at least one memory capacitance.

Each data switch 971 comprises first end, second end and gate terminal, and wherein first end is coupled to respective data lines 960, the second ends and is coupled to corresponding stored electric capacity 973, and gate terminal is coupled to corresponding gate line 950.For example, in the first row pixel cell, the gate terminal of data switch 971 with a plurality of pixel cells 970 of odd number ordering is coupled to the first row gate lines G L1, and the gate terminal of data switch 971 with a plurality of pixel cells 970 of even number ordering is coupled to the second row gate lines G L2.In the second row pixel cell, the gate terminal of data switch 971 with a plurality of pixel cells 970 of odd number ordering is coupled to the second row gate lines G L2, and the gate terminal of data switch 971 with a plurality of pixel cells 970 of even number ordering is coupled to the third line gate lines G L3, and all the other are in like manner analogized.

By the corresponding signal that each bar gate line 950 is transmitted, the conducting cut-off state of the corresponding a plurality of data switches 971 of may command, and then control writes data-signal the write operation of corresponding stored unit 973 via data line 960.Figure 13 is the pixel polarity synoptic diagram of the shown L picture of the liquid crystal indicator of Figure 12, in L picture 990, a plurality of pixel cells 970 (corresponding to odd column) with odd number ordering of odd-numbered line all are written into the positive polarity data-signal with a plurality of pixel cells 970 (corresponding to even column) with even number ordering of even number line, and a plurality of pixel cells 970 (corresponding to odd column) with odd number ordering of a plurality of pixel cells 970 (corresponding to even column) with even number ordering of odd-numbered line and even number line all are written into the negative polarity data-signal.Please continue with reference to figure 6, to produce signal and the common voltage sequential chart that Figure 13 has the L picture 990 of a counter-rotating, signal and common voltage sequential chart that this Figure 13 has the L picture 990 of a counter-rotating are same as sequential chart shown in Figure 6 according to the method for driving liquid crystal display of fifth embodiment of the invention.

Figure 14 is according to the sequential chart of Fig. 6 relevant write operation method list with the L picture that produces Figure 13.As Fig. 6 and shown in Figure 14, in second period of first period of first group of period, second group of period, and first period of the 3rd group of period, common voltage Vcom is set as first voltage (low-voltage), and in first period of second period of first group of period, second group of period, and second period of the 3rd group of period, common voltage Vcom is set as second voltage (high voltage).

In Fig. 6 and write operation shown in Figure 14, continuous mutually sub-period Td1-Td3 in first period of first group of period, many odd gates line GL1, GL3 that enable first group of gate line in regular turn according to putting in order of increasing progressively and a plurality of corresponding signal SGL1, SGL3 and the SGL5 of GL5, write a plurality of pixel cells 970 with odd number ordering of corresponding odd-numbered line pixel cell in order to a plurality of data-signals that will have positive polarity, and a plurality of data-signals that will have positive polarity write a plurality of pixel cells 970 with even number ordering of corresponding even number line pixel cell.Continuous mutually sub-period Td4-Td6 in second period of first group of period, many even number gate lines G L2, GL4 that enable first group of gate line in regular turn according to putting in order of increasing progressively and a plurality of corresponding signal SGL2, SGL4 and the SGL6 of GL6, write the pixel cell 970 with odd number ordering of corresponding even number line pixel cell in order to a plurality of data-signals that will have negative polarity, and a plurality of data-signals that will have a negative polarity write a plurality of pixel cells 970 with even number ordering of corresponding odd-numbered line pixel cell.

Continuous mutually sub-period Td1-Td3 in first period of second group of period, many even number gate lines G L12, GL10 that enable second group of gate line in regular turn according to putting in order of successively decreasing and a plurality of corresponding signal SGL12, SGL10 and the SGL8 of GL8, write a plurality of pixel cells 970 with odd number ordering of corresponding even number line pixel cell in order to a plurality of data-signals that will have negative polarity, and a plurality of data-signals that will have a negative polarity write a plurality of pixel cells 970 with even number ordering of corresponding odd-numbered line pixel cell.Continuous mutually sub-period Td4-Td6 in second period of second group of period, many odd gates line GL11, GL9 that enable second group of gate line in regular turn according to putting in order of successively decreasing and a plurality of corresponding signal SGL11, SGL9 and the SGL7 of GL7, write a plurality of pixel cells 970 with odd number ordering of corresponding odd-numbered line pixel cell in order to a plurality of data-signals that will have positive polarity, and a plurality of data-signals that will have positive polarity write a plurality of pixel cells 970 with even number ordering of corresponding even number line pixel cell.

Continuous mutually sub-period Td1-Td3 in first period of the 3rd group of period, many odd gates line GL13, GL15 that enable the 3rd group of gate line in regular turn according to putting in order of increasing progressively and a plurality of corresponding signal SGL13, SGL15 and the SGL17 of GL17, write a plurality of pixel cells 970 with odd number ordering of corresponding odd-numbered line pixel cell in order to a plurality of data-signals that will have positive polarity, and a plurality of data-signals that will have positive polarity write a plurality of pixel cells 970 with even number ordering of corresponding even number line pixel cell.Continuous mutually sub-period Td4-Td6 in second period of the 3rd group of period, many even number gate lines G L14, GL16 that enable the 3rd group of gate line in regular turn according to putting in order of increasing progressively and a plurality of corresponding signal SGL14, SGL16 and the SGL18 of GL18, write a plurality of pixel cells 970 with odd number ordering of corresponding even number line pixel cell in order to a plurality of data-signals that will have negative polarity, and a plurality of data-signals that will have a negative polarity write a plurality of pixel cells 970 with even number ordering of corresponding odd-numbered line pixel cell.

Please note, though in the write operation of the sub-period Td1 of first period of first group of period shown in Figure 14, only describe a plurality of pixel cells that a plurality of data-signals that will have positive polarity write the first row pixel cell, but can comprise a plurality of pixel cells 970 that a plurality of data-signals that will have positive polarity write last column pixel cell (even number line pixel cell) or secondary row pixel cell in addition with even number ordering with odd number ordering.The invention described above the 5th embodiment based on a method for driving liquid crystal display of inversion driving pattern in, the signal of adjacent gate polar curve group enables order for oppositely, so can reduce group's moire effect of the boundary pixel unit of adjacent gate polar curve group.In addition, the data-signal of the data-signal of each pixel cell of the L+1 picture that is produced according to the invention described above the 5th embodiment and the respective pixel unit of L picture 990 is an opposite polarity, promptly in the driving operation of L+1 picture, first voltage of common voltage Vcom is set as high voltage, and second voltage of common voltage Vcom is set as low-voltage, and be negative polarity, and be positive polarity corresponding to the data-signal that second voltage of common voltage Vcom is write corresponding to the data-signal that first voltage of common voltage Vcom is write.

Please continue with reference to figure 7, according to the method for driving liquid crystal display of sixth embodiment of the invention signal and the common voltage sequential chart with the L picture 990 that produces Figure 13, the signal and the common voltage sequential chart of the L picture 990 of this Figure 13 are same as sequential chart shown in Figure 7.Figure 15 is according to the sequential chart of Fig. 7 relevant write operation method list with the L picture that produces Figure 13.As Fig. 7 and shown in Figure 15, in first period of first period of first group of period, second group of period, and first period of the 3rd group of period, common voltage Vcom is set as first voltage (low-voltage), and in second period of second period of first group of period, second group of period, and second period of the 3rd group of period, common voltage Vcom is set as second voltage (high voltage).

In Fig. 7 and write operation shown in Figure 15, continuous mutually sub-period Td1-Td3 in first period of first group of period, many odd gates line GL1, GL3 that enable first group of gate line in regular turn according to putting in order of increasing progressively and a plurality of corresponding signal SGL1, SGL3 and the SGL5 of GL5, write a plurality of pixel cells 970 with odd number ordering of corresponding odd-numbered line pixel cell in order to a plurality of data-signals that will have positive polarity, and a plurality of data-signals that will have positive polarity write a plurality of pixel cells 970 with even number ordering of corresponding even number line pixel cell.Continuous mutually sub-period Td4-Td6 in second period of first group of period, many even number gate lines G L2, GL4 that enable first group of gate line in regular turn according to putting in order of increasing progressively and a plurality of corresponding signal SGL2, SGL4 and the SGL6 of GL6, write a plurality of pixel cells 970 with odd number ordering of corresponding even number line pixel cell in order to a plurality of data-signals that will have negative polarity, and a plurality of data-signals that will have a negative polarity write a plurality of pixel cells 970 with even number ordering of corresponding odd-numbered line pixel cell.

Continuous mutually sub-period Td1-Td3 in first period of second group of period, many odd gates line GL11, GL9 that enable second group of gate line in regular turn according to putting in order of successively decreasing and a plurality of corresponding signal SGL11, SGL9 and the SGL7 of GL7, write a plurality of pixel cells 970 with odd number ordering of corresponding odd-numbered line pixel cell in order to a plurality of data-signals that will have positive polarity, and a plurality of data-signals that will have a negative polarity write a plurality of pixel cells 970 with even number ordering of corresponding even number line pixel cell.Continuous mutually sub-period Td4-Td6 in second period of second group of period, many even number gate lines G L12, GL10 that enable second group of gate line in regular turn according to putting in order of successively decreasing and a plurality of corresponding signal SGL12, SGL10 and the SGL8 of GL8, write a plurality of pixel cells 970 with odd number ordering of corresponding even number line pixel cell in order to a plurality of data-signals that will have negative polarity, and a plurality of data-signals that will have a negative polarity write a plurality of pixel cells 970 with even number ordering of corresponding odd-numbered line pixel cell.

Please note, though in the write operation of the sub-period Td1 of first period of first group of period shown in Figure 15, only describe a plurality of pixel cells 970 that a plurality of data-signals that will have positive polarity write the first row pixel cell, but can comprise a plurality of pixel cells that a plurality of data-signals that will have positive polarity write last column pixel cell (even number line pixel cell) or secondary row pixel cell in addition with even number ordering with odd number ordering.The invention described above the 6th embodiment based on a method for driving liquid crystal display of inversion driving pattern in, the signal of adjacent gate polar curve group enables order for oppositely, so can reduce group's moire effect of the boundary pixel unit of adjacent gate polar curve group.In like manner, the data-signal of the data-signal of each pixel cell of the L+1 picture that is produced according to the invention described above the 6th embodiment and the respective pixel unit of L picture 990 is an opposite polarity, promptly in the driving operation of L+1 picture, first voltage of common voltage Vcom is set as high voltage, and second voltage of common voltage Vcom is set as low-voltage, and be negative polarity, and be positive polarity corresponding to the data-signal that second voltage of common voltage Vcom is write corresponding to the data-signal that first voltage of common voltage Vcom is write.

Figure 16 is for using another liquid crystal indicator synoptic diagram of the present invention's row inversion driving method.As shown in figure 16, liquid crystal indicator 10 comprises many data lines 16, many gate lines 15, many memory capacitance common electrode lines 18, many liquid crystal capacitance common electrode lines 19 and multirow pixel, wherein many gate lines 15 are divided into many group gate lines, and many memory capacitance common electrode lines 18 also can be divided into many group memory capacitance common electrode lines accordingly.In liquid crystal indicator 10, with 6 adjacent gate lines is one group of gate line, for example first to the 6th gate lines G L1-GL6 is first group of gate line, article the 7th to 12, gate lines G L7-GL12 is second group of gate line, so corresponding first to the 6th memory capacitance common electrode line LST1-LST6 is first group of memory capacitance common electrode line, and the 7th to the 12 memory capacitance common electrode line LST7-LST12 is second group of memory capacitance common electrode line.Each row pixel comprises a plurality of pixels 14, and each pixel 14 comprises three pixel cells 20.Each pixel cell 20 is red pixel unit, green pixel unit or blue pixel unit.Each pixel cell 20 comprises data switch 21, liquid crystal capacitance 23, reaches memory capacitance 25.Each liquid crystal capacitance 23 all is coupled to liquid crystal capacitance common electrode line 19 to receive liquid crystal capacitance common voltage Vclc.Memory capacitance 25 with delegation is coupled to identical memory capacitance common electrode line 18, in order to receive corresponding stored electric capacity common voltage, for example a plurality of memory capacitance 25 of first row all are coupled to memory capacitance common electrode line LST1 to receive memory capacitance common voltage Vcst_1, and a plurality of memory capacitance 25 of the third line all are coupled to memory capacitance common electrode line LST3 to receive memory capacitance common voltage Vcst_3.

Figure 17 is signal and a memory capacitance common voltage sequential chart of carrying out the row reverse turn operation according to the liquid crystal indicator of Figure 16, wherein transverse axis is a time shaft, the data-signal that positive sign representative in the bracket is write is a positive polarity, and the data-signal that the negative sign representative in the bracket is write is a negative polarity.As shown in figure 17, in the K picture, in first period of first group of period, first group of odd number memory capacitance common voltage Vcst_1, Vcst_3 and Vcst_5 are set to low level earlier, the signal SGL1 of the odd gates line of first group of gate line, SGL3 and SGL5, be enabled in regular turn by incremental order, and in regular turn a plurality of data-signals of positive polarity are write to a plurality of pixel cells 20 via many data lines 16, when the signal that is enabled after corresponding write operation is finished, corresponding memory capacitance common voltage can switch to high level from low level, and the positive polarity data signal voltage level that can will just write this moment by the capacity effect of corresponding stored electric capacity 25 upwards promotes again.In second period of first group of period, first group of even stored electric capacity common voltage Vcst_2, Vcst_4 and Vcst_6 are set to high level earlier, the signal SGL2 of the even number gate line of first group of gate line, SGL4 and SGL6, be enabled in regular turn by incremental order, and in regular turn a plurality of data-signals of negative polarity are write to a plurality of pixel cells 20 via many data lines 16, when the signal that is enabled after corresponding write operation is finished, corresponding memory capacitance common voltage can switch to low level from high level, and the negative polarity data signal voltage level that can will just write this moment by the capacity effect of corresponding stored electric capacity 25 reduces downwards again.

In the K picture, in first period of second group of period, second group of odd number memory capacitance common voltage Vcst_7, Vcst_9 and Vcst_11 are set to low level earlier, the signal SGL7 of the odd gates line of second group of gate line, SGL9 and SGL11, be enabled in regular turn by incremental order, and in regular turn a plurality of data-signals of positive polarity are write to a plurality of pixel cells 20 via many data lines 16, when the signal that is enabled after corresponding write operation is finished, corresponding memory capacitance common voltage can switch to high level from low level, and the positive polarity data signal voltage level that can will just write this moment by the capacity effect of corresponding stored electric capacity 25 upwards promotes again.In second period of second group of period, second group of even stored electric capacity common voltage Vcst_8, Vcst_10 and Vcst_12 are set to high level earlier, the signal SGL8 of the even number gate line of second group of gate line, SGL10 and SGL12, be enabled in regular turn by incremental order, and in regular turn a plurality of data-signals of negative polarity are write to a plurality of pixel cells 20 via many data lines 16, when the signal that is enabled after corresponding write operation is finished, corresponding memory capacitance common voltage can switch to low level from high level, and the negative polarity data signal voltage level that can will just write this moment by the capacity effect of corresponding stored electric capacity 25 reduces downwards again.

In the K+1 picture, in first period of first group of period, signal SGL1, SGL3 and the SGL5 of the odd gates line of first group of gate line, be enabled in regular turn by incremental order, and in regular turn a plurality of data-signals of negative polarity are write to a plurality of pixel cells 20 via many data lines 16, when the signal that is enabled after corresponding write operation is finished, corresponding memory capacitance common voltage can switch to low level from high level, and the negative polarity data signal voltage level that can will just write this moment by the capacity effect of corresponding stored electric capacity 25 reduces downwards again.In second period of first group of period, signal SGL2, SGL4 and the SGL6 of the even number gate line of first group of gate line, be enabled in regular turn by incremental order, and in regular turn a plurality of data-signals of positive polarity are write to a plurality of pixel cells 20 via many data lines 16, when the signal that is enabled after corresponding write operation is finished, corresponding memory capacitance common voltage can switch to high level from low level, and the positive polarity data signal voltage level that can will just write this moment by the capacity effect of corresponding stored electric capacity 25 upwards promotes again.

In the K+1 picture, in first period of second group of period, signal SGL7, SGL9 and the SGL11 of the odd gates line of second group of gate line, be enabled in regular turn by incremental order, and in regular turn a plurality of data-signals of negative polarity are write to a plurality of pixel cells 20 via many data lines 16, when the signal that is enabled after corresponding write operation is finished, corresponding memory capacitance common voltage can switch to low level from high level, and the negative polarity data signal voltage level that can will just write this moment by the capacity effect of corresponding stored electric capacity 25 reduces downwards again.In second period of second group of period, signal SGL8, SGL10 and the SGL12 of the even number gate line of second group of gate line, be enabled in regular turn by incremental order, and in regular turn a plurality of data-signals of positive polarity are write to a plurality of pixel cells 20 via many data lines 16, when the signal that is enabled after corresponding write operation is finished, corresponding memory capacitance common voltage can switch to high level from low level, and the positive polarity data signal voltage level that can will just write this moment by the capacity effect of corresponding stored electric capacity 25 upwards promotes again.

In other words, utilize the voltage that capacity effect caused of memory capacitance 25 to promote or the reduction effect, can thereby dwindle via the required voltage level amplitude of oscillation of data-signal that data line 16 writes.So in the handoff procedure of both positive and negative polarity gray scale voltage, with regard to cpable of lowering power consumption, and the component pressure specification of liquid crystal indicator driving circuit also can reduce, can use low withstand voltage element to reduce cost.

Figure 18 is for using another liquid crystal indicator synoptic diagram of pixel inversion driving method of the present invention.As shown in figure 18, liquid crystal indicator 30 comprises many data lines 36, many gate lines 35, many memory capacitance common electrode lines 38, many liquid crystal capacitance common electrode lines 39 and multirow pixel, wherein many gate lines 35 are divided into many group gate lines, and many memory capacitance common electrode lines 38 also can be divided into many group memory capacitance common electrode lines accordingly.Each row pixel comprises a plurality of pixels 34, and each pixel 34 comprises three pixel cells 40.Each pixel cell 40 is red pixel unit, green pixel unit or blue pixel unit.Each pixel cell 40 comprises data switch 41, liquid crystal capacitance 43, reaches memory capacitance 45.Each liquid crystal capacitance 43 all is coupled to liquid crystal capacitance common electrode line 39 to receive liquid crystal capacitance common voltage Vclc.

The memory capacitance 45 of three pixel cells 40 of each pixel 34 is coupled in same memory capacitance common electrode line 38, but is coupled in two different and adjacent memory capacitance common electrode lines 38 with the memory capacitance 45 of adjacent two pixels 34 of delegation.Signal and memory capacitance common voltage sequential chart that liquid crystal indicator 30 is carried out the pixel inversion operation are analogous to sequential chart shown in Figure 17.For example, in same picture, when signal SGLn is enabled, the N a plurality of staggered pixels 34 capable and that N-1 is capable that then are coupled to gate lines G Ln can be written into the first polarity data signal, thereafter when signal SGLn+1 is enabled, the N a plurality of staggered pixels 34 capable and that N+1 is capable that then are coupled to gate lines G Ln+1 can be written into the second polarity data signal, and wherein the polarity of first polarity and second polarity is opposite, so just can produce the display frame with pixel inversion.

Figure 19 puts another liquid crystal indicator synoptic diagram of inversion driving method for using the present invention.As shown in figure 19, liquid crystal indicator 50 comprises many data lines 56, many gate lines 55, many memory capacitance common electrode lines 58, many liquid crystal capacitance common electrode lines 59 and multirow pixel, wherein many gate lines 55 are divided into many group gate lines, and many memory capacitance common electrode lines 58 also can be divided into many group memory capacitance common electrode lines accordingly.Each row pixel comprises a plurality of pixels 54, and each pixel 54 comprises three pixel cells 60.Each pixel cell 60 is red pixel unit, green pixel unit or blue pixel unit.Each pixel cell 60 comprises data switch 61, liquid crystal capacitance 63, reaches memory capacitance 65.Each liquid crystal capacitance 63 all is coupled to liquid crystal capacitance common electrode line to receive liquid crystal capacitance common voltage Vclc.

Memory capacitance 65 with adjacent two pixel cells 60 of delegation is coupled in two different and adjacent memory capacitance common electrode lines 58.Signal and memory capacitance common voltage sequential chart that liquid crystal indicator 50 is carried out point reverse turn operation are analogous to sequential chart shown in Figure 17.For example, in same picture, when signal SGLn is enabled, the a plurality of staggered pixels unit 60 that N is capable and N-1 is capable that then is coupled to gate lines G Ln can be written into the first polarity data signal, thereafter when signal SGLn+1 is enabled, the a plurality of staggered pixels unit 60 that N is capable and N+1 is capable that then is coupled to gate lines G Ln+1 can be written into the second polarity data signal, and wherein the polarity of first polarity and second polarity is opposite, so just can produce the display frame with counter-rotating.

Above-mentioned relevant drive signals according to Figure 17 with the method for operating of carrying out capable counter-rotating, pixel inversion or some counter-rotating in, the liquid crystal capacitance common voltage is the direct current fixed level, the memory capacitance common voltage then is divided into many groups, each group memory capacitance common voltage is more respectively with corresponding to even number line and odd-numbered line interlace mode, the low common voltage of feed-in reaches the high common voltage of feed-in when writing the negative polarity data-signal when writing the positive polarity data-signal.Compared to the common voltage driving method of known reverse turn operation, can reduce the switching frequency of common voltage.In addition, no matter be row inversion driving pattern, pixel inversion drive pattern or some inversion driving pattern, voltage level by the memory capacitance common voltage switches, cooperate the voltage that capacity effect caused of memory capacitance to promote or the reduction effect, can reduce the required voltage swing of positive-negative polarity gray scale voltage of source electrode drive circuit output significantly, can reduce the required power consumption of positive-negative polarity gray scale voltage handoff procedure, and the withstand voltage scope of element that source electrode drive circuit uses also can reduce, so liquid crystal indicator just can use low withstand voltage element to reduce cost.

Figure 20 is for carrying out the row reverse turn operation to produce the work coherent signal sequential chart of J picture and J+1 picture according to the liquid crystal indicator of Fig. 4, and wherein transverse axis is a time shaft.In following explanation, when the odd-numbered line pixel cell of J picture and even number line pixel cell have positive polarity and negative polarity data-signal respectively, then the odd-numbered line pixel cell of J+x picture and even number line pixel cell have negative polarity and positive polarity data-signal respectively, the odd-numbered line pixel cell of J+y picture and even number line pixel cell have positive polarity and negative polarity data-signal respectively, wherein x is an odd number, and y is an even number.In Figure 20, basipetal signal is respectively common voltage Vcom corresponding to the J picture, the common voltage Vcom corresponding to the J+1 picture, the first auxiliary grid signal SGx1, the second auxiliary grid signal SGx2, and a plurality of signal SGL1-SGL12.

As shown in figure 20, in first period of first group of period, setting common voltage Vcom earlier is first common voltage, enable the first auxiliary grid signal SGx1 to write auxiliary data signal with first polarity, setting common voltage Vcom again is second common voltage, enable the second auxiliary grid signal SGx1 to write auxiliary data signal with second polarity, thereafter setting common voltage Vcom again is first common voltage, enable the signal SGL1 of the odd gates line of first group of gate line according to incremental order, SGL3 and SGL5, and according to the signal that is enabled in regular turn, the data-signal that will have first polarity in regular turn writes the multirow pixel.When first polarity was positive polarity, second polarity was negative polarity, and second common voltage is greater than first common voltage.When first polarity was negative polarity, second polarity was positive polarity, and second common voltage is less than first common voltage.When first polarity corresponding to the J picture is positive polarity, be negative polarity corresponding to first polarity of J+1 picture, vice versa.

In second period of first group of period, setting common voltage Vcom is second common voltage, enable signal SGL2, SGL4 and the SGL6 of the even number gate line of first group of gate line according to incremental order, and according to the signal that is enabled in regular turn, the data-signal that will have second polarity in regular turn writes the multirow pixel.In first period of second group of period, setting common voltage Vcom is first common voltage, enable signal SGL7, SGL9 and the SGL11 of the odd gates line of second group of gate line according to incremental order, and according to the signal that is enabled in regular turn, the data-signal that will have first polarity in regular turn writes the multirow pixel.In second period of second group of period, setting common voltage Vcom is second common voltage, enable signal SGL8, SGL10 and the SGL12 of the even number gate line of second group of gate line according to incremental order, and according to the signal that is enabled in regular turn, the data-signal that will have second polarity in regular turn writes the multirow pixel.

Figure 21 is for carrying out the row reverse turn operation to produce the work coherent signal sequential chart of J+2 picture and J+3 picture according to the liquid crystal indicator of Fig. 4, and wherein transverse axis is a time shaft.In Figure 21, basipetal signal is respectively common voltage Vcom corresponding to the J+2 picture, the common voltage Vcom corresponding to the J+3 picture, the first auxiliary grid signal SGx1, the second auxiliary grid signal SGx2, and a plurality of signal SGL1-SGL14.As shown in figure 21, in first period of first group of period, setting common voltage Vcom earlier is first common voltage, enable the first auxiliary grid signal SGx1 and signal SGL1 in regular turn, reach and write auxiliary data signal and a plurality of first line data signal in regular turn with first polarity, setting common voltage Vcom again is second common voltage, enable the second auxiliary grid signal SGx2 and signal SGL2 in regular turn, reach and write auxiliary data signal and a plurality of second line data signal in regular turn with second polarity, thereafter setting common voltage Vcom again is first common voltage, put in order according to increasing progressively of first group of gate line, the 3rd gate lines G L3 since first group of gate line, enable the signal SGL3 and the SGL5 of the odd gates line of first group of gate line in regular turn, the last signal SGL7 that enables article one gate lines G L7 of second group of gate line again, and according to the signal that is enabled in regular turn, the data-signal that will have first polarity in regular turn writes the multirow pixel.

In second period of first group of period, setting common voltage Vcom is second common voltage, put in order according to increasing progressively of first group of gate line, the 4th gate lines G L4 since first group of gate line, enable the signal SGL4 and the SGL6 of the even number gate line of first group of gate line in regular turn, the last signal SGL8 that enables the second gate lines G L8 of second group of gate line again, and according to the signal that is enabled in regular turn, the data-signal that will have second polarity in regular turn writes the multirow pixel.In first period of second group of period, setting common voltage Vcom is first common voltage, put in order according to increasing progressively of second group of gate line, the 3rd gate lines G L9 since second group of gate line, enable the signal SGL9 and the SGL11 of the odd gates line of second group of gate line in regular turn, the last signal SGL13 that enables article one gate lines G L13 of the 3rd group of gate line again, and according to the signal that is enabled in regular turn, the data-signal that will have first polarity in regular turn writes the multirow pixel.In second period of second group of period, setting common voltage Vcom is second common voltage, put in order according to increasing progressively of second group of gate line, the 4th gate lines G L10 since second group of gate line, enable the signal SGL10 and the SGL12 of the even number gate line of second group of gate line in regular turn, the last signal SGL14 that enables the second gate lines G L14 of the 3rd group of gate line again, and according to the signal that is enabled in regular turn, the data-signal that will have second polarity in regular turn writes the multirow pixel.

Figure 22 is for carrying out the row reverse turn operation to produce the work coherent signal sequential chart of J+4 picture and J+5 picture according to the liquid crystal indicator of Fig. 4, and wherein transverse axis is a time shaft.In Figure 22, basipetal signal is respectively common voltage Vcom corresponding to the J+4 picture, the common voltage Vcom corresponding to the J+5 picture, the first auxiliary grid signal SGx1, the second auxiliary grid signal SGx2, and a plurality of signal SGL1-SGL10.In first period of first group of period, setting common voltage Vcom is first common voltage, enable the first auxiliary grid signal SGx1 earlier and write auxiliary data signal with first polarity, put in order according to increasing progressively of first group of gate line again, enable the signal SGL1 and the SGL3 of the odd gates line of first group of gate line in regular turn, till fourth from the last bar gate lines G L3, and according to the signal that is enabled in regular turn, the data-signal that will have first polarity in regular turn writes the multirow pixel.

In second period of first group of period, setting common voltage Vcom is second common voltage, enable the second auxiliary grid signal SGx2 earlier and write auxiliary data signal with second polarity, put in order according to increasing progressively of first group of gate line again, enable the signal SGL2 and the SGL4 of the even number gate line of first group of gate line in regular turn, till third from the bottom gate lines G L4, and according to the signal that is enabled in regular turn, the data-signal that will have second polarity in regular turn writes the multirow pixel.In first period of second group of period, setting common voltage Vcom is first common voltage, enable the signal SGL5 of the second from the bottom gate line of first group of gate line earlier, put in order according to increasing progressively of second group of gate line again, enable the signal SGL7 and the SGL9 of the odd gates line of second group of gate line in regular turn, till fourth from the last bar gate lines G L9, and according to the signal that is enabled in regular turn, the data-signal that will have first polarity in regular turn writes the multirow pixel.In second period of second group of period, setting common voltage Vcom is second common voltage, enable the signal SGL6 of last gate lines G L6 of first group of gate line earlier, put in order according to increasing progressively of second group of gate line again, enable the signal SGL8 and the SGL10 of the even number gate line of second group of gate line in regular turn, till third from the bottom gate lines G L10, and according to the signal that is enabled in regular turn, the data-signal that will have first polarity in regular turn writes the multirow pixel.

Basically, above-mentioned relevant drive signals according to the 20th to 22 figure with the method for carrying out capable reverse turn operation in, utilize the first auxiliary grid signal SGx1 and the second auxiliary grid signal SGx2 in first period or second period that continue first group of period of picture mutually, sneak into the signal enable operation of first group of gate line by different way, and influence the enable operation of subsequent gate signal, make first period of respectively organizing the period or the signal enable operation of second period be not limited to a certain group of gate line, that is to say that a plurality of signals that are enabled in the same period can comprise not the signal of gate line on the same group.So above-mentioned relevant drive signals according to the 20th to 22 figure with the method for carrying out capable reverse turn operation in, the driving edge gate line of the day part of continuous picture is all also different mutually, so can reduce the moire effect (Mura effect) that the edge gate line by every group of gate line is caused, in order to improve picture quality.In one embodiment, the circuit structure of the liquid crystal indicator 400 of Fig. 4 can comprise the first supplementary gate polar curve, the second supplementary gate polar curve, the first secondary row pixel and the second secondary row pixel in addition, in order to the write operation according to the first auxiliary grid signal SGx1 and second auxiliary grid signal SGx2 execution auxiliary data signal.In another embodiment, the circuit structure of the liquid crystal indicator 400 of Fig. 4 can not comprise the first above-mentioned supplementary gate polar curve, the second supplementary gate polar curve, the first secondary row pixel and the second secondary row pixel, and the first auxiliary grid signal SGx1, the second auxiliary grid signal SGx2 and auxiliary data signal are the virtual signal that driving circuit is carried out signal Processing.

From the above, according to liquid crystal display apparatus driving circuit of the present invention, many gate lines are divided into many group gate lines, enable the odd gates line or the even number gate line of each group gate line respectively in regular turn with the increasing or decreasing order, and write the positive polarity data and write the negative polarity data with high common voltage with low common voltage, no matter so be row inversion driving pattern, the pixel inversion drive pattern, or some inversion driving pattern, all can reduce the signal voltage drift difference and the reduction full frame gradient luminance error of the data-signal of adjacent lines, simultaneously also moire effect can be reduced, therefore picture quality can be significantly improved.In addition, in addition can be in order to reduce the required voltage swing of positive-negative polarity gray scale voltage of source electrode drive circuit output, can reduce the required power consumption of positive-negative polarity gray scale voltage handoff procedure, and the withstand voltage scope of element that source electrode drive circuit uses also can reduce, so liquid crystal indicator just can use low withstand voltage element to reduce cost.

Though the present invention with embodiment openly as above; yet it is not in order to limit the present invention; any those of ordinary skills; without departing from the spirit and scope of the present invention; when can doing various changes and retouching, so protection scope of the present invention is as the criterion when looking the scope that claim defined of enclosing.

Claims

1. method based on inversion driving mode activated liquid crystal indicator includes the multirow pixel, organizes this liquid crystal indicators of gate line and many data lines more in order to driving, and this method comprises:

One first period in one first group of period puts in order according to increasing progressively, and enables a plurality of signals of many odd gates lines of this one first group of gate line organizing gate lines in regular turn more;

One second period in this first group of period puts in order according to increasing progressively, and enables a plurality of signals of many even number gate lines of this first group of gate line in regular turn;

Yu Xiangxu put in order according to successively decreasing in one first period of one second group of period of this first group of period, enabled a plurality of signals of many even number gate lines of this one second group of gate line organizing gate lines in regular turn more; And

One second period in this second group of period puts in order according to successively decreasing, and enables a plurality of signals of many odd gates lines of this second group of gate line in regular turn;

Wherein adjacent corresponding to this first group of gate line of this first group of period and this second group of gate line corresponding to this second group of period, and the number of the gate line that comprises of second group of gate line of this first group of gate line and this equates,

Wherein first period of this first group of period and second period do not overlap each other, and first period of this second group of period and second period do not overlap each other.

2. the method for claim 1, wherein:

In first period of this first group of period, a plurality of signals of many odd gates lines that enabled in regular turn according to this first group of gate line, a plurality of data-signals that will have one first polarity in regular turn write the multirow pixel of this liquid crystal indicator via described many data lines; And

In second period of this first group of period, a plurality of signals of many even number gate lines that enabled in regular turn according to this first group of gate line, a plurality of data-signals that will have one second polarity in regular turn write the multirow pixel of this liquid crystal indicator via described many data lines.

3. method as claimed in claim 2, wherein:

In first period corresponding to this first group of period of a N picture, set a liquid crystal capacitance common voltage and a memory capacitance common voltage is one first common voltage, wherein N is the sequence number of current picture; And

In second period, set this liquid crystal capacitance common voltage and this memory capacitance common voltage is one second common voltage corresponding to this first group of period of this N picture;

Wherein this first common voltage is different from this second common voltage, and the polarity of this first polarity and this second polarity is opposite, corresponding to first period of this first group of period of this N picture before second period.

4. method as claimed in claim 3, wherein this first polarity is positive polarity, this second polarity is negative polarity, and this second common voltage is greater than this first common voltage.

5. method as claimed in claim 3, wherein this first polarity is negative polarity, this second polarity is positive polarity, and this second common voltage is less than this first common voltage.

6. method as claimed in claim 3, wherein:

In being continued mutually corresponding to this N picture in first period of this second group of period of this first group of period, put in order according to successively decreasing of this second group of gate line, enable a plurality of signals of many even number gate lines of this second group of gate line in regular turn adjacent to this first group of gate line;

In first period corresponding to this second group of period of this N picture, a plurality of signals of many even number gate lines that enabled in regular turn according to this second group of gate line, a plurality of data-signals that will have this second polarity in regular turn write the multirow pixel of this liquid crystal indicator via described many data lines;

Second period in corresponding to this second group of period of this N picture puts in order according to successively decreasing of this second group of gate line, enables a plurality of signals of many odd gates lines of this second group of gate line in regular turn; And

In second period corresponding to this second group of period of this N picture, a plurality of signals of many odd gates lines that enabled in regular turn according to this second group of gate line, a plurality of data-signals that will have this first polarity in regular turn write the multirow pixel of this liquid crystal indicator via described many data lines.

7. method as claimed in claim 6 also comprises:

In corresponding to being continued mutually of this N picture, set this liquid crystal capacitance common voltage and this memory capacitance common voltage is this second common voltage in first period of this second group of period of this first group of period; And

In second period, set this liquid crystal capacitance common voltage and this memory capacitance common voltage is this first common voltage corresponding to this second group of period of this N picture;

Wherein corresponding to first period of this second group of period of this N picture before second period.

8. method as claimed in claim 6 also comprises:

In being continued mutually corresponding to this N picture in one first period of one the 3rd group of period of this second group of period, put in order according to one the 3rd group of increasing progressively of gate line adjacent to this second group of gate line, enable a plurality of signals of many odd gates lines of the 3rd group of gate line in regular turn, and according to the described a plurality of signals that enabled in regular turn, a plurality of data-signals that will have this first polarity in regular turn write the multirow pixel of this liquid crystal indicator via described many data lines; And

In one second period corresponding to the 3rd group of period of this N picture, put in order according to the 3rd group of increasing progressively of gate line, enable a plurality of signals of many even number gate lines of the 3rd group of gate line in regular turn, and according to the described a plurality of signals that enabled in regular turn, a plurality of data-signals that will have this second polarity in regular turn write the multirow pixel of this liquid crystal indicator via described many data lines;

Wherein corresponding to first period of the 3rd group of period of this N picture before second period.

9. method as claimed in claim 6 also comprises:

In being continued mutually corresponding to this N picture in one first period of one the 3rd group of period of this second group of period, set this liquid crystal capacitance common voltage and this memory capacitance common voltage is this first common voltage, put in order according to one the 3rd group of increasing progressively of gate line adjacent to this second group of gate line, enable a plurality of signals of many odd gates lines of the 3rd group of gate line in regular turn, and according to the described a plurality of signals that enabled in regular turn, a plurality of data-signals that will have this first polarity in regular turn write the multirow pixel of this liquid crystal indicator via described many data lines; And

In one second period corresponding to the 3rd group of period of this N picture, set this liquid crystal capacitance common voltage and this memory capacitance common voltage is this second common voltage, put in order according to the 3rd group of increasing progressively of gate line, enable a plurality of signals of many even number gate lines of the 3rd group of gate line in regular turn, and according to the described a plurality of signals that enabled in regular turn, a plurality of data-signals that will have this second polarity in regular turn write the multirow pixel of this liquid crystal indicator via described many data lines;

10. the method for claim 1, wherein:

In first period corresponding to this first group of period of a N+1 picture, put in order according to one first group of increasing progressively of gate line in these many group gate lines, enable a plurality of signals of many odd gates lines of this first group of gate line in regular turn;

In second period corresponding to this first group of period of this N+1 picture, put in order according to one first group of increasing progressively of gate line in these many group gate lines, enable a plurality of signals of many even number gate lines of this first group of gate line in regular turn;

Wherein corresponding to first period of this first group of period of this N+1 picture before second period.

11. the method for claim 1, wherein:

Setting a liquid crystal capacitance common voltage is a liquid crystal voltage;

In first period of this first group of period, first group of odd number memory capacitance common voltage is set to one first storage voltage earlier, a plurality of signals of many odd gates lines that enabled in regular turn according to this first group of gate line, a plurality of data-signals that will have one first polarity in regular turn write the multirow pixel of this liquid crystal indicator via described many data lines, when a plurality of signals of many odd gates lines of this first group of gate line were finished respectively at corresponding data write operation, this first group of odd number memory capacitance common voltage was switched to one second storage voltage;

In second period of this first group of period, first group of even stored electric capacity common voltage is set to described second storage voltage earlier, a plurality of signals of many even number gate lines that enabled in regular turn according to this first group of gate line, a plurality of data-signals that will have one second polarity in regular turn write the multirow pixel of this liquid crystal indicator via described many data lines, when a plurality of signals of many even number gate lines of this first group of gate line were finished respectively at corresponding data write operation, this first group of even stored electric capacity common voltage was switched to described first storage voltage.

12. method as claimed in claim 11, wherein this first polarity is positive polarity, and this second polarity is negative polarity, and this second storage voltage is greater than this first storage voltage.

13. method as claimed in claim 11, wherein this first polarity is negative polarity, and this second polarity is positive polarity, and this second storage voltage is less than this first storage voltage.