CN101286505A - Semi-conductor encapsulation structure having an antenna - Google Patents
Semi-conductor encapsulation structure having an antenna Download PDFInfo
- Publication number
- CN101286505A CN101286505A CN 200810099853 CN200810099853A CN101286505A CN 101286505 A CN101286505 A CN 101286505A CN 200810099853 CN200810099853 CN 200810099853 CN 200810099853 A CN200810099853 A CN 200810099853A CN 101286505 A CN101286505 A CN 101286505A
- Authority
- CN
- China
- Prior art keywords
- chip
- antenna
- substrate
- semiconductor package
- adhesive material
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
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Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
- H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
Landscapes
- Wire Bonding (AREA)
Abstract
The invention relates to a semiconductor packaging structure with an antenna, which comprises a substrate, a chip, a sealing compound material and an antenna, wherein, the substrate is provided with a first surface and a second surface; the chip is positioned on the first surface of the substrate and electrically connected to the substrate; the sealing compound material completely or partially covers the chip; the antenna is positioned on the sealing compound material and electrically connected to the chip. As the area of the sealing compound material is very large, the needed antenna can be easily placed on the sealing compound material without occupying the area of the substrate.
Description
Technical field
The invention relates to a kind of semiconductor package, in detail, is to be positioned at semiconductor package on the adhesive material about a kind of antenna.
Background technology
In wireless communication module, compact is very tangible trend at present, and the designer tries every possible means invariably more assembly is integrated in the same encapsulating structure.Yet the area shared owing to antenna is bigger usually, so be difficult to be integrated in the encapsulating structure.The common practice is that dwi hastasana is formed on the substrate in the encapsulating structure, yet, owing to also will put other assembly on this substrate, therefore can promptly be restricted for the area that forms this antenna.
Therefore, be necessary to provide the semiconductor package with antenna of a kind of innovation and tool progressive, to address the above problem.
Summary of the invention
The invention provides a kind of semiconductor package with antenna, it comprises a substrate, a chip, an adhesive material and an antenna.This substrate has a first surface and a second surface.This chip is the first surface that is positioned at this substrate, and is electrically connected to this substrate.This adhesive material coats all or part of this chip.This antenna is to be positioned on this adhesive material, and is electrically connected to this chip.By this,, therefore can place this required antenna easily, and can not take the area of this substrate because the area of this adhesive material is very big, therefore can be in this semiconductor package and do not increase package dimensions originally with aerial integration.In addition, this antenna is to expose to outside this adhesive material, and it can increase the benefit of this antenna.
Description of drawings
Fig. 1 shows that the present invention has the cross-sectional schematic of first embodiment of the semiconductor package of antenna;
Fig. 2 shows that the present invention has the cross-sectional schematic of second embodiment of the semiconductor package of antenna;
Fig. 3 shows that the present invention has the schematic top plan view of second embodiment of the semiconductor package of antenna; And
Fig. 4 shows that the present invention has the cross-sectional schematic of the 3rd embodiment of the semiconductor package of antenna.
Embodiment
With reference to figure 1, show that the present invention has the cross-sectional schematic of first embodiment of the semiconductor package of antenna.This semiconductor package 1 comprises a substrate 11, a chip 12, an adhesive material 13, an antenna 14 and several soldered balls 15.This substrate 11 has a first surface 111 and a second surface 112.This chip 12 is positioned at the first surface 111 of this substrate 11, and is electrically connected to this substrate 11.In the present embodiment, this chip 12 has an active surface 121, a back side 122, a line layer and at least one chip perforating holes (Through Silicon Via, TSV) 124.This line layer is to be positioned at this active surface 121.This active surface 121 is to cover the first surface 111 that crystal type is engaged to this substrate 11.This chip perforating holes 124 is to connect this back side 121 and this line layer.
This this chip 12 of adhesive material 13 covered sections.In the present embodiment, this adhesive material 13 has an opening 131, with the part at the back side 122 that manifests this chip 12.This antenna 14 (a for example RF antenna) is to be positioned on this adhesive material 13, and is electrically connected to this chip 12.This antenna 14 for example is a discontinuous pattern metal level, and its material for example is copper or aluminium.In the present embodiment, this antenna 14 is plating (coating) or attaches on this adhesive material 13 and in this opening 131, make that this antenna 14 is the back side 122 and this chip perforating holes 124 of this chip 12 of contact, and can electrically connect by this chip perforating holes 124 and this substrate 11.Be noted that this antenna 14 can extend to the side of this adhesive material 13, however this antenna 14 not physics contact this substrate 11.Described soldered ball 15 is the second surfaces 112 that are positioned at this substrate 11.
In the present invention, because the area of this adhesive material 13 is very big, therefore can place this required antenna 14 easily, and can not take the area of this substrate 11, therefore this antenna 14 can be integrated in this semiconductor package 1 and not increase package dimensions originally.In addition, this antenna 14 is to expose to outside this adhesive material 13, and it can increase the benefit of this antenna 14.
With reference to figure 2 and Fig. 3, show that respectively the present invention has the analysing and observe and schematic top plan view of second embodiment of the semiconductor package of antenna.This semiconductor package 2 comprises a substrate 21, a chip 22, several wires 26, an adhesive material 23, an antenna 24 and several soldered balls 25.This substrate 21 has a first surface 211 and a second surface 212.This chip 22 is positioned at the first surface 211 of this substrate 21, and is electrically connected to this substrate 21.In the present embodiment, this chip 22 has an active surface 221, a back side 222, several chip pad 223 and a rerouting layer (Redistribution Layer, RDL) 224.Described chip pad 223 and this rerouting layer 224 are to be positioned at this active surface 221.This back side 222 is to utilize a viscose 225 to attach to the first surface 211 of this substrate 21.Described lead 26 electrically connects the first surface 211 of described chip pad 223 to this substrate 21.
This this chip 22 of adhesive material 23 covered sections.In the present embodiment, this adhesive material 23 has an opening 231, to manifest the part active surface 221 of this chip 22.This antenna 24 is to be positioned on this adhesive material 23, and is electrically connected to this chip 22.This antenna 24 for example is a discontinuous pattern metal level.In the present embodiment, this antenna 24 is plating (Coating) or attaches on this adhesive material 23 and in this opening 231, makes that this antenna 24 is active surfaces 221 of this chip 22 of contact, and utilizes this rerouting layer 224 to be electrically connected to described chip pad 223.Described soldered ball 25 is the second surfaces 212 that are positioned at this substrate 21.
With reference to figure 4, show that the present invention has the cross-sectional schematic of the 3rd embodiment of the semiconductor package of antenna.This semiconductor package 3 comprises a substrate 31, a chip 32, an adhesive material 33, an antenna 34 and several soldered balls 35.This substrate 31 has a first surface 311 and a second surface 312.This chip 32 is positioned at the first surface 311 of this substrate 31, and is electrically connected to this substrate 31.In the present embodiment, this chip 32 has an active surface 321, a back side 322, a line layer and at least one chip perforating holes (Through Silicon Via, TSV) 324.This line layer is to be positioned at this active surface 321.This active surface 321 is to cover the first surface 311 that crystal type is engaged to this substrate 31.This chip perforating holes 324 is to connect this back side 321 and this line layer.
This adhesive material 33 coats all this chips 32.In the present embodiment, this adhesive material 33 more comprises at least one sealing perforating holes 331, and this sealing perforating holes 331 is to connect this chip perforating holes 324.This antenna 34 is to be positioned on this adhesive material 33, and is electrically connected to this chip 32.This antenna 34 for example is a discontinuous pattern metal level.In the present embodiment, this antenna 34 is plating (Coating) or attaches on this adhesive material 33, makes that this antenna 34 is these sealing perforating holes 331 of contact, and can electrically connect with this substrate 31 by this sealing perforating holes 331 and this chip perforating holes 324.Be noted that this antenna 34 can extend to the side of this adhesive material 33, however this antenna 34 not physics contact this substrate 31.Described soldered ball 35 is the second surfaces 312 that are positioned at this substrate 31.
Only the foregoing description only is explanation principle of the present invention and effect thereof, but not in order to restriction the present invention.Therefore, practise the foregoing description being made amendment and changing and still do not take off spirit of the present invention in the personage of this technology.Interest field of the present invention claim as described later is listed.
Claims (10)
1. semiconductor package with antenna comprises:
Substrate has first surface and second surface;
Chip is positioned at the first surface of this substrate, and is electrically connected to this substrate;
Adhesive material coats all or part of this chip; And
Antenna is positioned on this adhesive material, and is electrically connected to this chip.
2. semiconductor package as claimed in claim 1, wherein this chip has active surface, the back side, line layer and at least one chip perforating holes, this line layer is to be positioned at this active surface, this active surface is covering the first surface that crystal type is engaged to this substrate, and this chip perforating holes is to connect this back side and this line layer.
3. semiconductor package as claimed in claim 2, wherein this adhesive material has opening, and to manifest the back side of this chip, this antenna is the back side and this chip perforating holes of this chip of contact.
4. semiconductor package as claimed in claim 2, wherein this adhesive material coats all this chips, and this adhesive material more comprises at least one sealing perforating holes, and this sealing perforating holes is to connect this chip perforating holes, and this antenna is this sealing perforating holes of contact.
5. semiconductor package as claimed in claim 1, more comprise several wires, this chip has active surface, the back side, several chip pad and rerouting layer, described chip pad and this rerouting layer are to be positioned at this active surface, this back side is the first surface that attaches to this substrate, described lead electrically connects the first surface of described chip pad to this substrate, this adhesive material has an opening, to manifest the part active surface of this chip, this antenna is the active surface of this chip of contact, and utilizes this rerouting layer to be electrically connected to described chip pad.
6. semiconductor package as claimed in claim 1, wherein this antenna is plating or attaches on this adhesive material.
7. semiconductor package as claimed in claim 1, wherein this antenna is the side that extends to this adhesive material.
8. semiconductor package as claimed in claim 1, wherein antenna not physics contact this substrate.
9. semiconductor package as claimed in claim 1 more comprises several soldered balls, is positioned at the second surface of this substrate.
10. semiconductor package as claimed in claim 1, wherein this antenna is the discontinuous pattern metal level.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 200810099853 CN101286505B (en) | 2008-05-26 | 2008-05-26 | Semi-conductor encapsulation structure having an antenna |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 200810099853 CN101286505B (en) | 2008-05-26 | 2008-05-26 | Semi-conductor encapsulation structure having an antenna |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN101286505A true CN101286505A (en) | 2008-10-15 |
| CN101286505B CN101286505B (en) | 2012-06-13 |
Family
ID=40058584
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN 200810099853 Active CN101286505B (en) | 2008-05-26 | 2008-05-26 | Semi-conductor encapsulation structure having an antenna |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN101286505B (en) |
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101980359A (en) * | 2010-09-07 | 2011-02-23 | 日月光半导体制造股份有限公司 | Semiconductor package and manufacturing method thereof |
| CN105097747A (en) * | 2015-09-01 | 2015-11-25 | 上海伊诺尔信息技术有限公司 | Packaging structure and packaging method of intelligent card chip |
| CN109244642A (en) * | 2018-08-07 | 2019-01-18 | 清华大学 | Encapsulating antenna and its manufacturing method |
| CN111786702A (en) * | 2020-07-10 | 2020-10-16 | 歌尔科技有限公司 | NFC module and wearable equipment |
| CN112447690A (en) * | 2019-08-29 | 2021-03-05 | 力成科技股份有限公司 | Semiconductor packaging structure with antenna on top |
Family Cites Families (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP1126522A1 (en) * | 2000-02-18 | 2001-08-22 | Alcatel | Packaged integrated circuit with radio frequency antenna |
| JP4376715B2 (en) * | 2004-07-16 | 2009-12-02 | 三洋電機株式会社 | Manufacturing method of semiconductor device |
| US20060285480A1 (en) * | 2005-06-21 | 2006-12-21 | Janofsky Eric B | Wireless local area network communications module and integrated chip package |
-
2008
- 2008-05-26 CN CN 200810099853 patent/CN101286505B/en active Active
Cited By (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101980359A (en) * | 2010-09-07 | 2011-02-23 | 日月光半导体制造股份有限公司 | Semiconductor package and manufacturing method thereof |
| CN105097747A (en) * | 2015-09-01 | 2015-11-25 | 上海伊诺尔信息技术有限公司 | Packaging structure and packaging method of intelligent card chip |
| CN105097747B (en) * | 2015-09-01 | 2018-07-06 | 上海伊诺尔信息技术有限公司 | Intelligent card chip encapsulating structure and packaging method |
| CN109244642A (en) * | 2018-08-07 | 2019-01-18 | 清华大学 | Encapsulating antenna and its manufacturing method |
| CN109244642B (en) * | 2018-08-07 | 2020-11-13 | 清华大学 | Method for manufacturing packaged antenna |
| CN112447690A (en) * | 2019-08-29 | 2021-03-05 | 力成科技股份有限公司 | Semiconductor packaging structure with antenna on top |
| CN112447690B (en) * | 2019-08-29 | 2024-05-14 | 力成科技股份有限公司 | Semiconductor packaging structure with antenna arranged on top |
| CN111786702A (en) * | 2020-07-10 | 2020-10-16 | 歌尔科技有限公司 | NFC module and wearable equipment |
Also Published As
| Publication number | Publication date |
|---|---|
| CN101286505B (en) | 2012-06-13 |
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| SE01 | Entry into force of request for substantive examination | ||
| C14 | Grant of patent or utility model | ||
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