CN101286367A - FPGA built-in dual port memory test method - Google Patents
FPGA built-in dual port memory test method Download PDFInfo
- Publication number
- CN101286367A CN101286367A CNA2008101124190A CN200810112419A CN101286367A CN 101286367 A CN101286367 A CN 101286367A CN A2008101124190 A CNA2008101124190 A CN A2008101124190A CN 200810112419 A CN200810112419 A CN 200810112419A CN 101286367 A CN101286367 A CN 101286367A
- Authority
- CN
- China
- Prior art keywords
- port
- storer
- address
- begin
- bank bit
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Images
Landscapes
- Techniques For Improving Reliability Of Storages (AREA)
Abstract
The invention discloses a testing method of a storage with embedded double ports of an FPGA, which configures all the storages with the embedded double ports of the FPGA into the same one of the optional working modes, and leads the inputs of the same ports to be parallelly connected together so as to be used as a common input end; when in testing, the March C algorithm is adopted to alternately test two ports, and a combinatorial vector is simultaneously applied to the two ports so as to carry out the relevance failure testing of the two ports, thus judging the correctness of storage output. The testing method effectively finishes the testing of the storage with the embedded double ports of the FPGA, achieves the testing coverage of 100 percent, reasonably utilizes free resources in the FPGA as examination logics, simplifies debugging process, decreases input and output ports and greatly improves testing efficiency.
Description
Technical field
The present invention relates to a kind of method of testing of storer, particularly a kind of method of testing of FPGA built-in dual port memory.
Background technology
The FPGA built-in dual port memory is a kind of special dual-ported memory, and its feature is that storer can be configured to multiple mode of operation, and storer has different data widths and storage depth under the different mode of operations.Key to the test of FPGA built-in dual port memory is that the test coverage of guaranteeing the various types of faults under each mode of operation reaches 100%.
In recent years, the area occupied in chip of the built-in dual port memory among the FPGA is increasing, and frequency of utilization in actual applications is also more and more higher, therefore the full test of built-in dual port memory is become the link of particular importance in the FPGA measuring technology.Abroad the test of dual-ported memory is studied, a lot of method of testings have been proposed, these methods serve as that the basis produces test vector with March C algorithm mostly, this vector is applied in the fixing dual-ported memory of scale, and the output result of dual-ported memory is tested.These methods generally all will move twice with test procedure, only test a port at every turn, but the real work pattern of such method of testing and dual-ported memory has difference, can reduce the test coverage of certain coupling fault.Domestic research in this field also is in the starting stage, does not still have a kind of method of testing of maturation.
Summary of the invention
Technology of the present invention is dealt with problems and is: overcome the deficiencies in the prior art, a kind of method of testing with FPGA built-in dual port memory of high test coverage is provided.
Technical solution of the present invention is: a kind of method of testing of FPGA built-in dual port memory is characterized in that step is as follows:
(1) two storage ports to each embedded dual-ported memory of FPGA are numbered, and are respectively port A and port B;
(2) the Input Address end A of each built-in dual port memory port A, input data terminal A, port Enable Pin A, read-write Enable Pin A, reseting controling end A, input end of clock A are connected in parallel respectively as public input end A, the output terminal step-by-step of each built-in dual port memory port A is connected in parallel respectively as parallel output terminal A; The Input Address end B of each built-in dual port memory port B, input data terminal B, port Enable Pin B, read-write Enable Pin B, reseting controling end B, input end of clock B are connected in parallel respectively as public input end B, the output terminal step-by-step of each built-in dual port memory port B is connected in parallel respectively as parallel output terminal B;
(3) each built-in dual port memory is configured to identical mode of operation;
(4) the port A with each built-in dual port memory is made as effectively, and it is invalid that port B is made as, and by public input end A each storer of parallel connection is applied March C test of heuristics vector and carries out fault test;
(5) the port B with each built-in dual port memory is made as effectively, and it is invalid that port A is made as, and by public input end B each storer of parallel connection is applied March C test of heuristics vector and carries out fault test;
(6) port A and the port B with each built-in dual port memory is made as effectively simultaneously, by public input end A and public input end B each storer of parallel connection applied the relevance fault test that mix vector carries out two-port simultaneously;
(7) each built-in dual port memory is set to other identical mode of operation, and repeating step (4)～(6) are tested.
By public input end A each storer of parallel connection being applied the method that March C test of heuristics vector carries out fault test in the described step (4) is:
(1) each built-in dual port memory activates port A by port Enable Pin A, by port Enable Pin B close port B;
(2) write 0 in any order each bank bit of each address location of storer; Begin to read the storing value of each bank bit of each address location by ascending order from the start address of storer then, the readout step-by-step of each storer is carried out or operation and xor operation, judges that corresponding position is whether all identical and all is 0;
(3) begin to write 1 by the start address of ascending order to each bank bit of each address location from storer, begin to read the storing value of each bank bit of each address location then from the start address of storer by ascending order, the readout step-by-step of each storer is carried out and operation and xor operation, judges that corresponding position is whether all identical and all is 1;
(4) begin to write 0 by the start address of ascending order to each bank bit of each address location from storer, begin to read the storing value of each bank bit of each address location then from the last address of storer by descending, the readout step-by-step of each storer is carried out or operation and xor operation, judges that corresponding position is whether all identical and all is 0;
(5) begin to write 1 by the last address of descending to each bank bit of each address location from storer, begin to read the storing value of each bank bit of each address location then from the last address of storer by descending, the readout step-by-step of each storer is carried out and operation and xor operation, judges that corresponding position is whether all identical and all is 1;
(6) begin to write 0 by the last address of descending to each bank bit of each address location from storer, begin to read the storing value of each bank bit of each address location then in any order from the last address of storer, the readout step-by-step of each storer is carried out or operation and xor operation, judges that corresponding position is whether all identical and all is 0.
By public input end B each storer of parallel connection being applied the method that March C test of heuristics vector carries out fault test in the described step (5) is:
(1) each built-in dual port memory activates port B by port Enable Pin B, by port Enable Pin A close port A;
(2) begin to write 0 from the start address of storer in any order to each bank bit of each address location, begin to read the storing value of each bank bit of each address location then from the start address of storer by ascending order, the readout step-by-step of each storer is carried out or operation and xor operation, judges that corresponding position is whether all identical and all is 0;
(3) begin to write 1 by the start address of ascending order to each bank bit of each address location from storer, begin to read the storing value of each bank bit of each address location then from the start address of storer by ascending order, the readout step-by-step of each storer is carried out and operation and xor operation, judges that corresponding position is whether all identical and all is 1;
(4) begin to write 0 by the start address of ascending order to each bank bit of each address location from storer, begin to read the storing value of each bank bit of each address location then from the last address of storer by descending, the readout step-by-step of each storer is carried out or operation and xor operation, judges that corresponding position is whether all identical and all is 0;
(5) begin to write 1 by the last address of descending to each bank bit of each address location from storer, begin to read the storing value of each bank bit of each address location then from the last address of storer by descending, the readout step-by-step of each storer is carried out and operation and xor operation, judges that corresponding position is whether all identical and all is 1;
(6) begin to write 0 by the last address of any preface to each bank bit of each address location from storer, begin to read the storing value of each bank bit of each address location then from the last address of storer by descending, the readout step-by-step of each storer is carried out or operation and xor operation, judges that corresponding position is whether all identical and all is 0.
By public input end A and public input end B each storer of parallel connection being applied the method that mix vector carries out the relevance fault test simultaneously in the described step (6) is:
(1) each built-in dual port memory activates port A by port Enable Pin A, activates port B by port Enable Pin B;
(2) begin to write 0 by the start address of ascending order by port A from storer to each bank bit of each address location, begin to read the storing value of each bank bit of each address location then from the start address of storer by ascending order by port A, begin to read the storing value of each bank bit of each address location from the 2nd bit address of storer by ascending order by port B, the readout of each storer divides the port step-by-step to carry out or operation and xor operation, judges that corresponding position is whether all identical and all is 0;
(3) begin to write 1 by the start address of ascending order by port A from storer to each bank bit of each address location, begin to read the storing value of each bank bit of each address location then from the start address of storer by ascending order by port A, begin to read the storing value of each bank bit of each address location from the 2nd bit address of storer by ascending order by port B, the readout of each storer divides the port step-by-step to carry out and operation and xor operation, judges that corresponding position is whether all identical and all is 1;
(4) begin to finish to write 0 from the start address of storer by ascending order by port A to each bank bit of each address location to half position of storage depth, begin from half position of the memory stores degree of depth to write 0 for each bank bit of each address location by ascending order by port B to last end of address (EOA), begin from half position of the memory stores degree of depth to read the storing value of each bank bit of each address location by ascending order by port A then to last end of address (EOA), begin to finish to read the storing value of each bank bit of each address location to half position of storage depth from the start address of storer by ascending order by port B, the readout of each storer divides the port step-by-step to carry out or operation and xor operation, judges that corresponding position is whether all identical and all is 0;
(5) begin from half position of the memory stores degree of depth to write 1 for each bank bit of each address location by ascending order by port A to last end of address (EOA), begin to finish to write 1 from the start address of storer by ascending order by port B to each bank bit of each address location to half position of storage depth, after beginning to finish to read the storing value of each bank bit of each address location to half position of storage depth, the start address of storer writes 0 for again each bank bit of this address location by ascending order by port A then, begin after the storing value of each bank bit of each address location is read in last end of address (EOA), to write 0 for again each bank bit of this address location from half position of the memory stores degree of depth by ascending order by port B, the readout of each storer divides the port step-by-step to carry out and operation and xor operation, judges that corresponding position is whether all identical and all is 1;
(6) begin from the last address of storer to finish to write 1 by descending by port A to each bank bit of each address location to half position of storage depth, begin to finish to write 1 from half position of the memory stores degree of depth by descending by port B to each bank bit of each address location to start address, begin from half position of the memory stores degree of depth to finish to read the storing value of each bank bit of each address location by descending by port A then to start address, begin to finish to read the storing value of each bank bit of each address location to half position of storage depth from the last address of storer by descending by port B, the readout of each storer divides the port step-by-step to carry out and operation and xor operation, judges that corresponding position is whether all identical and all is 1;
(7) begin from the last address of storer to finish to write 0 by descending by port A to each bank bit of each address location to half position of storage depth, begin to finish to write 0 from half position of the memory stores degree of depth by descending by port B to each bank bit of each address location to start address, begin to finish to read the storing value of each bank bit of each address location then to half position of storage depth from the last address of storer by descending by port A, begin from half position of the memory stores degree of depth to finish to read the storing value of each bank bit of each address location by descending by port B to start address, the readout of each storer divides the port step-by-step to carry out or operation and xor operation, judges that corresponding position is whether all identical and all is 0.
The Input Address width of described port A or port B, input data width, output data width, data depth are determined by the mode of operation of storer.
The present invention's advantage compared with prior art is:
(1) carries out on the basis of fault test single port being carried out March C test of heuristics vector, increased by one group of mix vector, carry out the relevance fault test of two-port, improved the coverage rate of test;
(2) can utilize among the FPGA idle configurable logic resource as inspection logic, the output result of memory array be made check, save the input/output port of FPGA greatly, help the integrated of test macro, thereby can reduce testing cost by inside.
Description of drawings
Fig. 1 is the port synoptic diagram of the embedded single dual-ported memory of FPGA;
The cascade structure synoptic diagram of Fig. 2 for adopting the inventive method that the FPGA built-in dual port memory is tested;
Fig. 3 is the schematic diagram of inspection logic of the present invention.
Embodiment
As shown in Figure 1, be the port synoptic diagram of the embedded single dual-ported memory of FPGA.In the embodiment of the invention two ports are designated as port A201 and port B202 respectively, the first half of Fig. 1 is port A201, and the latter half is port B202.The input end of port A201 comprises address input end address_A203, data input pin datain_A204, port enable signal RAM_EN_A205, read-write control signal WEN_A206, reset signal RST_A207, clock signal clk _ A208, and the output terminal of port A201 is DOUT_A215; The input end of port B202 comprises address input end address_B209, data input pin datain_B210, port enable signal RAM_EN_B211, read-write control signal WEN_B212, reset signal RST_B213, clock signal clk _ B214, and the output terminal of port B202 is DOUT_B216.
Among the present invention, the built-in dual port memory among the FPGA all should be configured to same a kind of in the optional mode of operation.As shown in Figure 2, connect together as public input end 301 all kinds of inputs of dual port memory array middle port A201 are parallel respectively, all kinds of inputs of port B202 are parallel respectively to connect together as public input end 302; The output 305 of each port A201 is all parallel in the memory array is connected on the inspection logic 303, and the output 306 of each port B202 is all parallel to be connected on the inspection logic 304.Among Fig. 3 401,402, the 403rd, the synoptic diagram of inspection logic 303 or 304 specific implementations, form by look-up tables configuration idle among the FPGA by 401,402,403 inspection logics of forming 303 or 304, in the array output signal of the port A201 of each storer or port B202 all insert respectively in inspection logic 303 or 304 with door 401 or door 402, XOR gate 403 in; During test, when reading 1 operation, storer output is 1 entirely, be input to the door 401 carry out with the operation after, 401 output results should be 1 with door, otherwise show that stuck at 0 fault appears in certain storage unit, when reading 0 operation, storer output is 0 entirely, be input to or after door 402 carries out or operate, or door 402 is exported results and be should be 0, otherwise show that stuck at 1 fault appears in certain storage unit, because the value that each storage unit writes is all the same, so the result of XOR gate 403 should remain 0, otherwise shows that certain storage unit breaks down.
Embodiment
To the test of built-in dual port memory array with 5 kinds of reading and writing patterns, concrete steps are as follows:
Configuration for the first time and test
(1) each built-in dual port memory is configured to 256 * 16 mode of operation, data depth is 256, and data width is 16bit.
(2) each input end with same generic port in the storer is connected in parallel respectively as public input end; Inspection logic is by with door 401 or door 402, XOR gate 403 forms, the output data of same generic port is parallel simultaneously be input to door 401 or 402, XOR gate 403 on.
(3) activate port A201 by port Enable Pin A205, by port Enable Pin B211 close port B202; When adding test vector, the first step writes 16 0 for each address location by ascending order from first address (also can be by any preface, i.e. ascending order or descending, start address is optional), writes 0 operation through finishing after 256 clock period; Second step began each clock period by ascending order from start address and reads storing value (16 0) and the input or the door 402 and XOR gate 403 of an address location, under correct situation or door 402 should export 0 always, XOR gate 403 should export 0 always, otherwise illustrate that certain storage unit fails to realize writing 0 operation, finish through 256 clock period and read 0 and the product test operation; The 3rd step began each clock period by ascending order from start address and writes 16 1 for the appropriate address unit, through 256 clock period finish write 1 the operation, begin storing value (16 1) and the input and door 401 and XOR gate 403 that each clock period reads an address location by ascending order from start address then, under correct situation, should export 1 with door 401 always, XOR gate 403 should export 0 always, otherwise illustrate that certain storage unit fails to realize writing 1 operation, finish through 256 clock period and read 1 and product test; The 4th step began each clock period by ascending order from start address and writes 16 0 for the appropriate address unit, through 256 clock period finish write 0 the operation, begin each clock period by descending from termination address then and read storing value (16 0) and the input or the door 402 and XOR gate 403 of an address location, under correct situation or door 402 should export 0 always, XOR gate 403 should export 0 always, otherwise illustrate that certain storage unit fails to realize writing 0 operation, finish through 256 clock period and read 0 and the product test operation; The 5th step began each clock period by descending from termination address and writes 16 1 for the appropriate address unit, through 256 clock period finish write 1 the operation, begin storing value (16 1) and the input and door 401 and XOR gate 403 that each clock period reads an address location by descending from termination address then, under correct situation, should export 1 with door 401 always, XOR gate 403 should export 0 always, otherwise illustrate that certain storage unit fails to realize writing 1 operation, finish through 256 clock period and read 1 and product test; The 6th step began each clock period by descending from termination address and writes 16 0 for the appropriate address unit, through 256 clock period finish write 0 the operation, begin each clock period by descending from termination address then and read storing value (16 0) and the input or the door 402 and XOR gate 403 of an address location, under correct situation or door 402 should export 0 always, XOR gate 403 should export 0 always, otherwise illustrate that certain storage unit fails to realize writing 0 operation, finish through 256 clock period and read 0 and the product test operation;
(4) activate port B202 by port Enable Pin B211, by port Enable Pin A205 close port A201; When adding test vector, the first step is pressed descending (also can be by any preface, i.e. ascending order or descending, start address is optional) and is write 16 0 for each address location, writes 0 operation through finishing after 256 clock period; Second step began each clock period by ascending order from start address and reads storing value (16 0) and the input or the door 402 and XOR gate 403 of an address location, under correct situation or door 402 should export 0 always, XOR gate 403 should export 0 always, otherwise illustrate that certain storage unit fails to realize writing 0 operation, finish through 256 clock period and read 0 and the product test operation; The 3rd step began each clock period by ascending order from start address and writes 16 1 for the appropriate address unit, through 256 clock period finish write 1 the operation, begin storing value (16 1) and the input and door 401 and XOR gate 403 that each clock period reads an address location by ascending order from start address then, under correct situation, should export 1 with door 401 always, XOR gate 403 should export 0 always, otherwise illustrate that certain storage unit fails to realize writing 1 operation, finish through 256 clock period and read 1 and product test; The 4th step began each clock period by ascending order from start address and writes 16 0 for the appropriate address unit, through 256 clock period finish write 0 the operation, begin each clock period by descending from termination address then and read storing value (16 0) and the input or the door 402 and XOR gate 403 of an address location, under correct situation or door 402 should export 0 always, XOR gate 403 should export 0 always, otherwise illustrate that certain storage unit fails to realize writing 0 operation, finish through 256 clock period and read 0 and the product test operation; The 5th step began each clock period by descending from termination address and writes 16 1 for the appropriate address unit, through 256 clock period finish write 1 the operation, begin storing value (16 1) and the input and door 401 and XOR gate 403 that each clock period reads an address location by descending from termination address then, under correct situation, should export 1 with door 401 always, XOR gate 403 should export 0 always, otherwise illustrate that certain storage unit fails to realize writing 1 operation, finish through 256 clock period and read 1 and product test; The 6th step began each clock period by descending from termination address and writes 16 0 for the appropriate address unit, through 256 clock period finish write 0 the operation, begin each clock period by descending from termination address then and read storing value (16 0) and the input or the door 402 and XOR gate 403 of an address location, under correct situation or door 402 should export 0 always, XOR gate 403 should export 0 always, otherwise illustrate that certain storage unit fails to realize writing 0 operation, finish through 256 clock period and read 0 and the product test operation;
(5) activate port A201 and port B202 simultaneously by port Enable Pin A205, B211; When adding test vector, the first step begins each clock period by ascending order from start address by port A201 and writes 16 0 for an address location, through 256 clock period finish write 0 the operation, begin each clock period by ascending order from start address by port A201 then and read the storing value (16 0) of an address location, read the storing value (1 6 0) of an address location and return start address since each clock period of the 2nd bit address by ascending order by port B202 the 256th clock period, the readout of port A201 and port B202 is all imported or door 402 and XOR gate 403, under correct situation or door 402 should export 0 always, XOR gate 403 should export 0 always, otherwise illustrate that certain storage unit fails to realize writing 0 operation, finish through 256 clock period and read 0 and the product test operation; Second step, beginning each clock period by ascending order from start address by port A201 writes 16 1 for an address location, through 256 clock period finish write 1 the operation, begin each clock period by ascending order from start address by port A201 then and read the storing value (16 1) of an address location, read the storing value (16 1) of each address location and return start address since each clock period of the 2nd bit address by ascending order by port B202 the 256th clock period, the readout of port A201 and port B202 is all imported and door 401 and XOR gate 403, under correct situation, should export 1 with door 401 always, XOR gate 403 should export 0 always, otherwise illustrate that certain storage unit fails to realize writing 1 operation, finish through 256 clock period and read 1 and product test; The 3rd step began to 128th bit address to finish each clock period by ascending order from start address by port A201 and writes 16 0 for an address location, finishing each clock period by port B202 from the 129th bit address to a last bit address by ascending order writes 16 0 for an address location, through 128 clock period finish write 0 the operation, finish each clock period by port A201 from the 129th bit address to a last bit address by ascending order then and read the storing value (16 0) of an address location, begin to 128th bit address to finish each clock period by ascending order from start address by port B202 and read the storing value (16 0) of an address location, the readout of port A201 and port B202 is all imported or door 402 and XOR gate 403, under correct situation or door 402 should export 0 always, XOR gate 403 should export 0 always, otherwise illustrate that certain storage unit fails to realize writing 0 operation, finish through 128 clock period and read 0 and the product test operation; The 4th step finished each clock period by port A201 by ascending order and writes 16 1 for an address location from the 129th bit address to a last bit address, beginning to 128th bit address to finish each clock period by ascending order from start address by port B202 writes 1 for each bank bit of an address location, through 128 clock period finish write 1 the operation, begin to 128th bit address to finish storing value (16 1) that each clock period earlier read an address location by ascending order from start address by port A201 then and then this address location is write 16 0, finish the storing value (16 1) that each clock period reads an address location earlier by port B202 from the 129th bit address to a last bit address by ascending order and then this address location is write 16 0, the readout of port A201 and port B202 is all imported and door 401 and XOR gate 403, under correct situation, should export 1 with door 401 always, XOR gate 403 should export 0 always, otherwise illustrate that certain storage unit fails to realize writing 1 operation, finish through 128 clock period and read 1 and product test; The 5th step began to 129th bit address to finish each clock period by descending from last bit address by port A201 and writes 16 1 for an address location, finishing each clock period by port B202 from the 128th bit address to start address by descending writes 16 1 for an address location, through 128 clock period finish write 1 the operation, finish each clock period by port A201 from the 128th bit address to start address by descending then and read the storing value (16 1) of an address location, begin to 129th bit address to finish each clock period by descending from last bit address by port B202 and read the storing value (16 1) of an address location, the readout of port A201 and port B202 is all imported and door 401 and XOR gate 403, under correct situation, should export 1 with door 401 always, XOR gate 403 should export 0 always, otherwise illustrate that certain storage unit fails to realize writing 1 operation, finish through 128 clock period and read 1 and product test; The 6th step began to finish each clock period to the 129th bit address by port A201 by descending and writes 16 0 for an address location from last address, finishing each clock period by port B202 from the 128th bit address to start address by descending writes 16 0 for an address location, begin to finish each clock period by port A201 from last address by descending then and read the storing value (16 0) of an address location to the 129th bit address, finish each clock period by port B202 from the 128th bit address to start address by descending and read the storing value (16 0) of an address location, the readout of port A201 and port B202 is all imported or door 402 and XOR gate 403, under correct situation or door 402 should export 0 always, XOR gate 403 should export 0 always, otherwise illustrate that certain storage unit fails to realize writing 0 operation, finish through 128 clock period and read 0 and the product test operation.
Configuration for the second time and test
Each built-in dual port memory is configured to 512 * 8 mode of operation, and data depth is 512, and data width is 8.Similar method is tested according to configuration for the first time and test the time then.
Dispose for the third time and test
Each built-in dual port memory is configured to 1024 * 4 mode of operation, and data depth is 1024, and data width is 4.Similar method is tested according to configuration for the first time and test the time then.
The 4th configuration comprises the following steps:
Each built-in dual port memory is configured to 2048 * 2 mode of operation, and data depth is 2048, and data width is 2.Similar method is tested according to configuration for the first time and test the time then.
The 5th configuration and test
Each built-in dual port memory is configured to 4096 * 1 mode of operation, and data depth is 4096, and data width is 1.Similar method is tested according to configuration for the first time and test the time then.
By above-mentioned five configurations and test process, can finish the fault test of FPGA built-in dual port memory under different working modes.
The content that is not described in detail in the instructions of the present invention belongs to those skilled in the art's known technology.
Claims (5)
1, a kind of method of testing of FPGA built-in dual port memory is characterized in that step is as follows:
(1) two storage ports to each embedded dual-ported memory of FPGA are numbered, and are respectively port A (201) and port B (202);
(2) the Input Address end A (203) of each built-in dual port memory port A (201), input data terminal A (204), port Enable Pin A (205), read-write Enable Pin A (206), reseting controling end A (207), input end of clock A (208) are connected in parallel respectively as public input end A (301), output terminal (215) step-by-step of each built-in dual port memory port A (201) is connected in parallel respectively as parallel output terminal A (305); The Input Address end B (209) of each built-in dual port memory port B (202), input data terminal B (210), port Enable Pin B (211), read-write Enable Pin B (212), reseting controling end B (213), input end of clock B (214) are connected in parallel respectively as public input end B (302), output terminal (216) step-by-step of each built-in dual port memory port B (202) is connected in parallel respectively as parallel output terminal B (306);
(3) each built-in dual port memory is configured to identical mode of operation;
(4) the port A (201) with each built-in dual port memory is made as effectively, and it is invalid that port B (202) is made as, and by public input end A (301) each storer of parallel connection is applied March C test of heuristics vector and carries out fault test;
(5) the port B (202) with each built-in dual port memory is made as effectively, and it is invalid that port A (201) is made as, and by public input end B (302) each storer of parallel connection is applied March C test of heuristics vector and carries out fault test;
(6) port A (201) and the port B (202) with each built-in dual port memory is made as effectively simultaneously, by public input end A (301) and public input end B (302) each storer of parallel connection applied the relevance fault test that mix vector carries out two-port simultaneously;
(7) each built-in dual port memory is set to other identical mode of operation, and repeating step (4)～(6) are tested.
2, the method for testing of a kind of FPGA built-in dual port memory according to claim 1 is characterized in that: by public input end A (301) each storer of parallel connection being applied the method that March C test of heuristics vector carries out fault test in the described step (4) is:
(1) each built-in dual port memory activates port A (201) by port Enable Pin A (205), by port Enable Pin B (211) close port B (202);
(2) write 0 in any order each bank bit of each address location of storer; Begin to read the storing value of each bank bit of each address location by ascending order from the start address of storer then, the readout step-by-step of each storer is carried out or operation and xor operation, judges that corresponding position is whether all identical and all is 0;
(3) begin to write 1 by the start address of ascending order to each bank bit of each address location from storer, begin to read the storing value of each bank bit of each address location then from the start address of storer by ascending order, the readout step-by-step of each storer is carried out and operation and xor operation, judges that corresponding position is whether all identical and all is 1;
(4) begin to write 0 by the start address of ascending order to each bank bit of each address location from storer, begin to read the storing value of each bank bit of each address location then from the last address of storer by descending, the readout step-by-step of each storer is carried out or operation and xor operation, judges that corresponding position is whether all identical and all is 0;
(5) begin to write 1 by the last address of descending to each bank bit of each address location from storer, begin to read the storing value of each bank bit of each address location then from the last address of storer by descending, the readout step-by-step of each storer is carried out and operation and xor operation, judges that corresponding position is whether all identical and all is 1;
(6) begin to write 0 by the last address of descending to each bank bit of each address location from storer, begin to read the storing value of each bank bit of each address location then in any order from the last address of storer, the readout step-by-step of each storer is carried out or operation and xor operation, judges that corresponding position is whether all identical and all is 0.
3, the method for testing of a kind of FPGA built-in dual port memory according to claim 1 is characterized in that: by public input end B (302) each storer of parallel connection being applied the method that March C test of heuristics vector carries out fault test in the described step (5) is:
(1) each built-in dual port memory activates port B (202) by port Enable Pin B (211), by port Enable Pin A (205) close port A (201);
(2) begin to write 0 from the start address of storer in any order to each bank bit of each address location, begin to read the storing value of each bank bit of each address location then from the start address of storer by ascending order, the readout step-by-step of each storer is carried out or operation and xor operation, judges that corresponding position is whether all identical and all is 0;
(3) begin to write 1 by the start address of ascending order to each bank bit of each address location from storer, begin to read the storing value of each bank bit of each address location then from the start address of storer by ascending order, the readout step-by-step of each storer is carried out and operation and xor operation, judges that corresponding position is whether all identical and all is 1;
(4) begin to write 0 by the start address of ascending order to each bank bit of each address location from storer, begin to read the storing value of each bank bit of each address location then from the last address of storer by descending, the readout step-by-step of each storer is carried out or operation and xor operation, judges that corresponding position is whether all identical and all is 0;
(5) begin to write 1 by the last address of descending to each bank bit of each address location from storer, begin to read the storing value of each bank bit of each address location then from the last address of storer by descending, the readout step-by-step of each storer is carried out and operation and xor operation, judges that corresponding position is whether all identical and all is 1;
(6) begin to write 0 by the last address of any preface to each bank bit of each address location from storer, begin to read the storing value of each bank bit of each address location then from the last address of storer by descending, the readout step-by-step of each storer is carried out or operation and xor operation, judges that corresponding position is whether all identical and all is 0.
4, the method for testing of a kind of FPGA built-in dual port memory according to claim 1 is characterized in that: by public input end A (301) and public input end B (302) each storer of parallel connection being applied the method that mix vector carries out the relevance fault test simultaneously in the described step (6) is:
(1) each built-in dual port memory activates port A (201) by port Enable Pin A (205), activates port B (202) by port Enable Pin B (211);
(2) begin to write 0 by the start address of ascending order by port A (201) from storer to each bank bit of each address location, begin to read the storing value of each bank bit of each address location then from the start address of storer by ascending order by port A (201), begin to read the storing value of each bank bit of each address location from the 2nd bit address of storer by ascending order by port B (202), the readout of each storer divides the port step-by-step to carry out or operation and xor operation, judges that corresponding position is whether all identical and all is 0;
(3) begin to write 1 by the start address of ascending order by port A (201) from storer to each bank bit of each address location, begin to read the storing value of each bank bit of each address location then from the start address of storer by ascending order by port A (201), begin to read the storing value of each bank bit of each address location from the 2nd bit address of storer by ascending order by port B (202), the readout of each storer divides the port step-by-step to carry out and operation and xor operation, judges that corresponding position is whether all identical and all is 1;
(4) begin to finish to write 0 from the start address of storer by ascending order by port A (201) to each bank bit of each address location to half position of storage depth, begin from half position of the memory stores degree of depth to write 0 for each bank bit of each address location by ascending order by port B (202) to last end of address (EOA), begin from half position of the memory stores degree of depth to read the storing value of each bank bit of each address location by ascending order by port A (201) then to last end of address (EOA), begin to finish to read the storing value of each bank bit of each address location to half position of storage depth from the start address of storer by ascending order by port B (202), the readout of each storer divides the port step-by-step to carry out or operation and xor operation, judges that corresponding position is whether all identical and all is 0;
(5) begin from half position of the memory stores degree of depth to write 1 for each bank bit of each address location by ascending order by port A (201) to last end of address (EOA), begin to finish to write 1 from the start address of storer by ascending order by port B (202) to each bank bit of each address location to half position of storage depth, after beginning to finish to read the storing value of each bank bit of each address location to half position of storage depth, the start address of storer writes 0 for again each bank bit of this address location by ascending order by port A (201) then, begin after the storing value of each bank bit of each address location is read in last end of address (EOA), to write 0 for again each bank bit of this address location from half position of the memory stores degree of depth by ascending order by port B (202), the readout of each storer divides the port step-by-step to carry out and operation and xor operation, judges that corresponding position is whether all identical and all is 1;
(6) begin from the last address of storer to finish to write 1 by descending by port A (201) to each bank bit of each address location to half position of storage depth, begin to finish to write 1 from half position of the memory stores degree of depth by descending by port B (202) to each bank bit of each address location to start address, begin from half position of the memory stores degree of depth to finish to read the storing value of each bank bit of each address location by descending by port A (201) then to start address, begin to finish to read the storing value of each bank bit of each address location to half position of storage depth from the last address of storer by descending by port B (202), the readout of each storer divides the port step-by-step to carry out and operation and xor operation, judges that corresponding position is whether all identical and all is 1;
(7) begin from the last address of storer to finish to write 0 by descending by port A (201) to each bank bit of each address location to half position of storage depth, begin to finish to write 0 from half position of the memory stores degree of depth by descending by port B (202) to each bank bit of each address location to start address, begin to finish to read the storing value of each bank bit of each address location then to half position of storage depth from the last address of storer by descending by port A (201), begin from half position of the memory stores degree of depth to finish to read the storing value of each bank bit of each address location by descending by port B (202) to start address, the readout of each storer divides the port step-by-step to carry out or operation and xor operation, judges that corresponding position is whether all identical and all is 0.
5, according to the method for testing of claim 2 or 3 described a kind of FPGA built-in dual port memories, it is characterized in that: the Input Address width of described port A (201) or port B (202), input data width, output data width, data depth are determined by the mode of operation of storer.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN200810112419A CN100576361C (en) | 2008-05-23 | 2008-05-23 | A kind of method of testing of FPGA built-in dual port memory |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN200810112419A CN100576361C (en) | 2008-05-23 | 2008-05-23 | A kind of method of testing of FPGA built-in dual port memory |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN101286367A true CN101286367A (en) | 2008-10-15 |
| CN100576361C CN100576361C (en) | 2009-12-30 |
Family
ID=40058503
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN200810112419A Active CN100576361C (en) | 2008-05-23 | 2008-05-23 | A kind of method of testing of FPGA built-in dual port memory |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN100576361C (en) |
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102520337A (en) * | 2011-11-14 | 2012-06-27 | 华为技术有限公司 | Method for accessing register, device and automatic testing machine |
| CN102054536B (en) * | 2009-11-09 | 2012-10-03 | 上海华虹Nec电子有限公司 | Device for testing DP (Dual Port) SRAM (Static Random Access Memory) by utilizing ALPG tester |
| CN105893200A (en) * | 2014-10-21 | 2016-08-24 | 北京京航计算通讯研究所 | Method based on model replacement for inspecting equivalence of blackbox in FPGA |
| CN107451017A (en) * | 2016-05-31 | 2017-12-08 | 中车株洲电力机车研究所有限公司 | A kind of method for testing reliability and system for double port memory |
| CN108108278A (en) * | 2017-12-26 | 2018-06-01 | 北京国睿中数科技股份有限公司 | Verify the method and system of bus port function coverage |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103532770A (en) * | 2012-07-06 | 2014-01-22 | 成都林海电子有限责任公司 | Information interactive test method for satellite mobile communication terminal based on Beidou |
-
2008
- 2008-05-23 CN CN200810112419A patent/CN100576361C/en active Active
Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102054536B (en) * | 2009-11-09 | 2012-10-03 | 上海华虹Nec电子有限公司 | Device for testing DP (Dual Port) SRAM (Static Random Access Memory) by utilizing ALPG tester |
| CN102520337A (en) * | 2011-11-14 | 2012-06-27 | 华为技术有限公司 | Method for accessing register, device and automatic testing machine |
| CN105893200A (en) * | 2014-10-21 | 2016-08-24 | 北京京航计算通讯研究所 | Method based on model replacement for inspecting equivalence of blackbox in FPGA |
| CN107451017A (en) * | 2016-05-31 | 2017-12-08 | 中车株洲电力机车研究所有限公司 | A kind of method for testing reliability and system for double port memory |
| CN108108278A (en) * | 2017-12-26 | 2018-06-01 | 北京国睿中数科技股份有限公司 | Verify the method and system of bus port function coverage |
| CN108108278B (en) * | 2017-12-26 | 2021-07-30 | 北京国睿中数科技股份有限公司 | Method and system for verifying function coverage rate of bus port |
Also Published As
| Publication number | Publication date |
|---|---|
| CN100576361C (en) | 2009-12-30 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN100576361C (en) | A kind of method of testing of FPGA built-in dual port memory | |
| CN101458971B (en) | Test system and method for built-in memory | |
| CN101996687A (en) | Built-in system test method of multiple static random access memory (SRAM) based on scanning test | |
| CN103576076B (en) | System and method for executing sweep test | |
| US6519194B2 (en) | Semiconductor memory device with a rapid packet data input, capable of operation check with low speed tester | |
| US6658611B1 (en) | Programmable built-in self-test system for semiconductor memory device | |
| CN103310852B (en) | Based on the mbist controller structural system of IEEE 1500 operating such SRAM/ROM | |
| CN111308329B (en) | Circuit, device and method for testability design of many-core computing chip | |
| US7203873B1 (en) | Asynchronous control of memory self test | |
| CN103617810A (en) | Test structure and test method for embedded memory | |
| CN102522123B (en) | Method for increasing read-write test efficiency of storage equipment by utilizing data generator module | |
| CN108062267A (en) | Configurable register file self-testing method and generating device | |
| US7805644B2 (en) | Multiple pBIST controllers | |
| CN102789815A (en) | PROM circuit framework for FPGA configuration | |
| CN101923897A (en) | SIC (semiconductor integrated circuit) and the method for testing that is used for SIC (semiconductor integrated circuit) | |
| CN105938727A (en) | Semiconductor system and method for testing semiconductor device | |
| CN103903651A (en) | Double-line serial port build-in self-test circuit, and communication method thereof | |
| CN107068196A (en) | Built-in self-test circuit, system and method for flash memory | |
| CN112698994A (en) | Partial bit stream read-back technology for FPGA internal resource test | |
| CN105047229A (en) | Circuit and method for self testing in memory cell of RRAM | |
| JPH04178580A (en) | Self diagnostic device for semiconductor memory | |
| JP3681892B2 (en) | Data input / output circuit and data input / output method of semiconductor device | |
| CN107290656B (en) | A kind of expansible JTAG debugging structure of integrated bi-directional CRC check function | |
| CN103065672A (en) | Asynchronous static random access memory based on internet protocol (IP) of synchronous static random access memory | |
| KR102038414B1 (en) | Test device and operating method thereof |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant |