CN101286364A - Phase-change memorizer 1R1T structure and its driver circuit design method - Google Patents
Phase-change memorizer 1R1T structure and its driver circuit design method Download PDFInfo
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- CN101286364A CN101286364A CNA2008100366192A CN200810036619A CN101286364A CN 101286364 A CN101286364 A CN 101286364A CN A2008100366192 A CNA2008100366192 A CN A2008100366192A CN 200810036619 A CN200810036619 A CN 200810036619A CN 101286364 A CN101286364 A CN 101286364A
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Abstract
The invention relates to a design method of a phase-change storage 1R1T structure and a drive circuit that is used by the phase-change storage 1R1T structure. The invention is characterized in that an IRIT structure that interconnects a phase-change resistance GST and an NMOS gate tube in a certain way is adopted, and based on the adopted IRIT structure, the design method of the drive circuit is disclosed and is characterized in that the source end of the gate tube is connected with one end of the drive circuit, the leakage end of the gate tube is connected with the phase-change resistance, the grid end of the gate tube is connected with the bit line of a phase-change array, the other end of the phase-change resistance is connected with the highest power level VDD of the circuit. A double-level current mirror circuit is adopted, wherein, the first level comprises three current mirrors that are formed by three pairs of PMOS tubes, the second level comprises three current mirrors that are formed by three pairs of NMOS tubes, and the double-level current mirror circuit is finally coupled with the bit line, thus generating a drive current that is used for reading, writing and erasing, and applied to the phase-change storage unit. Under the precondition that the complexity and the scale of circuit design are not increased, the design method of the drive circuit obtains the effects of lowering the requirements of the technical production line and production cost.
Description
Technical field
The invention belongs to the large scale integrated circuit technical field, be specifically related to a kind of new 1R1T structural design and the corresponding design of drive circuit that mainly constitutes thereof by the two-stage current-mirror structure.
Background technology
Chalcogenide compound random access memory (C-RAM, Chalcogenide-Random Access Memory) technology is based on that Ao Fuxinsiji electronic effect that S.R.Ovshinsky proposes in the 60 to 70's of 20th century sets up, and is named as Ao Fuxinsiji electrical effect storage and uniform device (OUM-Ovonics UnifiedMemory) again.The ultimate principle of phase transition storage is: be worked into the reversible transition material of nano-scale, the high resistant characteristic when low-resistance when utilizing the material crystalline state and amorphous state realizes the storage of different conditions.The used material of phase change cells is considerably less in the phase transition storage, and storage density is high and make simply, only needs to increase on existing standard CMOS process that 2-4 mask process just can create and ready-made lsi technology combination is very perfect.
In the cut-throat competition of the non-volatile memory technology of research and development high-performance of future generation, phase transition storage is read and write number of times in read or write speed, data hold time, and cellar area, many advantages of aspects such as power consumption have shown great competitive power, have obtained development faster.Phase transition storage not only can be widely used in civilian microelectronics such as mobile phone, digital camera, MP3 player, mobile memory card and other handheld device as FLASH and DRAM, and has important application prospects in military domain such as Aero-Space, guided missile systems.In addition, phase transition storage typical case from now on uses and will be deep into every field, comprising network router, hinge communicator, scanner, various terminal, printer and the such auto-navigation system of similar gps system, also has a large amount of potential applications in addition.IBM is responsible for nano science responsible official Si Peike. Na Layaen (Narayan) expression, the function that phase transition storage can provide a lot of flash memories to provide, phase transition storage is expected to replace hard disk, can make high-speed electronic calculator, perhaps can deposit computer software in phase transition storage.
What extensively adopt at present is GeSbTe (GST) compound or the phase-change material that obtains after mixing based on GeSbTe, and the phase transition storage core texture is the 1T1R structure, and Fig. 1 and Fig. 2 have provided its physical arrangement and circuit structure.Among Fig. 2, T is a gate tube, adopts NMOS (N NMOS N-channel MOS N) pipe generally speaking, and its source end ground connection.Traditional chip-stored array as shown in Figure 3, the 1T1R structure of said NMOS pipe source end ground connection above the storage array of its core has adopted.But like this processing line has been proposed higher requirement,, must be incorporated into phase-change material GST in the processing line during manufacturing, and this has just proposed higher requirement to processing line, spends huge because all need there be metal-oxide-semiconductor at GST material two ends; Perhaps GST is not integrated into the CMOS processing line, also promptly with standard CMOS (complementary metal oxide semiconductor (CMOS)) technology circuit part is made earlier, do the GST material with the GST processing line at last, because gate tube is a source end ground connection, so just need very long metal lead wire that the GST of top layer is connected with the gate tube of bottom, and the metal that last one deck plays the connection effect still needs bigger area, is unfavorable for the integrated of phase transition storage.
Summary of the invention
The object of the present invention is to provide the method for designing of a kind of phase transition storage 1R1T structure and employed driving circuit.Be characterised in that employing with a phase change resistor GST and a NMOS gate tube by the interconnective 1R1T structure of certain way.Wherein comprise the design of new gate tube position, this gate tube source termination drive source one end, and drain terminal connects GST resistance, the bit line in the grid termination phase change memory array, the maximum level VDD of the other end connection circuit of phase change resistor GST.And the main phase-change memorizer driver circuit that constitutes by a two-stage current mirror of the design of setting out thus.Like this, can reduce the requirement to processing line, under the prerequisite that does not increase circuit complexity, available standards CMOS processing line is finished basic circuit earlier, does GST core material and subsequent technique with the GST processing line then, finally finishes entire chip.This method goes for 0.18um, and 0.13um or littler technology will be more conducive to the integrated of phase transition storage.
The source termination drive current source that the present invention proposes and unearthed 1R1T structural design, and further design whole driving circuit according to this 1R1T structure, like this, on the basis that does not increase the entire chip circuit complexity, reduce the technological requirement of making this chip, increased the implementation of phase change memory chip.Though the 1R1T structure of invention design, because its source end is also unearthed, there is a voltage difference like this between source end and the substrate, will there be the inclined to one side effect of a lining in gate tube, open under the grid voltage at identical gate tube, the electric current that gate tube can flow through can decrease, so design the time need become the size of gate tube bigger a little, but this does not influence its application.At some middle-grade embedded electronic products, in using as the design of smart card etc., because itself capacity is less, do not need integrated on a large scale, therefore the requirement to the gate tube size can suitably reduce, so adopt 1R1T structure of the present invention and corresponding driving circuit structure, can satisfy the performance requirement of its product fully, but greatly reduce manufacturing cost.
Phase transition storage mainly comprises address decoding circuitry, Drive and Control Circuit, and the reading and writing driving circuit is read the storage array of amplifying circuit and core, and its basic structure synoptic diagram is as shown in Figure 4.The storage array of core adopts 1T1R structure shown in Figure 5, this structrual description storage unit the be connected situation concrete with driving circuit.
Phase-changing memory cell array of the present invention comprises several word lines, several bit lines and several phase change cells that are in the word line and the bit line zone of intersection, each phase-change memory cell comprises a word line by each, a gate tube and a phase change resistor definition, and each phase change resistor all can be programmed between amorphous state and crystalline state; Address decoder decoding line of input address is to select the word line of each storage unit; The column address of circuit according to input selected in the position, selects a bit lines.Write the driving circuit generation and make storage unit be programmed for amorphous reset pulse electric current, and make storage unit be programmed for the set pulse current of crystalline state.Read the driving circuit generation and read the read current of the state of memory cells after being programmed.Drive and Control Circuit produces the reset pulse of certain pulse width, set pulse or read pulse.
The driving circuit of the present invention's design is mainly a two-stage current mirroring circuit, wherein the first order comprises three current mirrors that formed by three pairs of PMOS pipes, the second level comprises three current mirrors that formed by three pairs of NMOS pipes, and finally be coupled to bit line and impose on phase-change memory cell, produce the drive current that is used for reading and writing, wiping; In first order current mirroring circuit and second level current mirroring circuit, add gauge tap, the opening and close by Drive and Control Circuit and partly control of this gauge tap.The prime pulse signal generator produces the drive control signal of certain pulsewidth, and the opening and closing of switch in the Control current mirror makes that thus the electric current that is added on the phase change cells is the signal that certain pulsewidth is arranged.Realize reading and writing, wiping operation smoothly to storage unit.
This shows that a kind of phase transition storage 1R1T structure provided by the invention is characterized in that adopting with a phase change resistor GST and a NMOS gate tube by the interconnective 1R1T structure of certain mode, and based on this design driven circuit.
A kind of phase transition storage provided by the invention is characterized in that comprising:
Phase-change memory cell, each includes a phase-change material GST that can programme between amorphous state and crystalline state; The NMOS gate tube that connects each storage unit, it is connected by certain mode with phase-change memory cell, and several such linkage units constitute the storage array of phase transition storage core.
Address decoding circuitry is used to select at least one storage unit.
Control circuit is used to control the phase-change memory cell of choosing is carried out reading and writing, wipes operation, produces certain pulse width.
The reading and writing driving circuit is used to generate the phase-change memory cell of choosing is applied the read current that carries out read operation, and the phase-change memory cell of choosing is programmed for amorphous wiping electric current and is programmed for the write current of crystalline state.
Read amplifying circuit, be used for the state of storage unit is read amplification.
The method for designing that is used for the driving circuit of phase transition storage 1R1T structure provided by the invention is by the two-stage current mirroring circuit, wherein the first order comprises three current mirrors that formed by three pairs of PMOS pipes, the second level comprises three current mirrors that formed by three pairs of NMOS pipes, and finally be coupled to bit line and impose on phase-change memory cell, produce the drive current that is used for reading and writing, wiping.
In first order current mirroring circuit and second level current mirroring circuit, add gauge tap, the opening and close by Drive and Control Circuit and partly control of this gauge tap.
Produce the drive control signal of certain pulsewidth by pulse signal generator, the opening and closing of switch in the level current mirror of control back makes that thus the electric current that is added on the phase change cells is the signal that certain pulsewidth is arranged.
In sum, adopted 1R1T structure provided by the invention, avoided phase-change material GST is integrated into the CMOS processing line and processing line is polluted destruction, thereby the technological requirement to the phase change memory chip manufacturing decreases, applicable to the phase change memory chip manufacturing that phase-change material can not be incorporated in the processing line.The present invention does not increase the scale and the complicacy of circuit design, but has obtained to reduce the effect of production line requirement and saving manufacturing cost.
Description of drawings
Fig. 1 is the physical arrangement synoptic diagram of phase-change memory storage unit.
Fig. 2 is the electrical block diagram of phase transition storage 1R1T commonly used.
Fig. 3 is traditional chip-stored array synoptic diagram commonly used.
Fig. 4 is that phase transition storage GST subsequent technique provided by the invention is made GST resistance synoptic diagram.
Fig. 5 is the connection diagram of 1R1T provided by the invention and driving circuit.
Fig. 6 is a phase change memory chip internal circuit synoptic diagram provided by the invention.
Fig. 7 writes the sequential synoptic diagram for phase transition storage provided by the invention.
Fig. 8 reads the sequential synoptic diagram for phase transition storage provided by the invention.
Fig. 9 is core memory array figure provided by the invention.
Figure 10 is the electrical schematic diagram that 1R1T provided by the invention is connected with driving circuit.
Figure 11 reads the amplifying circuit synoptic diagram for phase transition storage provided by the invention.
Embodiment
A specific embodiment of 1R1T specific implementation of the present invention as shown in Figure 4, at first is to finish basic circuit part by the standard CMOS process line, and drain terminal one deck of gate tube connects by outermost metal, deposits SiO then on this layer metal
2And etch a less through hole 3, and fill and go up tungsten (as bottom electrode), be right after this than small through hole be another big slightly through hole 4, so far, all finish with standard CMOS process.Adopt the GST processing line then, sputter last layer phase-change material GST at first, bigger through hole above covering etches away unnecessary GST then, (can add one deck SiO
2), long thereon again layer of metal aluminium (Al) is as top electrode 5, and etching finally covers one deck passivation layer silicon dioxide.
Like this, phase change memory chip is in storage array the phase change resistor GST part, the remaining circuit part can be finished with the standard CMOS process line earlier, and then comprise phase-change material with the manufacturing of GST processing line, the phase change resistor of top electrode, its bottom electrode and gate tube drain terminal link together, and top electrode meets maximum level VDD.When specifically making this phase change memory chip, with common CMOS processing line all circuit parts are finished earlier, use follow-up GST technology then, avoided original C MOS processing line, like this, with twice technology separately, do not change original CMOS processing line, save cost, increased the manufacture of phase transition storage.
According to one embodiment of present invention, lower floor is of a size of 0.26 μ m * 0.26 μ m, the bottom electrode size that also promptly contacts with GST than small through hole; The upper strata is of a size of 0.8 μ m * 0.8 μ m than large through-hole, and phase-change material GST is of a size of 5 μ m * 5 μ m.Certainly, these sizes change to some extent according to different embodiment.
The 1R1T structure that the storage unit of core adopts, as shown in Figure 5, its gate tube T is between phase change resistor GST and drive current source, that is to say, the source end of this gate tube is also unearthed, during specific design, because the substrate of gate tube meets minimum level VSS when making, and gate tube source end is owing to connect the drive current one-level, it is not zero level, there is the inclined to one side effect of a lining in inevitable like this this gate tube that makes, like this, under identical grid voltage, this gate tube can reduce the maximum current that flows through, but owing to the electric current that phase change cells is carried out the phase transformation operation does not need very big (2mA is following to get final product), like this, do not need very big size, under the high level grid voltage of determining, drive current can pass through gate tube, so only need size phase strain with gate tube bigger but do not need big a lot, and because phase-change material adds that the area of upper/lower electrode has a definite scope, as long as guarantee that the gate tube width is a lot of greatly unlike aforementioned dimensions,, just can guarantee can too much not increase the area of entire chip.
In addition, adopt 1R1T structure of the present invention, be added on the gate tube the pressure drop meeting than the pressure drop on the gate tube in the 1R1T structure of source end ground connection more greatly, but this moment, the final drive current that arrives on the phase change cells is produced by the pipe of the NMOS in the current mirror of the second level, and final drive current is produced by the PMOS pipe in the 1R1T structure of traditional gate tube source end ground connection, under the drive current of identical supply voltage and definite size, integrated circuit is not than traditional more power consumption of circuit structure consumption, like this, also guaranteed the low-power consumption requirement of phase change memory chip.
According to embodiment shown in Figure 6, the phase change memory chip internal circuit synoptic diagram of invention mainly comprises phase-changing memory cell array, address decoder (line is selected circuit and bit line select circuitry), the reading and writing driving circuit, Drive and Control Circuit and read amplifying circuit.Which storage unit the decoding circuit decision chooses, the control circuit control Driver Circuit applies the current impulse of certain width to the unit of choosing, and act on the storage unit by the current impulse that driving circuit section produces a certain size, storage unit is undergone phase transition; Sensing circuit is used to read the state of memory cells after being applied.Fig. 7,8 has provided the sequential relationship of chip read-write.
Fig. 9 has provided the storage array synoptic diagram of core.As an embodiment, chip adopts the mode of octet output, respective design 8 driving circuits and 8 structures of reading amplifying circuit.
As embodiment, be specially a two-stage current mirroring circuit by driving circuit shown in Figure 10 and reading method circuit shown in Figure 11, the final generation is used for Set, Reset, the drive current that varies in size of Read.Between first order current mirroring circuit and second level current mirroring circuit, add gauge tap SWITCH1, SWITCH2, SWITCH3, the opening and close by Drive and Control Circuit and partly control of these gauge tap.Drive and Control Circuit is the control signal that produces certain pulsewidth by pulse signal generator, the opening and the shut-in time of switch in the control back level current mirror, make thus be added on the phase change cells for certain pulsewidth and the high pulse signal of arteries and veins being arranged, realization Reset, Set, the Read operation.
When carrying out write operation, it at first is example with Reset, need apply a weak point and strong voltage or current impulse, electric energy is transformed into heat energy, the temperature of phase-change material is elevated to more than the temperature of fusion,, the long-range order of polycrystalline is destroyed through cooling fast, thereby realize that low-resistance becomes high resistant by the conversion of polycrystalline to amorphous.At first gate tube NT is opened by the high level of decoding circuit output, by Drive and Control Circuit switch SW ITCH1 is opened subsequently, and SWITCH2, SWITCH3 is in closed condition at this moment, like this, by PMOS pipe P0, the current mirror that P1 forms, produce a certain size and certain multiple in the electric current I 1 of reference current Ibias; Same, by NMOS pipe N1, the current mirror that N4 forms with I1 once more mirror image obtain required Reset electric current I 1 ', I1 ' is applied on the phase change cells GST by transmission gate TG that opens and the gate tube NT that opens, thereby phase-change material is undergone phase transition, the sequential of SWTICH1 has determined the width of the Reset current impulse that applied, and requirement is short pulse, is generally less than for 50 nanoseconds.
When wiping (Set), need apply a voltage or a current impulse long and intensity is medium, the temperature of phase-change material is elevated to more than the Tc, be lower than temperature of fusion, keep the regular hour (being generally less than for 50 nanoseconds), make phase-change material be converted into polycrystalline by amorphous, high resistant becomes low-resistance.During concrete enforcement, SWITCH1, SWITCH3 closes, SWITCH2 opens, by managing P0 by PMOS, P2 and NMOS pipe N2, the two-stage current mirror that N5 forms produces required Set electric current I 2 ', be applied on the phase change cells GST, phase-change material is taken place by the conversion of amorphous state to crystalline state, the sequential of SWITCH2 has determined the Set current pulse width that applied.Requirement is a long slightly pulse, between 150～200 nanoseconds.
When reading (Read) operation, switch SW ITCH4 opens, and transmission gate TG opens, SWITCH1 in the current mirror, SWITCH2 closes, and SWITCH3 opens, by PMOS pipe P0, P32 and NMOS pipe N3, the two-stage current mirror that N6 forms produces the read current I3 ' of required sizing really, is applied on the phase change cells GST, and this read current is enough little, the heat energy that produces guarantees that the temperature of phase-change material is lower than Tc all the time, and material does not undergo phase transition.The essence of reading is the voltage condition of reading on the GST unit, sees the resistance situation by its voltage.This voltage is compared amplification with a reference voltage through sense amplifier and is read by port SOUT output, and the read-out voltage when crystalline state and amorphous state can strict distinguish.The read current pulse width that is applied is by the sequential decision of SWITCH2.
Above-mentioned current-mirror structure also can adopt cascode structure or other to improve structure, can make the electric current of mirror image not be subjected to the influence of load variations.
Claims (10)
1, a kind of phase transition storage 1R1T structure is characterized in that an end of the source termination driving circuit of gate tube, and drain terminal connects phase change resistor, the bit line of grid termination phase transformation array, the maximum level VDD of the other end connection circuit of phase change resistor.
2, by the described phase transition storage 1R1T of claim 1 structure, it is characterized in that described gate tube is a N NMOS N-channel MOS N pipe.
3, by the described phase transition storage 1R1T of claim 1 structure, it is characterized in that described phase-changing memory cell array comprises several word lines, several bit lines and is in word line and several phase-change memory cells of the bit line zone of intersection.
4,, it is characterized in that described each phase-change memory cell is by a word line, a gate tube and a phase change resistor definition by the described phase transition storage 1R1T of claim 3 structure.
5, by the described phase transition storage 1R1T of claim 3 structure, it is characterized in that described phase transition storage comprises address decoding circuitry, Drive and Control Circuit, read-write drive circuit, reads the storage array of amplifying circuit and core;
Wherein, each phase-change memory cell comprises a phase-change material GST that can programme between amorphous state and crystalline state; The NMOS gate tube that connects each storage unit, it is connected by certain mode with phase-change memory cell, and several such linkage units constitute the storage array of phase transition storage core;
Address decoding circuitry is used to select at least one storage unit;
Drive and Control Circuit is used to control the phase-change memory cell of choosing is carried out reading and writing, wipes operation, produces certain pulse width;
The reading and writing driving circuit is used to generate the phase-change memory cell of choosing is applied the read current that carries out read operation, and the phase-change memory cell of choosing is programmed for amorphous wiping electric current and is programmed for the write current of crystalline state;
Read amplifying circuit, be used for the state of storage unit is read amplification.
6, the design of drive circuit method that is used for each described phase transition storage 1R1T structure of claim 1-5, it is characterized in that by the two-stage current mirroring circuit, wherein the first order comprises three current mirrors that formed by three pairs of PMOS pipes, the second level comprises three current mirrors that formed by three pairs of NMOS pipes, and finally be coupled to bit line and impose on phase-change memory cell, produce the drive current that is used for reading and writing, wiping.
7, by the described method for designing that is used for the driving circuit of phase transition storage 1R1T structure of claim 6, it is characterized in that adding gauge tap in first order current mirroring circuit and second level current mirroring circuit, opening and closing of gauge tap is partly to be controlled by Drive and Control Circuit.
8, by the described method for designing that is used for the Drive and Control Circuit of phase transition storage 1R1T structure of claim 6, it is characterized in that producing the drive control signal of certain pulsewidth by pulse signal generator, the opening and closing of switch in the control back level current mirror, the electric current that is added on the phase-change memory cell is the signal that certain pulsewidth is arranged.
9,, it is characterized in that producing the pulse of pulsewidth less than 50 nanoseconds by the described method for designing that is used for the Drive and Control Circuit of phase transition storage 1R1T structure of claim 8.
10, by the described method for designing that is used for the Drive and Control Circuit of phase transition storage 1R1T structure of claim 6, it is characterized in that described current mirror adopts cascode structure, make the electric current of mirror image not be subjected to the influence of load variations.
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Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN102096050A (en) * | 2010-12-10 | 2011-06-15 | 奇瑞汽车股份有限公司 | Detection device of direct current-direct current power supply circuit |
| CN103093816A (en) * | 2013-01-29 | 2013-05-08 | 中国科学院苏州纳米技术与纳米仿生研究所 | Phase change memory driving circuit and setting and resetting method |
| CN104380385A (en) * | 2012-05-15 | 2015-02-25 | 美光科技公司 | Apparatuses including current compliance circuits and methods |
| CN113315506A (en) * | 2021-05-07 | 2021-08-27 | 中国科学院上海微系统与信息技术研究所 | Phase change memory time sequence reconfigurable Boolean logic circuit, method and device |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN102096050A (en) * | 2010-12-10 | 2011-06-15 | 奇瑞汽车股份有限公司 | Detection device of direct current-direct current power supply circuit |
| CN104380385A (en) * | 2012-05-15 | 2015-02-25 | 美光科技公司 | Apparatuses including current compliance circuits and methods |
| CN104380385B (en) * | 2012-05-15 | 2017-11-17 | 美光科技公司 | The device and method of rule circuit are closed comprising electric current |
| US10210928B2 (en) | 2012-05-15 | 2019-02-19 | Micron Technology, Inc. | Apparatuses including current compliance circuits and methods |
| CN103093816A (en) * | 2013-01-29 | 2013-05-08 | 中国科学院苏州纳米技术与纳米仿生研究所 | Phase change memory driving circuit and setting and resetting method |
| CN103093816B (en) * | 2013-01-29 | 2015-08-05 | 中国科学院苏州纳米技术与纳米仿生研究所 | Phase-change memorizer driver circuit and set and repositioning method |
| CN113315506A (en) * | 2021-05-07 | 2021-08-27 | 中国科学院上海微系统与信息技术研究所 | Phase change memory time sequence reconfigurable Boolean logic circuit, method and device |
| CN113315506B (en) * | 2021-05-07 | 2024-04-05 | 中国科学院上海微系统与信息技术研究所 | Phase-change memory time sequence reconfigurable Boolean logic circuit, method and device |
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