CN101281989A - Co-plane waveguide based on SOI substrate and manufacturing method thereof - Google Patents

Abstract

The invention provides a coplanar wave guide based on SOI substrate, which includes a SOI substrate, a silicon dioxide layer formed on the SOI substrate, a ground line and a signal line formed on the silicon dioxide layer and arranged at an interval, wherein a corrosion hole band along the ground line an the signal line is arranged on a interval band between the adjacent ground line and the signal line, and bottom of the corrosion hole band forms a strip-type groove. The invention also provides a preparation method for the coplanar wave guide based on the SOI substrate. On precondition of not increasing size of the coplanar wave guide and other loss, the coplanar wave guide based on the SOI substrate can reduce effective dielectric constant of medium, thereby reducing medium loss and increasing transmission characteristic.

Description

Based on co-plane waveguide of SOI substrate and preparation method thereof

Technical field

The invention belongs to integrated circuit (IC)-components and make the field, relate in particular to a kind of co-plane waveguide based on silicon-on-insulator (SOI) substrate and preparation method thereof.

Background technology

In CMOS (Complementary Metal Oxide Semiconductor) (CMOS) radio frequency integrated circuit (RFIC), microwave transmission line is indispensable part, and its main application is the loss transmission electromagnetic energy with minimum.In addition, microwave transmission line also is used to constitute microwave devices such as resonant circuit, filter.

Co-plane waveguide is one of transmission line the most frequently used in the radio frequency integrated circuit, and the factor that influences the co-plane waveguide loss has conductor losses, dielectric loss, radiation loss.Wherein mainly be conductor losses and dielectric loss.Conductor losses is mainly caused by the resistance of metallic conductor itself, skin effect and proximity effect under the high frequency.Skin effect is inevitable under high frequency, and its power is by material and frequency decision; Proximity effect is because wire coil is close mutually, and electromagnetic interference causes that electric current causes the increase of conductor resistance inhomogeneous the flowing of cross-sectional area of conductor, can be improved by the distance that increases between ground wire and the holding wire.But above-mentioned distance is closely related with the co-plane waveguide characteristic impedance, and increases apart from being unfavorable for improving integrated level, and is main at present by reducing the loss that dielectric loss reduces co-plane waveguide.Solution comprises: cover advanced low-k materials on low-resistance silicon, as polyimide film; Adopt the high resistant substrate, as High Resistivity Si or porous silicon substrate; Adopt ground shield technology etc.

CMOS technology generally all adopts the higher silicon substrate that mixes, and energy loss is more when radio circuit is worked, so, on such substrate, be difficult to form high-quality passive device.And more serious under the high frequency by crosstalking of low-resistance silicon substrate, be difficult to integrated high performance circuit, as radio circuit, analog circuit, digital circuit etc.In order to overcome intrinsic shortcoming in the silicon CMOS radio frequency technology, people are just seeking the substitute technology of silicon CMOS technology, as technology such as SiGe, SiC, SOI, wherein the SOI technology overcomes the deficiency of body silicon materials with its unique material structure, can reduce parasitic capacitance, pick up speed reduces power consumption, reducing to crosstalk, is most promising silicon CMOS substitute technology.Therefore design seems very necessary based on the low-loss co-plane waveguide of SOI substrate.

Summary of the invention

Technical problem solved by the invention be to provide a kind of effective dielectric constant less based on co-plane waveguide of SOI substrate and preparation method thereof, to reduce the diectric attenuation constant of co-plane waveguide, improve transmission characteristic.

In order to solve the problems of the technologies described above, the invention provides a kind of co-plane waveguide based on the SOI substrate, described co-plane waveguide comprises the SOI substrate, be formed on the silicon dioxide layer on the SOI substrate, and be formed on the silicon dioxide layer and ground wire and the holding wire alternately arranged, wherein, offer on the intervallum between adjacent ground wire and the holding wire along the corrosion pore area of ground wire and holding wire trend, and the below of corrosion pore area forms strip groove.

Further, described co-plane waveguide comprises two ground wires and a signal line, be opened in and form two strip grooves between these two ground wires and the signal line, the degree of depth that described groove is offered is the buried oxidation layer that exposes SOI underlayer surface silicon below, and the cell wall of described groove and the angle of silicon dioxide layer are 0 °～90 °.

Another program of the present invention provides a kind of manufacture method of the co-plane waveguide based on the SOI substrate, and described method comprises the following steps:

One SOI substrate is provided, and described SOI underlayer surface silicon below has buried oxidation layer;

On described SOI substrate, deposit layer of silicon dioxide, on silicon dioxide layer, form a metal level, remove part metals, form a signal line and two ground wires, and described holding wire is clipped between two ground wires by photoetching, etching;

Form two corrosion pore areas by photoetching, etching on the silicon dioxide layer of intervallum between described holding wire and the ground wire, described etch pit is evenly arranged on the intervallum, exposes SOI underlayer surface silicon;

By etch pit, the SOI underlayer surface silicon below the described intervallum is eroded, form strip groove.

Further, described SOI substrate adopts preparation such as the technology of annotating oxygen isolation, wafer bonding or smart peeling.

Further, use etching process, erode by the SOI underlayer surface silicon of etch pit with described intervallum below.

Further, adopt the described silicon dioxide layer of plasma reinforced chemical vapour deposition process deposits.

Co-plane waveguide based on the SOI substrate of the present invention can reduce the effective dielectric constant of medium, thereby reduce dielectric loss not increasing the co-plane waveguide size and not causing under the prerequisite of other loss increase.Compare with existing co-plane waveguide based on the SOI substrate, co-plane waveguide of the present invention has been removed electromagnetic field and has been concentrated the holding wire of distribution and the underlayer surface silicon of the below between the ground wire, makes this cavity dielectric constant near 1, has reduced effective dielectric constant ε _Eff, reduced dielectric loss, thereby can effectively improve transmission characteristic.

Description of drawings

By following examples and in conjunction with the description of its accompanying drawing, can further understand purpose, specific structural features and the advantage of its invention.Wherein, accompanying drawing is:

Fig. 1 is the cross-sectional structure schematic diagram of the co-plane waveguide based on the SOI substrate of the present invention.

Fig. 2 is the vertical section structure schematic diagram of the co-plane waveguide based on the SOI substrate of the present invention.

Fig. 3 is the structure vertical view of the co-plane waveguide based on the SOI substrate of the present invention.

Fig. 4 is the manufacture method flow chart of the co-plane waveguide based on the SOI substrate of the present invention.

Fig. 5 finishes the co-plane waveguide structure cutaway view behind the step S10 among Fig. 4.

Fig. 6 finishes the co-plane waveguide structure cutaway view behind the step S20 among Fig. 4.

Fig. 7 finishes the co-plane waveguide structure cutaway view behind the step S30 among Fig. 4.

Embodiment

Below will be described in further detail co-plane waveguide based on the SOI substrate of the present invention and preparation method thereof.

Co-plane waveguide based on the SOI substrate of the present invention is based on the SOI art designs, and Fig. 1, Fig. 2 are the cross section and the vertical section structure schematic diagrames of this co-plane waveguide, and is corresponding to respectively waveguide and the direction that is parallel to waveguide.Referring to Fig. 1, Fig. 2, and in conjunction with reference structure vertical view shown in Figure 3, co-plane waveguide based on the SOI substrate of the present invention comprises SOI substrate 10, be formed on the silicon dioxide layer 20 on the SOI substrate 10, and be formed on ground wire 31 (G) and holding wire 32 (S) on the silicon dioxide layer 20, wherein, Fig. 2 ground wire/holding wire that do not draw.

Particularly, this SOI substrate 10 can adopt technology preparations such as injection oxygen isolation technology, wafer bonding or smart peeling.

Different with existing co-plane waveguide is, co-plane waveguide of the present invention is offered several etch pits 40 on the intervallum between adjacent ground wire 31 and the holding wire 32, these etch pits 40 constitute along the corrosion pore area of ground wire 31 and holding wire 32 trends, and form strip groove 50 below the corrosion pore area.

In a preferred embodiment of the invention, this co-plane waveguide comprises two ground wires 31 and a signal line 32, all adopts metal (for example aluminium) to make.Between two ground wires 31 and a signal line 32, form two strip grooves 50, the degree of depth that described groove 50 is offered is the buried oxidation layer 11 that exposes SOI underlayer surface silicon 12 belows, and the cell wall 51 of described groove 50 is 0 °～90 ° with the angular range of silicon dioxide passivation layer 20.

Referring to Fig. 4, cooperate with reference to Fig. 5 to Fig. 7, the co-plane waveguide based on the SOI substrate of the present invention adopts following method to make:

At first, execution in step S10 provides a SOI substrate 10, adopts plasma reinforced chemical vapour deposition technology deposition of silica layer 20 on substrate 10, and forms a metal level 30 on silicon dioxide layer 20.Co-plane waveguide structure behind the completing steps S10 as shown in Figure 5.

Then, execution in step S20 removes part metals 30 by photoetching, etching, forms holding wire 32 and ground wire 31.Co-plane waveguide structure behind the completing steps S20 as shown in Figure 6.

Then, execution in step S30 forms several etch pits 40 by photoetching, etching on the silicon dioxide layer 20 of intervallum between holding wire 32 and the ground wire 31, forms along the corrosion pore area of ground wire 31 and holding wire 32 trends, exposes SOI underlayer surface silicon 12.Co-plane waveguide structure behind the completing steps S30 as shown in Figure 7.

At last, execution in step S40, erodes the SOI underlayer surface silicon 12 below the intervallum by etch pit 40 with etching process, forms strip groove 50.The corrosion depth of described strip groove 50 is for exposing buried oxidation layer 11.The cell wall 51 of strip groove 50 and the angle of silicon dioxide layer 20 are because etching process and substrate situation different are divided into following several situation:

Embodiment one, with corrosive liquids such as KOH to the top layer silicon wafer to index for { SOI of 100} carries out wet etching, because solution is to { corrosion rate of 100} silicon is than { corrosion of 111} silicon is faster, under the sufficiently long situation of etching time, cell wall 51 orientation index of strip groove 50 be 111}, the cell wall 51 of strip groove 50 is 54.7 ° with the angle of silicon dioxide layer 20;

Embodiment two, with corrosive liquids such as KOH to the top layer silicon wafer to index for { SOI of 100} carries out wet etching, if surface silicon thickness is very little or etching time falls short of, the not arrival of cell wall 51 of strip groove 50 the 111} crystal face, the cell wall 51 of strip groove 50 and the angle of silicon dioxide layer 20 are less than 54.7 °;

Embodiment three, be that the SOI of any orientation index carries out wet etching with corrosive liquids such as KOH to surface silicon, the cell wall 51 of strip groove 50 is the acute angle of uncertain angle with the angle of silicon dioxide layer 20;

Embodiment four, pass through Cl ₂Carry out reactive ion etching Deng gas, can obtain subvertical etching profile, the cell wall 51 of strip groove 50 and the angle of silicon dioxide layer 20 are near 90 °.

Therefore, the angle of the cell wall 51 of strip groove 50 and silicon dioxide layer 20 is between 0 ° to 90 °.After finishing above steps, promptly obtain co-plane waveguide of the present invention shown in Figure 1.

Transmission principle below in conjunction with co-plane waveguide illustrates technique effect of the present invention.

Transmission line in the integrated circuit is lossy.R _t, L _t, C _tAnd G _tThe distributed resistance, distributed inductance, distributed capacitance and the distribution electricity that are respectively the transmission line unit length are led.When high frequency, these parameters can present the influence to energy or signal transmission.The amplitude and the phase place of incident wave voltage and current along the line will be by index law e ^{-γ z}Decay.Wherein γ is a propagation constant:

$\mathrm{\γ}=\sqrt{(R_t+\mathrm{j\ω}{L}_t)(G_t+\mathrm{j\ω}{C}_t)}=\mathrm{\α}+\mathrm{j\β}$ (formula 1)

Be used for describing decay and the phase change of guided wave along the navigation system communication process.Wherein real part α is called attenuation constant, the variation of representation unit length row wave-amplitude; Imaginary part β is called phase-shift constant, the variation of representation unit length traveling-wave phase.

For microwave transmission line (R _t＜＜ω L _t, G _t＜＜ω C _t):

$\mathrm{\α}=\frac{R_t}{2Z_c}+\frac{G_t{Z}_c}{2},$ $\mathrm{\β}=\mathrm{\ω}\sqrt{L_t{C}_t}$ (formula 2)

Z _cCharacteristic impedance for transmission line:

$Z_c=\sqrt{\frac{\mathrm{j\ω}{L}_t(1+\frac{R_t}{\mathrm{j\ω}{L}_t})}{\mathrm{j\ω}{C}_t(1+\frac{G_t}{\mathrm{j\ω}{C}_t})}}\≈\sqrt{\frac{L_t}{C_t}}$ (formula 3)

As seen the attenuation constant of transmission line depends on the resistance loss of lead itself and the dielectric loss between lead.

The loss of co-planar waveguide is mainly derived from dielectric loss and conductor losses, and its attenuation constant α can be expressed as α=α _Die+ α _Con, α wherein _DieBe the attenuation constant of medium, α _ConAttenuation constant for conductor.

Dielectric loss is an electric field when passing through medium, owing to medium molecule alternant polarization and lattice collide the thermal losses that produces back and forth.It is mainly reflected on the distributed capacitance.If it is ε that co-plane waveguide all is in relative dielectric constant _rMedium in, its distributed capacitance C _tThan increase ε during for medium with the air _rDoubly.But a signal part of transmitting on the co-plane waveguide is ε at dielectric constant usually _rMedium in, another part is in air.Be equivalent to be in a kind of blending agent, need to introduce effective dielectric constant ε _EffQ revises with the medium fill factor, curve factor:

${\mathrm{\ϵ}}_{\mathrm{eff}}=\frac{{\mathrm{\ϵ}}_r+1}{2}$ (formula 4)

$q=\frac{{\mathrm{\ϵ}}_{\mathrm{eff}}-1}{{\mathrm{\ϵ}}_r-1}$ (formula 5)

Co-plane waveguide diectric attenuation constant alpha then _DieFor:

${\mathrm{\α}}_{\mathrm{die}}=\frac{27.3}{{\mathrm{\λ}}_0}\left(\frac{q{\mathrm{\ϵ}}_r}{\sqrt{{\mathrm{\ϵ}}_{\mathrm{eff}}}}\right)\mathrm{tg\δ}=\frac{27.3}{{\mathrm{\λ}}_0}\frac{{\mathrm{\ϵ}}_r}{\sqrt{{\mathrm{\ϵ}}_{\mathrm{eff}}}}\frac{{\mathrm{\ϵ}}_{\mathrm{eff}}-1}{{\mathrm{\ϵ}}_r-1}\mathrm{tg\δ}$ (formula 6)

In the formula, λ ₀Be free space wavelength, ε _rBe the medium dielectric constant, tg δ is a loss angle tangent, ε _EffBe effective dielectric constant.

Because electromagnetic field mainly is distributed in the dielectric layer of ground wire and holding wire below, therefore when calculating effective dielectric constant, mainly consider the relative dielectric constant of this zone medium.Ignore silicon dioxide passivation layer, by formula 4 as can be known, the ε of the co-plane waveguide based on SOI of the present invention _Eff≈ 1, and the ε of existing co-plane waveguide _Eff≈ 7.This shows that the effective dielectric constant of the co-plane waveguide based on SOI of the present invention can make co-plane waveguide diectric attenuation constant alpha much smaller than the effective dielectric constant of existing co-plane waveguide _DieBe minimized, thereby transmission characteristic is improved.

Claims (9)

1, a kind of co-plane waveguide based on silicon-on-insulator (SOI) substrate, described co-plane waveguide comprises the SOI substrate, be formed on the silicon dioxide layer on the SOI substrate, and be formed on the silicon dioxide layer and ground wire and the holding wire alternately arranged, it is characterized in that: offer on the intervallum between adjacent ground wire and the holding wire along the corrosion pore area of ground wire and holding wire trend, and the below of corrosion pore area forms strip groove.

2, co-plane waveguide as claimed in claim 1 is characterized in that: described co-plane waveguide comprises two ground wires and a signal line, forms two strip grooves between these two ground wires and a signal line.

3, co-plane waveguide as claimed in claim 1 is characterized in that: described SOI underlayer surface silicon below has buried oxidation layer, and the degree of depth that described groove is offered is for exposing buried oxidation layer.

4, co-plane waveguide as claimed in claim 1 is characterized in that: the cell wall of described groove and the angle of silicon dioxide layer are 0 °～90 °.

5, a kind of manufacture method of the co-plane waveguide based on the SOI substrate is characterized in that described method comprises the following steps:

One SOI substrate is provided, and described SOI underlayer surface silicon below has buried oxidation layer;

On described SOI substrate, deposit layer of silicon dioxide, on silicon dioxide layer, form a metal level, remove part metals, form a signal line and two ground wires, and described holding wire is clipped between two ground wires by photoetching, etching;

Form two corrosion pore areas by photoetching, etching on the silicon dioxide layer of intervallum between described holding wire and the ground wire, described etch pit is evenly arranged on the intervallum, exposes SOI underlayer surface silicon;

By etch pit, the SOI underlayer surface silicon below the described intervallum is eroded, form strip groove.

6, manufacture method as claimed in claim 5 is characterized in that, described SOI substrate adopts injection oxygen isolation technology, wafer bonding or the preparation of smart peeling technology.

7, manufacture method as claimed in claim 5 is characterized in that: adopt the described silicon dioxide layer of plasma reinforced chemical vapour deposition process deposits.

8, manufacture method as claimed in claim 5 is characterized in that: use etching process, erode by the SOI underlayer surface silicon of etch pit with described intervallum below.

9, manufacture method as claimed in claim 5 is characterized in that: the corrosion depth of described strip groove is for exposing buried oxidation layer.

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