CN101281989A - Coplanar waveguide based on SOI substrate and its fabrication method - Google Patents

Abstract

The invention provides a coplanar waveguide based on an SOI substrate and a manufacturing method thereof. The coplanar waveguide includes an SOI substrate, a silicon dioxide layer formed on the SOI substrate, and a ground line and a signal line formed on the silicon dioxide layer and arranged at intervals, wherein the adjacent ground line and the signal line Corrosion hole strips along the direction of the ground wire and the signal line are provided on the interval strips between them, and strip-shaped grooves are formed under the corrosion hole strips. The present invention also correspondingly provides a method for manufacturing the coplanar waveguide based on the SOI substrate. The coplanar waveguide based on the SOI substrate of the present invention can reduce the effective dielectric constant of the medium without increasing the size of the coplanar waveguide and causing no increase in other losses, thereby reducing the dielectric loss and improving the transmission characteristics.

Description

Coplanar waveguide based on SOI substrate and its fabrication method

technical field

The invention belongs to the field of integrated circuit device manufacturing, in particular to a coplanar waveguide based on a silicon-on-insulator (SOI) substrate and a manufacturing method thereof.

Background technique

In complementary metal-oxide-semiconductor (CMOS) radio-frequency integrated circuits (RFICs), microwave transmission lines are an integral component whose main purpose is to transmit electromagnetic energy with minimal loss. In addition, microwave transmission lines are also used to form microwave components such as resonant circuits and filters.

Coplanar waveguide is one of the most commonly used transmission lines in radio frequency integrated circuits. Factors affecting the loss of coplanar waveguide include conductor loss, dielectric loss, and radiation loss. The main ones are conductor loss and dielectric loss. Conductor loss is mainly caused by the resistance of the metal conductor itself, the skin effect at high frequencies, and the proximity effect. The skin effect is inevitable at high frequencies, and its strength is determined by the material and frequency; the proximity effect is due to the proximity of the metal coils to each other, and electromagnetic interference causes the current to flow unevenly in the conductor cross section, resulting in an increase in the resistance of the wire. It can be increased by increasing the ground wire and The distance between signal lines was improved. However, the above distance is closely related to the characteristic impedance of the coplanar waveguide, and increasing the distance is not conducive to improving the integration level. At present, the transmission loss of the coplanar waveguide is mainly reduced by reducing the dielectric loss. Solutions include: covering low-resistance silicon with low dielectric constant materials, such as polyimide film; using high-resistance substrates, such as high-resistance silicon or porous silicon substrates; using ground shielding technology, etc.

The CMOS process generally uses a highly doped silicon substrate, and the energy loss is large when the radio frequency circuit is working. Therefore, it is difficult to form high-quality passive devices on such a substrate. Moreover, the crosstalk through the low-resistance silicon substrate is serious at high frequencies, making it difficult to integrate high-performance circuits, such as radio frequency circuits, analog circuits, digital circuits, etc. In order to overcome the inherent shortcomings of silicon CMOS radio frequency technology, people are looking for alternative technologies of silicon CMOS technology, such as SiGe, SiC, SOI and other technologies. Among them, SOI technology overcomes the shortage of bulk silicon materials with its unique material structure and can reduce parasitic Capacitors, for faster speed, lower power consumption, and less crosstalk, are the most promising silicon CMOS replacement technology. Therefore, it is very necessary to design low-loss coplanar waveguides based on SOI substrates.

Contents of the invention

The technical problem solved by the present invention is to provide a coplanar waveguide based on an SOI substrate with a small equivalent dielectric constant and its manufacturing method, so as to reduce the dielectric attenuation constant of the coplanar waveguide and improve transmission characteristics.

In order to solve the above technical problems, the present invention provides a coplanar waveguide based on an SOI substrate. The coplanar waveguide includes an SOI substrate, a silicon dioxide layer formed on the SOI substrate, and a silicon dioxide layer formed on the silicon dioxide layer. And alternately arranged ground wires and signal wires, wherein, the space between adjacent ground wires and signal wires is provided with corrosion hole belts along the direction of the ground wires and signal wires, and strip-shaped grooves are formed under the corrosion hole belts .

Further, the coplanar waveguide includes two ground wires and one signal wire, two strip-shaped grooves are formed between the two ground wires and one signal wire, and the depth of the grooves is such that the SOI For the buried oxide layer under the surface silicon of the substrate, the included angle between the groove wall of the groove and the silicon dioxide layer is 0°-90°.

Another solution of the present invention is to provide a method for manufacturing a coplanar waveguide based on an SOI substrate, the method comprising the following steps:

An SOI substrate is provided, and a buried oxide layer is provided under the surface silicon of the SOI substrate;

A layer of silicon dioxide is deposited on the SOI substrate, a metal layer is formed on the silicon dioxide layer, and part of the metal is removed by photolithography and etching to form a signal line and two ground lines, and the signal line Sandwiched between two ground wires;

On the silicon dioxide layer of the spacer between the signal line and the ground line, two etching holes are formed by photolithography and etching, and the etching holes are evenly arranged on the spacer, exposing the silicon on the surface of the SOI substrate;

Through the etching holes, the silicon on the surface layer of the SOI substrate under the spacer strips is etched away to form strip-shaped grooves.

Further, the SOI substrate is prepared by techniques such as oxygen injection isolation, silicon wafer bonding or intelligent stripping.

Further, the silicon on the surface layer of the SOI substrate under the spacer zone is etched away through the etching hole by using an etching process.

Further, the silicon dioxide layer is deposited by a plasma enhanced chemical vapor deposition process.

The coplanar waveguide based on the SOI substrate of the present invention can reduce the effective dielectric constant of the medium without increasing the size of the coplanar waveguide and causing other losses to increase, thereby reducing the dielectric loss. Compared with the existing coplanar waveguide based on SOI substrate, the coplanar waveguide of the present invention removes the silicon on the surface layer of the substrate between the signal line and the ground line where the electromagnetic field is concentrated, so that the dielectric constant of the cavity is close to 1. The effective dielectric constant ε _eff is reduced, and the dielectric loss is reduced, so that the transmission characteristics can be effectively improved.

Description of drawings

Through the description of the following embodiments combined with the accompanying drawings, the purpose, specific structural features and advantages of the invention can be further understood. Among them, the attached figure is:

Fig. 1 is a schematic cross-sectional structure diagram of a coplanar waveguide based on an SOI substrate according to the present invention.

Fig. 2 is a schematic diagram of the longitudinal section structure of the coplanar waveguide based on the SOI substrate of the present invention.

Fig. 3 is a top view of the structure of the coplanar waveguide based on the SOI substrate of the present invention.

Fig. 4 is a flow chart of the manufacturing method of the coplanar waveguide based on the SOI substrate of the present invention.

FIG. 5 is a cross-sectional view of the coplanar waveguide structure after step S10 in FIG. 4 is completed.

FIG. 6 is a cross-sectional view of the coplanar waveguide structure after step S20 in FIG. 4 is completed.

FIG. 7 is a cross-sectional view of the coplanar waveguide structure after step S30 in FIG. 4 is completed.

Detailed ways

The SOI substrate-based coplanar waveguide of the present invention and its manufacturing method will be further described in detail below.

The coplanar waveguide based on the SOI substrate of the present invention is designed based on SOI technology. Fig. 1 and Fig. 2 are schematic diagrams of the cross-section and longitudinal section structure of the coplanar waveguide, corresponding to directions perpendicular to the waveguide and parallel to the waveguide respectively. Referring to Fig. 1, Fig. 2, and in conjunction with referring to the top view of the structure shown in Fig. 3, the coplanar waveguide based on the SOI substrate of the present invention comprises an SOI substrate 10, a silicon dioxide layer 20 formed on the SOI substrate 10, and Ground wires 31 (G) and signal wires 32 (S) are formed on the silicon dioxide layer 20 , wherein the ground wires/signal wires are not shown in FIG. 2 .

Specifically, the SOI substrate 10 can be prepared by using technologies such as oxygen implantation isolation technology, silicon wafer bonding, or intelligent lift-off.

Different from the existing coplanar waveguide, the coplanar waveguide of the present invention provides several corrosion holes 40 on the interval between adjacent ground wires 31 and signal wires 32, and these corrosion holes 40 constitute a The pattern of the signal line 32 is etched with holes, and a strip-shaped groove 50 is formed under the corroded holes.

In a preferred embodiment of the present invention, the coplanar waveguide includes two ground wires 31 and one signal wire 32, both of which are made of metal (such as aluminum). Two strip-shaped grooves 50 are formed between the two ground wires 31 and one signal wire 32. The depth of the grooves 50 is such that the buried oxide layer 11 under the surface silicon 12 of the SOI substrate is exposed. The included angle between the groove wall 51 of the groove 50 and the silicon dioxide passivation layer 20 ranges from 0° to 90°.

Referring to Fig. 4, with reference to Fig. 5 to Fig. 7, the coplanar waveguide based on SOI substrate of the present invention is made by the following method:

Firstly, step S10 is performed, providing an SOI substrate 10 , depositing a silicon dioxide layer 20 on the substrate 10 by using a plasma-enhanced chemical vapor deposition process, and forming a metal layer 30 on the silicon dioxide layer 20 . The coplanar waveguide structure after step S10 is completed is shown in FIG. 5 .

Next, step S20 is performed to remove part of the metal 30 by photolithography and etching to form the signal line 32 and the ground line 31 . The coplanar waveguide structure after step S20 is completed is shown in FIG. 6 .

Then, step S30 is performed to form several etching holes 40 by photolithography and etching on the silicon dioxide layer 20 in the interval zone between the signal line 32 and the ground line 31 to form corrosion holes 40 along the direction of the ground line 31 and the signal line 32. The holes expose the silicon 12 on the surface of the SOI substrate. The coplanar waveguide structure after step S30 is completed is shown in FIG. 7 .

Finally, step S40 is performed to etch away the silicon 12 on the surface of the SOI substrate under the spacer through the etching hole 40 by an etching process to form a strip groove 50 . The etching depth of the stripe groove 50 is such that the buried oxide layer 11 is exposed. The angle between the groove wall 51 of the strip groove 50 and the silicon dioxide layer 20 is divided into the following situations due to the difference of the etching process and the substrate condition:

Example 1. Wet etch the SOI with crystal orientation index of {100} silicon on the surface layer with KOH etc., because the corrosion rate of {100} silicon by the solution is much faster than that of {111} silicon. If it is long enough, the crystal orientation index of the groove wall 51 of the strip-shaped groove 50 is {111}, and the angle between the groove wall 51 of the strip-shaped groove 50 and the silicon dioxide layer 20 is 54.7°;

Embodiment 2: Use KOH etchant etchant to carry out wet etching to the SOI whose surface layer silicon orientation index is {100}, if the thickness of the surface layer silicon is small or the etching time is not long enough, the groove wall 51 of the strip groove 50 does not reach { 111} crystal plane, the angle between the groove wall 51 of the strip groove 50 and the silicon dioxide layer 20 is less than 54.7°;

Embodiment 3, using KOH and other corrosive liquids to wet-etch SOI with any crystal orientation index on the surface layer silicon, the angle between the groove wall 51 of the strip groove 50 and the silicon dioxide layer 20 is an acute angle of uncertain angle;

Embodiment 4: Reactive ion etching is carried out by Cl ₂ and other gases to obtain a nearly vertical etching profile, and the angle between the groove wall 51 of the strip groove 50 and the silicon dioxide layer 20 is close to 90°.

Therefore, the included angle between the groove wall 51 of the strip groove 50 and the silicon dioxide layer 20 is between 0° and 90°. After completing the above steps, the coplanar waveguide of the present invention shown in FIG. 1 is obtained.

The technical effect of the present invention will be described below in conjunction with the transmission principle of the coplanar waveguide.

Transmission lines in integrated circuits are lossy. R _t , L _t , C _t and G _t are the distributed resistance, distributed inductance, distributed capacitance and distributed conductance per unit length of the transmission line, respectively. At high frequencies, these parameters can appear to have an impact on energy or signal transmission. The amplitude and phase of the incident wave voltage and current along the line will decay exponentially e ^-γz . where γ is the propagation constant:

$\mathrm{\γ}=\sqrt{(R_t+\mathrm{j\ω}{L}_t)(G_t+\mathrm{j\ω}{C}_t)}=\mathrm{\α}+\mathrm{j\β}$ (Formula 1)

It is used to describe the attenuation and phase change of the guided wave as it propagates along the guided system. Among them, the real part α is called the attenuation constant, which represents the change of the amplitude of the traveling wave per unit length; the imaginary part β is called the phase shift constant, which represents the change of the phase of the traveling wave per unit length.

For microwave transmission lines (R _t <<ωL _t , G _t <<ωC _t ):

$\mathrm{\&alpha;}=\frac{R_t}{2Z_c}+\frac{G_t{Z}_c}{2},$ $\mathrm{\&beta;}=\mathrm{\&omega;}\sqrt{L_t{C}_t}$ (Formula 2)

Z _c is the characteristic impedance of the transmission line:

$Z_c=\sqrt{\frac{\mathrm{j\&omega;}{L}_t(1+\frac{R_t}{\mathrm{j\&omega;}{L}_t})}{\mathrm{j\&omega;}{C}_t(1+\frac{G_t}{\mathrm{j\&omega;}{C}_t})}}\&ap;\sqrt{\frac{L_t}{C_t}}$ (Formula 3)

It can be seen that the attenuation constant of the transmission line depends on the resistance loss of the wire itself and the dielectric loss between the wires.

The loss of coplanar waveguide mainly comes from dielectric loss and conductor loss, and its attenuation constant α can be expressed as α=α _die +α _con , where α _die is the attenuation constant of the medium, and α _con is the attenuation constant of the conductor.

Dielectric loss is the heat loss caused by the alternating polarization of the medium molecules and the back and forth collision of the crystal lattice when the electric field passes through the medium. It is mainly reflected in the distributed capacitance. If the coplanar waveguide is entirely in a medium with a relative permittivity of ε _r , its distributed capacitance C _t will increase by ε _r times compared with that of air as a medium. But usually part of the signal transmitted on the coplanar waveguide is in the medium with a dielectric constant ε _r , and the other part is in the air. Equivalent to being in a mixed medium, it is necessary to introduce the equivalent dielectric constant ε _eff and the medium filling factor q to correct:

${\mathrm{\&epsiv;}}_{\mathrm{eff}}=\frac{{\mathrm{\&epsiv;}}_r+1}{2}$ (Formula 4)

$q=\frac{{\mathrm{\&epsiv;}}_{\mathrm{eff}}-1}{{\mathrm{\&epsiv;}}_r-1}$ (Formula 5)

Then the attenuation constant α _die of the coplanar waveguide medium is:

${\mathrm{\&alpha;}}_{\mathrm{die}}=\frac{27.3}{{\mathrm{\&lambda;}}_0}\left(\frac{q{\mathrm{\&epsiv;}}_r}{\sqrt{{\mathrm{\&epsiv;}}_{\mathrm{eff}}}}\right)\mathrm{tg\&delta;}=\frac{27.3}{{\mathrm{\&lambda;}}_0}\frac{{\mathrm{\&epsiv;}}_r}{\sqrt{{\mathrm{\&epsiv;}}_{\mathrm{eff}}}}\frac{{\mathrm{\&epsiv;}}_{\mathrm{eff}}-1}{{\mathrm{\&epsiv;}}_r-1}\mathrm{tg\&delta;}$ (Formula 6)

In the formula, λ ₀ is the free space wavelength, ε _r is the dielectric constant of the medium, tgδ is the loss tangent, and ε _eff is the equivalent dielectric constant.

Since the electromagnetic field is mainly distributed in the dielectric layer below the ground wire and the signal wire, the relative dielectric constant of the medium in this area is mainly considered when calculating the equivalent dielectric constant. Neglecting the silicon dioxide passivation layer, it can be known from Equation 4 that ε _eff ≈1 for the SOI-based coplanar waveguide of the present invention, and ε _eff ≈7 for the existing coplanar waveguide. It can be seen that the equivalent dielectric constant of the SOI-based coplanar waveguide of the present invention is much smaller than that of the existing coplanar waveguide, which can reduce the attenuation constant α _die of the coplanar waveguide medium, thereby enabling transmission Features are improved.

Claims (9)

1. A coplanar waveguide based on a silicon-on-insulator (SOI) substrate, said coplanar waveguide comprising an SOI substrate, a silicon dioxide layer formed on the SOI substrate, and a silicon dioxide layer formed on the silicon dioxide layer and Alternately arranged ground wires and signal wires are characterized in that: the space between adjacent ground wires and signal wires is provided with corrosion hole belts along the direction of the ground wires and signal wires, and strip-shaped concave holes are formed below the corrosion hole belts. groove. 2. The coplanar waveguide according to claim 1, characterized in that: the coplanar waveguide includes two ground wires and one signal wire, and two strip-shaped concaves are formed between the two ground wires and one signal wire. groove. 3. The coplanar waveguide according to claim 1, characterized in that there is a buried oxide layer under the surface silicon of the SOI substrate, and the depth of the groove is such that the buried oxide layer is exposed. 4. The coplanar waveguide according to claim 1, characterized in that: the angle between the groove wall of the groove and the silicon dioxide layer is 0°-90°. 5. A method for manufacturing a coplanar waveguide based on an SOI substrate, characterized in that the method comprises the following steps: An SOI substrate is provided, and a buried oxide layer is provided under the surface silicon of the SOI substrate; A layer of silicon dioxide is deposited on the SOI substrate, a metal layer is formed on the silicon dioxide layer, and part of the metal is removed by photolithography and etching to form a signal line and two ground lines, and the signal line Sandwiched between two ground wires; On the silicon dioxide layer of the spacer between the signal line and the ground line, two etching holes are formed by photolithography and etching, and the etching holes are evenly arranged on the spacer, exposing the silicon on the surface of the SOI substrate; Through the etching holes, the silicon on the surface layer of the SOI substrate under the spacer strips is etched away to form strip-shaped grooves. 6. The manufacturing method according to claim 5, wherein the SOI substrate is prepared by oxygen injection isolation technology, silicon wafer bonding or intelligent lift-off technology. 7. The manufacturing method according to claim 5, characterized in that the silicon dioxide layer is deposited by a plasma enhanced chemical vapor deposition process. 8. The manufacturing method according to claim 5, characterized in that: the silicon on the surface layer of the SOI substrate under the spacer zone is etched away through the etching hole by using an etching process. 9. The manufacturing method according to claim 5, characterized in that: the etching depth of the strip-shaped groove is such that the buried oxide layer is exposed.

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