CN101271825A - Chip identification production method and light shield - Google Patents
Chip identification production method and light shield Download PDFInfo
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- CN101271825A CN101271825A CNA200710038450XA CN200710038450A CN101271825A CN 101271825 A CN101271825 A CN 101271825A CN A200710038450X A CNA200710038450X A CN A200710038450XA CN 200710038450 A CN200710038450 A CN 200710038450A CN 101271825 A CN101271825 A CN 101271825A
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Abstract
The invention provides a fabrication method of a chip label, and a photomask, comprising the steps as follows: chip label images corresponding to the chips one by one are determined; the chip label images are transferred on a chip cutting protecting ring of a wafer, so as to form a chip label. By the steps, the position of the chip at the wafer is determined according to the label on the chip, thus determining the mass of the whole wafer.
Description
Technical field
The present invention relates to the Computer-Assisted Design, Manufacture And Test field of semiconductor device, relate in particular to the manufacture method and the light shield of semiconductor device chip sign.
Background technology
In semiconductor fabrication, finish semiconductor product and will pass through many technologies, for example photoetching process, etch process, ion implantation technology etc. usually; In these technologies, must be applied to board and many red tapes of huge quantity.Therefore, those skilled in the art are devoted to all to guarantee that the board running is normal, keep or improve product percent of pass, problem points and board maintenance etc. are confirmed in detecting, so that the speed of production of semiconductor product and quality can conform with customer demand.
Generally speaking, inquire into the problem of semiconductor technology and can set about analyzing, comprise quality test data on technological parameter data, the line, defects detection data, sample test data, wafer sort data and encapsulation back test data from following data information.Wherein, encapsulation back test data is after the wafer cutting and carrying out canned program, and prepared semiconductor device is carried out the detected value that product test obtains.
Yet integrated circuit is gone through nearly 40 years development, and the number of devices that one chip can hold presents volatile growth.Along with the semiconductor process techniques progress to very lagre scale integrated circuit (VLSIC), or even more advanced technology, the device count of being held on the one chip are increased to several ten million devices by in the past several thousand devices.Therefore, for the circuit and the huge device of quantity of dense distribution like this,, the inspection or the QC work of chip is become more important in order to ensure the running characteristic and the reliability of chip.
The detection method of existing chip comprises that the patent No. is 98115227 described detection critical voltage of Chinese patent or saturation current, in making the semiconductor device process, detect, therefore need not chip is cut down from wafer, so just can know the quality situation of understanding whole wafer.For example the test of electric performance test and yield then needs Chip Packaging just can detect after intact in addition, it is that 03102246 Chinese patent application is described that concrete technical scheme please refer to application number, earlier chip is cut down from wafer, and then chip encapsulated, having encapsulated the back tests pin of chip with probe, after yet such test is finished can only touch the quality situation of single chip, and owing to can't determine the single chip position on wafer originally, thereby can't determine the quality situation of wafer.
Prior art is when carrying out the detection of electric performance test or yield, must earlier chip after cutting down encapsulation, just can be tested wafer, yet after finishing, such test can only understand the quality situation of single chip, and owing to can't determine the single chip position on wafer originally, thereby can't determine the quality situation of wafer.
Summary of the invention
The problem that the present invention solves provides a kind of manufacture method and light shield of chip identification, prevents to test the position that can't be reduced to behind the chip on the original wafer, can't determine the situation of whole wafer.
For addressing the above problem, the invention provides a kind of manufacture method of chip identification, comprise the following steps: to determine and chip chip identification figure one to one; The chip identification figure transfer to the chip cutting guard ring of wafer, is formed chip identification.
The step of described formation chip identification comprises: at least one exposure area of definition on wafer; Form corresponding area identification on the chip cutting guard ring of the chip correspondence of each exposure area, described area identification is used to distinguish different exposure areas; On light shield, form the regional chip identification figure of distinguishing same exposure area chips; Regional chip identification figure transfer on the light shield to the chip cutting guard ring at the non-area identification place of exposure area, is formed and the regional one to one chip identification of chip, and constitute chip identification with area identification.
The corresponding area identification of described formation writes on the chip cutting guard ring by laser beam.
Described area identification comprises Arabic numerals, English alphabet or Arabic numerals and English alphabet combination.
The instrument of the regional chip identification figure of described formation is with laser beam or electron beam.
With regional chip identification figure transfer on the light shield to the instrument on the chip cutting guard ring is exposure bench.
Described exposure area area is 1/5～1/4 of a light shield area.
The regional chip identification figure quantity that comprises on the described light shield is consistent with the number of chips in the exposure area.
Described regional chip identification figure can be Arabic numerals, also can English alphabet or Arabic numerals and English alphabet combination.
The step of described formation chip identification comprises: write chip identification with laser beam on the chip cutting guard ring.
The step of described formation chip identification comprises: form the light shield corresponding with the exposure area, wherein comprise the chip identification figure of distinguishing the exposure area and distinguishing same exposure area chips on each light shield; Chip identification figure transfer on the light shield to the chip cutting guard ring of the corresponding exposure area of wafer, is formed the chip identification of distinguishing chip on the wafer.
Described chip cutting guard ring be positioned at chip around.
The present invention also provides a kind of light shield, comprises transparency carrier, is positioned at chromium rete, chip identification figure on the transparency carrier, runs through the chromium rete and exposes transparency carrier.
Compared with prior art, the present invention has the following advantages: the present invention determines and chip chip identification figure one to one that the chip identification figure can be on light shield; The chip identification figure transfer to the chip cutting guard ring of wafer, is formed chip identification.After can finishing chip testing like this, know that according to the sign on the chip this chip was positioned at the position of wafer originally, thereby determine the quality situation of whole wafer, and then can note improving in the position that defect problem occurs in follow-up chip manufacturing process.
Description of drawings
Fig. 1 is the embodiment flow chart that the present invention makes chip identification;
Fig. 2 to Fig. 6 is the embodiment schematic diagram that the present invention makes chip identification.
Embodiment
The present invention determines and chip chip identification figure one to one that the chip identification figure can be on light shield; The chip identification figure transfer to the chip cutting guard ring of wafer, is formed chip identification.After can finishing chip testing like this, know that according to the sign on the chip this chip was positioned at the position of wafer originally, thereby determine the quality situation of whole wafer, and then can note improving in the position that defect problem occurs in follow-up chip manufacturing process.For above-mentioned purpose of the present invention, feature and advantage can be become apparent more, the specific embodiment of the present invention is described in detail below in conjunction with accompanying drawing.
The invention provides a kind of manufacture method of chip identification, comprise the following steps: to determine and chip chip identification figure one to one; The chip identification figure transfer to the chip cutting guard ring of wafer, is formed chip identification.
The invention provides a kind of light shield, comprise transparency carrier, be positioned at chromium rete, chip identification figure on the transparency carrier, run through the chromium rete and expose transparency carrier.
Fig. 1 is the embodiment flow chart that the present invention makes chip identification.As shown in Figure 1, execution in step S201 defines at least one exposure area on wafer.
In the present embodiment, the area of each exposure area is identical, and the chip-count that is comprised is identical.
Execution in step S202 forms corresponding area identification on the chip cutting guard ring of the chip correspondence of each exposure area, described area identification is used to distinguish different exposure areas.
Area identification directly writes on the chip cutting guard ring by laser beam.
Described area identification can be Arabic numerals, also can English alphabet or Arabic numerals and English alphabet in conjunction with etc.
Be the chip cutting guard ring around the described chip, be used for follow-up chip being protected chip when wafer cuts down.
Described area identification is positioned on the chip cutting guard ring, can be not cut during follow-up cutting and can be distinguished during encapsulation.
Execution in step S203 forms the regional chip identification figure of distinguishing same exposure area chips on light shield.
In the present embodiment, at first in layout software, form and treat exposure area chip identification figure; To treat that by electron beam or laser beam writing station exposure area chip identification figure transfer to light shield, forms regional chip identification figure then.
Execution in step S204 to the chip cutting guard ring at the non-area identification place of exposure area, forms the regional chip identification figure transfer on the light shield and the regional one to one chip identification of chip, and constitutes chip identification with area identification.
Described regional chip identification is positioned on the chip cutting guard ring, can be not cut during follow-up cutting and can be distinguished during encapsulation; Chip in the corresponding same exposure area of the regional chip identification of wherein each, regional chip identification can be positioned on the chip cutting guard ring on any one side of chip.
Described regional chip identification can be Arabic numerals, also can English alphabet, Arabic numerals and English alphabet in conjunction with etc.
Except that present embodiment, the method that forms chip identification can also be: directly write on the chip cutting guard ring and chip chip identification one to one with laser beam.
Another embodiment that forms chip identification is: form the light shield corresponding with the exposure area, wherein comprise the chip identification figure of distinguishing the exposure area and distinguishing same exposure area chips on each light shield; Chip identification figure transfer on the light shield to the chip cutting guard ring of the corresponding exposure area of wafer, is formed the chip identification of distinguishing chip on the wafer.
Fig. 2 to Fig. 6 is the first embodiment schematic diagram that the present invention makes chip identification.As shown in Figure 2, at first on wafer 200, divide the identical exposure area 202 of some areas, be defined as the first exposure area E successively
1, the second exposure area E
2, the 3rd exposure area E
3N exposure area E
n
As shown in Figure 3, with laser beam successively at the first exposure area E
1Plurality of chips cutting guard ring 204 on the identical one to one first area of ablating with chip 206 identify A; With identical method at the second exposure area E
2The chip cutting guard ring of each chip 206 correspondences on ablate second area sign B identical; At the 3rd exposure area E
3Identical one to one the 3rd area identification C...... ablate on the interior chip cutting guard ring 204 at the 3rd exposure area E with chip 206
nThe identical one to one n-quadrant of ablation sign N on the interior chip cutting guard ring 204 with chip 206, first area sign, second area sign, the 3rd area identification ... the n-quadrant identifies in order to distinguish different exposure areas.
Described first area sign, second area sign, the 3rd area identification ... the n-quadrant sign can be Arabic numerals, also can English alphabet or Arabic numerals and English alphabet in conjunction with etc.
Around the described chip 206 be chip cutting guard ring 204, is used for follow-up chip 206 being protected chip 206 when wafer cuts down; First area sign, second area sign, the 3rd area identification ... the n-quadrant sign can be positioned on the chip cutting guard ring 204 on any one side around the chip 206, as long as corresponding one by one with chip.
First area sign, second area sign, the 3rd area identification ... the size of n-quadrant sign be so long as can not be cut during follow-up diced chip, and do not influence the subsequent device circuit.
The first exposure area E
1, the second exposure area E
2, the 3rd exposure area E
3... N exposure area E
nIn the chip 206 quantity unanimities that comprise.
Except that embodiment, on wafer, form first area sign, second area sign, the 3rd area identification ... the method for n-quadrant sign can also be to make the light shield identical with exposure area quantity, sign figure on each light shield is different, but the sign figure on the single light shield is identical, then the sign figure on each light shield is passed through the exposure imaging process transfer to the chip cutting road of corresponding exposure area.
As shown in Figure 4; in pattern layout software; design some different exposure area chip identification figures 300 for the treatment of; treat that wherein exposure area chip identification figure 300 is different Arabic numerals 1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16; describedly treat that the distance between the exposure area chip identification figure 300 can be equidistant; can be not equidistant yet, needing only can be one by one corresponding to each chip when being formed on the chip cutting guard ring at last.
In the present embodiment, treat that the quantity of exposure area chip identification figure 300 is corresponding with each exposure area chips quantity.
Described treat exposure area chip identification figure 300 can be Arabic numerals, also can English alphabet or Arabic numerals and English alphabet in conjunction with etc.
As shown in Figure 5, the exposure area chip identification figure 300 for the treatment of in Fig. 4 layout software is transferred on the light shield 302, forms regional chip identification figure 304 by electron beam writing station or laser beam writing station.
In the present embodiment, the size of exposure area determines that according to light shield 302 sizes the size of general exposure area is 1/5～1/4 of a light shield 302.
Wherein light shield 302 comprises transparency carrier, chromium rete and photoresist layer, treats that exposure area chip identification figure 300 is transferred on the photoresist layer; With the photoresist layer is mask, and the etching chromium rete is to exposing transparency carrier; And then ashing removal photoresist layer, form regional chip identification figure 304.
As shown in Figure 6, by exposure bench the regional chip identification figure 304 on Fig. 5 light shield 302 is transferred to successively the first exposure area E of wafer shown in Figure 2 200
1, the second exposure area E
2, the 3rd exposure area E
3... N exposure area E
nOn each chip cutting guard ring 204 at the non-area identification place of each interior chip 206 correspondences.
At first the Arabic numerals 1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16 in the regional chip identification figure 304 on the light shield 302 are transferred to the first exposure area E
1On each interior chip 206, form and the regional one to one chip identification 208 of each chip 206; Then the Arabic numerals 1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16 in the regional chip identification figure 304 on the light shield 302 are transferred to the second exposure area E
2On each interior chip 206, form and the regional one to one chip identification 208 of each chip 206; Arabic numerals 1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16 in the regional chip identification figure 304 on the light shield 302 are transferred to the 3rd exposure area E
3On each interior chip 206, form with the regional one to one chip identification 208...... of each chip 206 Arabic numerals 1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16 in the regional chip identification figure 304 on the light shield 302 are transferred to N exposure area E
nOn each interior chip 206, form and the regional one to one chip identification 208 of each chip 206.Described regional chip identification 208 constitutes chip identification with area identification, is used to distinguish each chip on the wafer.
Described regional chip identification 208 can be formed on any cutting guard ring 204 of chip 206; and can be formed at the optional position of cutting guard ring 204; for example centre position or marginal position; as long as be in the follow-up position that is not cut on the cutting guard ring 204, as long as and the first exposure area E
1The first area sign is not overlapping ... with N exposure area E
nThe n-quadrant sign is not overlapping.
When test, chip 204 is cut down from wafer 200, pass through packaging technology again with each chip 204 encapsulated mouldings.Each chip 204 is carried out electric performance test or yield test, assess the quality of each chip 204, and then determine the position of chip 204 on wafer 200 according to the chip identification on each chip 204, draw the overall condition of wafer 200, and can draw doing badly of which position on the wafer 200, need in follow-up manufacturing process, improve.
Though the present invention with preferred embodiment openly as above; but it is not to be used for limiting the present invention; any those skilled in the art without departing from the spirit and scope of the present invention; can make possible change and modification, so protection scope of the present invention should be as the criterion with the scope that claim of the present invention was defined.
Claims (13)
1. the manufacture method of a chip identification is characterized in that, comprises the following steps:
Determine and chip chip identification figure one to one;
The chip identification figure transfer to the chip cutting guard ring of wafer, is formed chip identification.
2. according to the manufacture method of the described chip identification of claim 1, it is characterized in that: the step of described formation chip identification comprises:
At least one exposure area of definition on wafer;
Form corresponding area identification on the chip cutting guard ring of the chip correspondence of each exposure area, described area identification is used to distinguish different exposure areas;
On light shield, form the regional chip identification figure of distinguishing same exposure area chips;
Regional chip identification figure transfer on the light shield to the chip cutting guard ring at the non-area identification place of exposure area, is formed and the regional one to one chip identification of chip, and constitute chip identification with area identification.
3. according to the manufacture method of the described chip identification of claim 2, it is characterized in that: the corresponding area identification of described formation writes on the chip cutting guard ring by laser beam.
4. according to the manufacture method of the described chip identification of claim 3, it is characterized in that: described area identification comprises Arabic numerals, English alphabet or Arabic numerals and English alphabet combination.
5. according to the manufacture method of the described chip identification of claim 2, it is characterized in that: the instrument of the regional chip identification figure of described formation is with laser beam or electron beam.
6. according to the manufacture method of the described chip identification of claim 5, it is characterized in that: with regional chip identification figure transfer on the light shield to the instrument on the chip cutting guard ring is exposure bench.
7. according to the manufacture method of the described chip identification of claim 6, it is characterized in that: described exposure area area is 1/5～1/4 of a light shield area.
8. according to the manufacture method of the described chip identification of claim 7, it is characterized in that: the regional chip identification figure quantity that comprises on the described light shield is consistent with the number of chips in the exposure area.
9. the manufacture method of described chip identification according to Claim 8 is characterized in that: described regional chip identification figure can be Arabic numerals, also can English alphabet or Arabic numerals and English alphabet combination.
10. according to the manufacture method of the described chip identification of claim 1, it is characterized in that: the step of described formation chip identification comprises: write chip identification with laser beam on the chip cutting guard ring.
11. manufacture method according to the described chip identification of claim 1, it is characterized in that: the step of described formation chip identification comprises: form the light shield corresponding with the exposure area, wherein comprise the chip identification figure of distinguishing the exposure area and distinguishing same exposure area chips on each light shield;
Chip identification figure transfer on the light shield to the chip cutting guard ring of the corresponding exposure area of wafer, is formed the chip identification of distinguishing chip on the wafer.
12. the manufacture method according to each described chip identification of claim 1 to 11 is characterized in that: described chip cutting guard ring be positioned at chip around.
13. a light shield comprises transparency carrier, is positioned at the chromium rete on the transparency carrier, it is characterized in that, also comprises:
The chip identification figure runs through the chromium rete and exposes transparency carrier.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN200710038450A CN100576434C (en) | 2007-03-22 | 2007-03-22 | The manufacture method of chip identification and light shield |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN200710038450A CN100576434C (en) | 2007-03-22 | 2007-03-22 | The manufacture method of chip identification and light shield |
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| Publication Number | Publication Date |
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| CN101271825A true CN101271825A (en) | 2008-09-24 |
| CN100576434C CN100576434C (en) | 2009-12-30 |
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| CN200710038450A Expired - Fee Related CN100576434C (en) | 2007-03-22 | 2007-03-22 | The manufacture method of chip identification and light shield |
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Cited By (10)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN102800656A (en) * | 2011-05-20 | 2012-11-28 | 精材科技股份有限公司 | Chip package, method for forming the same, and package wafer |
| CN103324037A (en) * | 2013-07-04 | 2013-09-25 | 北京京东方光电科技有限公司 | Exposure device and method |
| CN105430585A (en) * | 2015-11-30 | 2016-03-23 | 歌尔声学股份有限公司 | Traceable chip, manufacturing method thereof and electronic device |
| US10079206B2 (en) | 2016-10-27 | 2018-09-18 | Mapper Lithography Ip B.V. | Fabricating unique chips using a charged particle multi-beamlet lithography system |
| CN109003898A (en) * | 2017-06-07 | 2018-12-14 | 郑州光力瑞弘电子科技有限公司 | One kind realizing the new process of pattern transfer on thin slice (including wafer) |
| CN109669321A (en) * | 2017-10-16 | 2019-04-23 | 中芯国际集成电路制造(上海)有限公司 | A kind of wafer side washing system and wafer side washing method |
| US10522472B2 (en) | 2016-09-08 | 2019-12-31 | Asml Netherlands B.V. | Secure chips with serial numbers |
| CN112630618A (en) * | 2020-11-20 | 2021-04-09 | 深圳市国微电子有限公司 | Chip testing method and device |
| WO2022021102A1 (en) * | 2020-07-28 | 2022-02-03 | 华为技术有限公司 | Die, wafer, and method for identifying location of die on wafer |
| CN114185244A (en) * | 2022-02-15 | 2022-03-15 | 绍兴中芯集成电路制造股份有限公司 | Photomask set and wafer marking method |
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- 2007-03-22 CN CN200710038450A patent/CN100576434C/en not_active Expired - Fee Related
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| CN102800656A (en) * | 2011-05-20 | 2012-11-28 | 精材科技股份有限公司 | Chip package, method for forming the same, and package wafer |
| CN102800656B (en) * | 2011-05-20 | 2015-11-25 | 精材科技股份有限公司 | The formation method of wafer encapsulation body, wafer encapsulation body and encapsulation wafer |
| CN103324037A (en) * | 2013-07-04 | 2013-09-25 | 北京京东方光电科技有限公司 | Exposure device and method |
| CN103324037B (en) * | 2013-07-04 | 2015-01-07 | 北京京东方光电科技有限公司 | Exposure device and method |
| WO2015000263A1 (en) * | 2013-07-04 | 2015-01-08 | 京东方科技集团股份有限公司 | Exposure device and exposure method thereof |
| US9523920B2 (en) | 2013-07-04 | 2016-12-20 | Boe Technology Group Co., Ltd. | Exposure device and exposure method |
| CN105430585A (en) * | 2015-11-30 | 2016-03-23 | 歌尔声学股份有限公司 | Traceable chip, manufacturing method thereof and electronic device |
| US11004800B2 (en) | 2016-09-08 | 2021-05-11 | Asml Netherlands B.V. | Secure chips with serial numbers |
| US10522472B2 (en) | 2016-09-08 | 2019-12-31 | Asml Netherlands B.V. | Secure chips with serial numbers |
| US11688694B2 (en) | 2016-09-08 | 2023-06-27 | Asml Netherlands B.V. | Secure chips with serial numbers |
| US10714427B2 (en) | 2016-09-08 | 2020-07-14 | Asml Netherlands B.V. | Secure chips with serial numbers |
| US11152302B2 (en) | 2016-10-27 | 2021-10-19 | Asml Netherlands B.V. | Fabricating unique chips using a charged particle multi-beamlet lithography system |
| US10600733B2 (en) | 2016-10-27 | 2020-03-24 | Asml Netherlands B.V. | Fabricating unique chips using a charged particle multi-beamlet lithography system |
| US10418324B2 (en) | 2016-10-27 | 2019-09-17 | Asml Netherlands B.V. | Fabricating unique chips using a charged particle multi-beamlet lithography system |
| US10079206B2 (en) | 2016-10-27 | 2018-09-18 | Mapper Lithography Ip B.V. | Fabricating unique chips using a charged particle multi-beamlet lithography system |
| CN109003898A (en) * | 2017-06-07 | 2018-12-14 | 郑州光力瑞弘电子科技有限公司 | One kind realizing the new process of pattern transfer on thin slice (including wafer) |
| CN109669321B (en) * | 2017-10-16 | 2021-09-14 | 中芯国际集成电路制造(上海)有限公司 | Wafer edge washing system and wafer edge washing method |
| CN109669321A (en) * | 2017-10-16 | 2019-04-23 | 中芯国际集成电路制造(上海)有限公司 | A kind of wafer side washing system and wafer side washing method |
| WO2022021102A1 (en) * | 2020-07-28 | 2022-02-03 | 华为技术有限公司 | Die, wafer, and method for identifying location of die on wafer |
| CN112630618A (en) * | 2020-11-20 | 2021-04-09 | 深圳市国微电子有限公司 | Chip testing method and device |
| CN114185244A (en) * | 2022-02-15 | 2022-03-15 | 绍兴中芯集成电路制造股份有限公司 | Photomask set and wafer marking method |
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|---|---|
| CN100576434C (en) | 2009-12-30 |
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