CN101261405B - LCD panel - Google Patents
LCD panel Download PDFInfo
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- CN101261405B CN101261405B CN2007100730659A CN200710073065A CN101261405B CN 101261405 B CN101261405 B CN 101261405B CN 2007100730659 A CN2007100730659 A CN 2007100730659A CN 200710073065 A CN200710073065 A CN 200710073065A CN 101261405 B CN101261405 B CN 101261405B
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- liquid crystal
- crystal panel
- sept
- pixel region
- crystal layer
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Abstract
The invention relates to a liquid-crystal panel which comprises a lower substrate, an upper substrate, a liquid-crystal layer and a plurality of pixel regions. The lower substrate has a plurality of data lines and a plurality of scan lines; the upper substrate is arranged corresponding to the lower substrate; the liquid-crystal layer is arranged between the upper substrate and the lower substrate. Two adjacent scan line and data line define a minimum region as a pixel region and each pixel region comprises at least a first spacer and a second spacer. The first spacer is arranged at the place of the data line of the pixel region which is correspondingly defined and has a predetermined distance from the lower substrate so as to serve the circulation of the liquid-crystal layer; two ends of the second spacer are respectively connected with alignment films which are arranged at two sides of the liquid-crystal layer so as to supply a gap for pouring the liquid-crystal layer between the upper substrate and the lower substrate. The color and the brightness of the image displayed by the liquid-crystal panel do not have distortion.
Description
Technical field
The present invention relates to a kind of liquid crystal panel, particularly a kind of liquid crystal panel that comprises sept.
Background technology
Seeing also Fig. 1, is a kind of structural representation of prior art liquid crystal panel.This liquid crystal panel comprises an infrabasal plate 2, many data lines 4, multi-strip scanning line 6, a pixel electrode 8, a control element 10 and septs 12.These many data lines 4 are arranged on this infrabasal plate 2 with this multi-strip scanning line 6, and it intersects the formation matrix circuit, and this sweep trace 6 is defined as a pixel region (not label) with the Minimum Area that this data line 4 is defined.This pixel region comprises that a pixel electrode 8, is positioned at the control element 10 and a sept 12 of this sweep trace 6 and data line 4 intersections.This sept 12 is arranged on the position that upper substrate (figure does not show) is gone up relative control element 10, and connects with control element 10, and a predefined spacing between upper substrate and the infrabasal plate 2 is provided.Once alignment film (figure does not show) is arranged on this data line 4, the sweep trace 6.
Seeing also Fig. 2, is the sectional view of liquid crystal panel shown in Figure 1 along the II-II direction.This liquid crystal panel comprises that liquid crystal layer 42 and that assembly 40, on the assembly 38, is clamped in 38 of assemblies 40 and following assembly on this is used to provide the sept 12 that assembly 40 and this time assembly 38 on this have a predetermined gap.Should go up assembly 40 and comprise alignment film 36 on the upper substrate 32 that is cascading, the common electrode layer 34 and from top to bottom.This time assembly 38 comprises that an infrabasal plate 2, a gate electrode 16, one first insulation course 18, a protective seam 19, semi-conductor layer 20, a through hole 21, one source pole electrode 22, a drain electrode 24, one second insulation course 26, a pixel electrode 28 reach alignment film 30.This gate electrode 16 is arranged on this infrabasal plate 2, and the sweep trace in the connection layout 16.This first insulation course 18 covers this gate electrode 16 and infrabasal plate 2.This semiconductor layer 20 is arranged on first insulation course 18 of these gate electrode 16 corresponding positions.This source electrode 22 is oppositely arranged with this drain electrode 24, and part covers this semiconductor layer 20 and this first insulation course 18, the wherein data line 4 in these source electrode 22 connection layout 1.This protective seam 19 is arranged on this first insulation course 18, and overlapping with the part of this drain electrode 24.This second insulation course 26 is arranged on this drain electrode 24 and this source electrode 22, and covers this source electrode 22, this drain electrode 24 and this first insulation course 18.This protective seam 19 and 26 of this second insulation courses have a through hole 21, thereby expose this drain electrode 24.This pixel electrode 28 is arranged on this protective seam 19, and is connected with this drain electrode 24 by this through hole 21.This time alignment film 30 covers on this pixel electrode 28 and this second insulation course 26, and covers this pixel electrode 28 and this second insulation course 26.One end of this sept 12 connected with going up alignment film 36, and the following alignment film 30 of the other end and this gate electrode 16 corresponding positions connects.
In the prior art, can form stray capacitance between this time assembly 38 and common electrode layer 34 that should go up assembly 40 and the matrix circuit that constitutes by a plurality of pixel regions, dielectric material wherein is the liquid crystal molecule of liquid crystal layer, when being subjected to electric field influence, this liquid crystal molecule can tilt to reverse, cause dielectric coefficient to change, the capacity effect that stray capacitance is produced can change because of GTG, causes when carrying out data transmission, have the phenomenon of distortion, and be difficult to control or repairing.In addition, liquid crystal panel is when forming liquid crystal layer, to accurately control the amount of liquid crystal that splashes into, and there is no headspace feed flow crystalline substance, display of the prior art splashes into when too much as buffering, as in manufacturing process, splashing into too much liquid crystal, then can cause upper substrate 32 and this infrabasal plate 2 when pressing, to cause structural failure or can't seal fully, cause the technology yield to descend because of internal pressure is excessive.
Summary of the invention
Problem for the easy distortion of data transmission that solves the prior art liquid crystal panel is necessary to provide a kind of liquid crystal panel that improves distortion phenomenon.
A kind of liquid crystal panel, it comprises an infrabasal plate, a upper substrate, a liquid crystal layer and a plurality of pixel region.This infrabasal plate has many data lines and multi-strip scanning line, and this upper substrate is provided with respect to this infrabasal plate, and this liquid crystal layer is arranged between this upper substrate and this infrabasal plate.Adjacent two sweep traces and data line define Minimum Area and define a pixel region.Each pixel region comprises one second sept and at least one first sept, and this first sept correspondence defines on the linear position data of this pixel region and is provided with, and and this infrabasal plate between a predefined spacing is arranged, for this liquid crystal layer circulation.The two ends of this second sept connect with the alignment film that is arranged on the liquid crystal layer both sides respectively, for the gap of injecting liquid crystal layer is provided between this upper substrate and infrabasal plate, the specific inductive capacity of this first sept and this second sept is less than the specific inductive capacity of liquid crystal molecule in this liquid crystal layer and be a fixed value.
Compared with prior art, because this liquid crystal panel is provided with the hybrid combination that is made of this first sept and this second sept, and the specific inductive capacity of this hybrid combination is less than liquid crystal molecule and do not change because of GTG, make that the stray capacitance that forms on this data line is less and immobilize, thereby the distortion phenomenon when reducing the transmission data, make pixel electrode reach predetermined charge and discharge effect, make the color of this liquid crystal panel display frame and brightness undistorted.In addition, have one to interspace in advance between this first sept and infrabasal plate, when splashing into too much liquid crystal, can play buffer action, make unnecessary liquid crystal can not have influence on the complete of the sealing of liquid crystal panel and structure, improve the technology yield.
Description of drawings
Fig. 1 is a kind of prior art liquid crystal panel structure synoptic diagram.
Fig. 2 is the sectional view of liquid crystal panel shown in Figure 1 along the II-II direction
Fig. 3 is the structural representation of liquid crystal panel first embodiment of the present invention.
Fig. 4 is the structural representation of liquid crystal panel one pixel region shown in Figure 3.
Fig. 5 is the sectional view of V-V direction of the pixel region of liquid crystal panel shown in Figure 3.
Fig. 6 is the sectional view of VI-VI direction of the pixel region of liquid crystal panel shown in Figure 3.
Fig. 7 is the structural representation of a pixel region of liquid crystal panel second embodiment of the present invention.
Embodiment
See also Fig. 3 and Fig. 4, Fig. 3 is the structural representation of liquid crystal panel first embodiment of the present invention, and Fig. 4 is the structural representation of liquid crystal panel one pixel region shown in Figure 3.This liquid crystal panel comprises assembly on one 82, one and should go up liquid crystal layer 62 that following assembly 80, that assembly 82 is oppositely arranged is clamped in 80 of assemblies 82 and this time assembly this on, a plurality of first sept 54 and second sept 56 that is arranged on 80 of assemblies 82 and following assembly on this, and the specific inductive capacity of the permittivity ratio liquid crystal molecule of this first sept 54 and this second sept 56 is little and immobilize.
This time assembly 80 contiguous these liquid crystal layer 62 1 sides are provided with the matrix form circuit structure that is made of many data lines 46, multi-strip scanning line 48, a pixel electrode 50 and a plurality of control element 52.This data line 46 intersects formation one matrix circuit with this sweep trace 48, and the Minimum Area that the two defines is defined as a pixel region.Each pixel region includes a pixel electrode 50 and a control element 52.This control element 52 is arranged on this sweep trace 48 and these data line 46 intersections.This pixel electrode 50 utilizes a through hole (not label) to realize being electrically connected with this control element 52.This second sept 56 is arranged on this sweep trace 48 corresponding positions, and its two ends connect with upward assembly 82 is low mutually with this time assembly 80 respectively.This first sept 54 is arranged on this assembly 82 with respect to the position of this data line 46, and and 80 of following assemblies have a constant spacing.
Seeing also Fig. 5, is the sectional view of liquid crystal panel shown in Figure 4 along the V-V direction.This liquid crystal panel comprises assembly 80 on this, this time assembly 82 and one second sept 56 on the V-V direction.Should go up assembly 82 and comprise alignment film 78 on the upper substrate 74 that is cascading, the common electrode layer 76 and from top to bottom.This time assembly 80 comprises an infrabasal plate 44, one first insulation course 66, a data line 46, one second insulation course 70 and following alignment film 72.This first insulation course 66 covers this infrabasal plate 44, and this data line 46 is arranged on this first insulation course 66.This second insulation course 70 covers this data line 46 and this first insulation course 66.This time alignment film 72 covers this second insulation course 70.This first sept 54 is d1 highly, be arranged on this on alignment film 78, and and 72 of this time alignment films a fixed interval (FI) d2 is arranged.
Seeing also Fig. 6, is the sectional view of liquid crystal panel shown in Figure 4 along the VI-VI direction.This liquid crystal panel comprises assembly 82 on this, once assembly 80 and one second sept 56 on the VI-VI direction.Should go up assembly 82 also comprises this upper substrate 74, this common electrode layer 76 that is cascading from top to bottom and should go up alignment film 78.This time assembly 80 comprises this infrabasal plate 44, this sweep trace 48, this first insulation course 66, a liner 58, this second insulation course 70 and this time alignment film 72.This sweep trace 48 is arranged on this infrabasal plate 44.This first insulation course 66 covers this sweep trace 48 and this infrabasal plate 44.This liner 58 is arranged on this first insulation course 66 of these sweep trace 48 corresponding positions, and its material is identical with this data line 46.This second insulation course 70 covers this liner 58 and this first insulation course 66.This time alignment film 72 is arranged on this second insulation course 70.56 pairs of this second septs should be provided with at place, liner 58 positions, it highly also is d1, then an end of this second sept 56 connects with the last alignment film 78 that should go up assembly 82 surfaces, the other end and this time alignment film 72 connect, thereby provide a constant spacing for assembly on this 82 and this time assembly 80.In addition, this second sept 56 also can be arranged on the place of overlapping mutually of this sweep trace 48 and this data line 46, maybe can be arranged on respect to the position (as shown in Figure 1) of this control element 52 or above-mentioned three positions and select one or mix and be provided with.
Seeing also Fig. 7, is the structural representation of a pixel region of liquid crystal panel second embodiment of the present invention.Liquid crystal panel structure shown in this liquid crystal panel and first embodiment is basic identical, and its difference is: each pixel region of this liquid crystal panel includes a plurality of first septs 54 and one second sept 56.This first sept 54 is arranged on assembly (figure does not show) and goes up the position with respect to this data line 46, and do not connect with this time assembly, its shape can be strip (as shown in Figure 3) or rectangular-shaped (as shown in Figure 6) or both and mixes setting, and two 54 adjacent of first septs have a fixed gap simultaneously.The two ends of this second gap 56 respectively with this on assembly and following assembly connect, it can be arranged on this on assembly the position with respect to this sweep trace 48, or be arranged on this data line 46 and these sweep trace 48 intersections, or be arranged on respect to the position (as shown in Figure 1) of this control element 52 or above-mentioned three positions and select one or mix and be provided with.
First sept of liquid crystal panel of the present invention and the specific inductive capacity of second sept are less than the specific inductive capacity of liquid crystal molecule and be a fixed value, so this data line 46 is less and stable with the stray capacitance on this sweep trace 48, distortion in the time of can reducing the transmission data, make pixel electrode reach specific charge and discharge effect, so the picture color of liquid crystal panel and brightness are undistorted.In addition, the sept of this hybrid combination and following inter-module have a fixed air gap, play buffer action when splashing into too much liquid crystal, make unnecessary liquid crystal can not have influence on the complete of the sealing of liquid crystal panel and structure, raising technology yield.
Claims (10)
1. liquid crystal panel, it comprises an infrabasal plate, one upper substrate and a liquid crystal layer, this infrabasal plate has many data lines and multi-strip scanning line, this upper substrate is provided with respect to this infrabasal plate, this liquid crystal layer is arranged between this upper substrate and this infrabasal plate, adjacent two sweep traces and data line define Minimum Area and define a pixel region, it is characterized in that: each pixel region of this liquid crystal panel comprises one second sept and at least one first sept, this first sept correspondence defines on the linear position data of this pixel region and is provided with, and and a predefined spacing arranged between this infrabasal plate, for this liquid crystal layer circulation, the two ends of this second sept connect with the alignment film that is arranged on the liquid crystal layer both sides respectively, for the gap of injecting liquid crystal layer is provided between this upper substrate and infrabasal plate, the specific inductive capacity of this first sept and this second sept is less than the specific inductive capacity of liquid crystal molecule in this liquid crystal layer and be a fixed value.
2. liquid crystal panel as claimed in claim 1 is characterized in that: the pixel region of this liquid crystal panel further comprises a liner, and this second sept is to being provided with at place, liner position.
3. liquid crystal panel as claimed in claim 2 is characterized in that: this liner is identical with this data line material.
4. liquid crystal panel as claimed in claim 1 is characterized in that: this second sept defines in correspondence on the sweep trace of this pixel region and is provided with.
5. liquid crystal panel as claimed in claim 1 is characterized in that: this second sept to should sweep trace and the data line place of overlapping mutually be provided with.
6. liquid crystal panel as claimed in claim 1 is characterized in that: each pixel region of this liquid crystal panel further comprises a control element, and this control element is arranged on this sweep trace and data line intersection.
7. liquid crystal panel as claimed in claim 6 is characterized in that: this second sept is to being provided with at place, control element position.
8. liquid crystal panel as claimed in claim 1 is characterized in that: this each pixel region has one first sept.
9. liquid crystal panel as claimed in claim 1 is characterized in that: this each pixel region has a plurality of first septs, and has certain clearance between adjacent two first septs.
10. liquid crystal panel as claimed in claim 1 is characterized in that: this first sept is a strip or rectangular-shaped.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN2007100730659A CN101261405B (en) | 2007-03-09 | 2007-03-09 | LCD panel |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN2007100730659A CN101261405B (en) | 2007-03-09 | 2007-03-09 | LCD panel |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN101261405A CN101261405A (en) | 2008-09-10 |
| CN101261405B true CN101261405B (en) | 2011-05-18 |
Family
ID=39961955
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN2007100730659A Expired - Fee Related CN101261405B (en) | 2007-03-09 | 2007-03-09 | LCD panel |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN101261405B (en) |
Families Citing this family (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102854649A (en) * | 2011-06-30 | 2013-01-02 | 上海天马微电子有限公司 | Liquid crystal display panel, liquid crystal display and manufacturing method of liquid crystal display panel |
| CN104460142B (en) * | 2014-12-15 | 2017-05-24 | 深圳市华星光电技术有限公司 | Liquid crystal display panel |
| CN106094360A (en) * | 2016-08-22 | 2016-11-09 | 深圳市华星光电技术有限公司 | Curved surface display panels |
| JP2019191404A (en) * | 2018-04-26 | 2019-10-31 | シャープ株式会社 | Display panel |
| CN109240008A (en) * | 2018-10-29 | 2019-01-18 | 惠科股份有限公司 | Display device |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1530721A (en) * | 2003-03-17 | 2004-09-22 | ���ǵ�����ʽ���� | Panel for displaying device, manufacturing method thereof and liquid-crystal displaying device therewith |
| CN1661425A (en) * | 2004-02-25 | 2005-08-31 | Lg.菲利浦Lcd株式会社 | Liquid crystal display device and method of fabricating the same |
-
2007
- 2007-03-09 CN CN2007100730659A patent/CN101261405B/en not_active Expired - Fee Related
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1530721A (en) * | 2003-03-17 | 2004-09-22 | ���ǵ�����ʽ���� | Panel for displaying device, manufacturing method thereof and liquid-crystal displaying device therewith |
| CN1661425A (en) * | 2004-02-25 | 2005-08-31 | Lg.菲利浦Lcd株式会社 | Liquid crystal display device and method of fabricating the same |
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| Publication number | Publication date |
|---|---|
| CN101261405A (en) | 2008-09-10 |
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Granted publication date: 20110518 Termination date: 20180309 |
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| CF01 | Termination of patent right due to non-payment of annual fee |