CN101251794A - Recording internal memory data reading system and method - Google Patents
Recording internal memory data reading system and method Download PDFInfo
- Publication number
- CN101251794A CN101251794A CNA2008100827451A CN200810082745A CN101251794A CN 101251794 A CN101251794 A CN 101251794A CN A2008100827451 A CNA2008100827451 A CN A2008100827451A CN 200810082745 A CN200810082745 A CN 200810082745A CN 101251794 A CN101251794 A CN 101251794A
- Authority
- CN
- China
- Prior art keywords
- data
- address
- microprocessor
- memory control
- read
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000000034 method Methods 0.000 title claims abstract description 17
- 238000006243 chemical reaction Methods 0.000 claims description 4
- 230000008676 import Effects 0.000 claims 1
- 230000000694 effects Effects 0.000 abstract description 3
- 238000012545 processing Methods 0.000 description 11
- 238000010586 diagram Methods 0.000 description 9
- 230000009183 running Effects 0.000 description 6
- 230000005540 biological transmission Effects 0.000 description 4
- 230000006870 function Effects 0.000 description 4
- 230000001360 synchronised effect Effects 0.000 description 3
- 238000011161 development Methods 0.000 description 2
- 241001269238 Data Species 0.000 description 1
- 238000004590 computer program Methods 0.000 description 1
- 238000013461 design Methods 0.000 description 1
Images
Abstract
The invention discloses a memory control system and a memory data reading method. The memory control system comprises a microprocessor, a serial storing device, a first buffer, a second buffer, a memory control unit and a multi-task device. The memory control system and the memory data reading method of the invention uses the characteristic that most time microprocessors read the continuous address data in a serial memory, to achieve the effect of accelerating memory reading speed by prereading and temporarily storing the data which is required to be read by the microprocessor.
Description
Technical field
What the present invention relates to is a kind of internal memory treating apparatus, particularly be a kind of memory control system and internal storage data read method.
Background technology
General micro controller (Micro-processor, MCU) do not have built-in ROM (read-only memory) (Read-OnlyMemory, ROM), and in the past all by and the mode of column bus (Parallel BUS) come external ROM (read-only memory) (for example flash memory (Flash memory)) access program code (ROM Code).And because present design is that microprocessor and scale controller (Scaler) are incorporated in the same chip (Chip), therefore the stitch (Pin) in order to save microprocessor then changes into and adopts the mode of universal serial bus (Serial BUS) to come ROM (read-only memory) access program code.Under the framework of universal serial bus, when microprocessor reads the program code of ROM (read-only memory), only can in the frequency period (Clock) of a fundamental frequency (Base band), read the data of (Bit), so the processing speed of microprocessor can significantly reduce.
For example, as shown in Figure 1, described figure is the oscillogram that showed when one or two cycle, (2T) microprocessor was with the serial mode transmission operation.In the drawings, label MCUclk is the frequency period of microprocessor running; Label xclk is the frequency period of system's fundamental frequency.General 2T microprocessor is when the period 1 of MCUclk T0, to ROM (read-only memory), capture the big or small data (data) of (Fetch) byte (byte), but when capturing eight described data at every turn, all need prior spended time decoding eight (bit) order code (command), with 24 address code (address); And when MCUclk T1 second round, the 2T microprocessor is carried out described data (program code).By described figure as can be known, the 2T microprocessor in acquisition when the executive routine code, but need just execution of 40 fundamental frequency cycle xclk respectively, also be that the 2T microprocessor needs 80 fundamental frequency cycle xclk just can run through the data of a byte altogether.An instruction of general microprocessor needs the data of one to four byte, is example with the instruction of two byte datas: the 2T microprocessor when carrying out this instruction, need altogether four MCUclk-promptly 160 frequency period xclk just can finish running.Therefore, under the framework of serial transmission, various microprocessors (2T, 6T, 8T MCU ...) time of carrying out an instruction will elongate in large quantities, and the speed of total system executive routine is restricted.
Summary of the invention
At the problems referred to above, one of purpose of the present invention can improve a kind of memory control system and a kind of internal storage data read method that microprocessor reads the speed of serial internal memory providing.
One embodiment of the invention provide a kind of memory control system.Described internal memory control is to include a microprocessor, a serial storage device, one first impact damper, one second impact damper, a memory control unit and a multiplexer.Described microprocessor is in order to exporting a plurality of addresses, and described these addresses comprise one first address and one second address or a three-address at least.Serial storage device is in order to store the data of corresponding described these addresses.And first impact damper is in order to temporary one first data or one the 3rd data.Second impact damper is then in order to temporary one second data.Memory control unit receives first address, reads first data of corresponding first address according to first address to storage device; And receive second address, read second data of corresponding second address according to second address to storage device; Or receive three-address, read the 3rd data of corresponding three-address according to three-address to storage device.Wherein, when described first, second impact damper all has data, memory control unit will produce one and select signal.And multiplexer receives first data and second data or the 3rd data, and according to selecting signal deciding how to export first data, second data or the 3rd data to microprocessor.Palpus attention person, when the initial state of described microprocessor has just begun to read the data of storage device, memory control unit will provide at least one pseudo-order to postpone microprocessor between one third phase, till described first impact damper has described first data and described second impact damper and has described second data; And when an address and second address be when arranging continuously, multiplexer is according to selecting signal to export first data and export second data in a second phase between a first phase; And when first address and second address are discontinuous arrangement, described memory control unit will provide at least one pseudo-order to postpone microprocessor between one third phase, till first impact damper has the 3rd data and second impact damper and has second data.
Moreover one embodiment of the invention provide a kind of internal storage data read method.Described method comprises the following step: at first, receive one first address and one second address and a three-address.Then, judge whether first address and second address arrange continuously, when arrange continuously first address and second address, read and first data and second data of temporary corresponding first address and second address to internal memory, and export first data and second data in regular turn to microprocessor; And when first address and the discontinuous arrangement in second address, provide a pseudo-order to postpone microprocessor one Preset Time, and in described Preset Time, read and second data and the 3rd data of temporary corresponding second address and three-address to internal memory, and export second data and the 3rd data in regular turn to microprocessor.
Memory control system of the present invention and internal storage data read method are that to utilize the most of the time microprocessor be the characteristic that reads the continuation address data of serial internal memory, by the data that read in advance and temporary microprocessor requirement is read, reach the effect of rapid memory reading efficiency.
Description of drawings
Fig. 1 shows a kind of oscillogram that had now when two cycles, (2T) microprocessor was with the serial mode transmission operation;
Fig. 2 shows the synoptic diagram of a kind of memory control system of one embodiment of the invention;
Fig. 3 shows the waveform of the frequency period of the frequency period of microprocessor of one embodiment of the invention and system's fundamental frequency, and memory control system respectively installs the synoptic diagram of operating state under the consecutive access pattern;
The synoptic diagram of one embodiment of the special read mode of Fig. 4 A and Fig. 4 B demonstration memory control system of the present invention;
Fig. 5 A, Fig. 5 B, with Fig. 5 C be the synoptic diagram of another embodiment that shows the special read mode of memory control system of the present invention;
Fig. 6 A, Fig. 6 B, with Fig. 6 C be the synoptic diagram of another embodiment that shows the special read mode of memory control system of the present invention;
Fig. 7 shows the process flow diagram of the internal storage data read method of one embodiment of the invention.
Description of reference numerals: 20-memory control system; The 21-microprocessor; The 22-serial storage device; 23-internal memory control device; The MUX-multiplexer; Buf1, Buf2-impact damper; The 231-memory control unit; P/S, S/P-converting unit.
Embodiment
Below with reference to graphic detailed description memory control system of the present invention and internal storage data read method.
Fig. 2 is the synoptic diagram that shows a kind of memory control system 20 of one embodiment of the invention.Described memory control system 20 includes a microprocessor 21, a serial (serial) storage device 22, an internal memory control device 23 and a multiplexer MUX.
Described microprocessor 21 can be two present cycle 2T, phase 4T, six cycle 6T all around ..., or various microprocessor control unit (the Microprocessor control unit of future development, MCU) or various microprocessor (Microprocessor unit, MPU).Microprocessor 21 is in order to the demand according to its computing, produce one comprise an address information at least read signal Rs.Certainly, the described signal Rs that reads also can comprise out of Memory, as instruction (command) etc.
Internal memory control device (memory master) the 23rd, the fundamental frequency xclk of employing system operates.Described internal memory control device 23 is in order to a plurality of addresses that signal Rs provides of reading according to the different time of microprocessor 21, reads the data of corresponding described these addresses to the storage device 22.And including one first impact damper Buf1, one second impact damper Buf2, a memory control unit 231, one (parallel) arranged side by side, internal memory control device 23 is serial to converting unit S/P arranged side by side to serial (serial) converting unit P/S and.The described first impact damper Buf1 all is in order to keep in the data (program code) of corresponding above-mentioned address with the second impact damper Buf2.Side by side to serial conversion unit P/S be in order to will from microprocessor 21 side by side the conversion of signals of input be the signal of serial output.And being serial to converting unit S/P arranged side by side is in order to being converted to output data arranged side by side by the data of serial input in the storage device 22, to deliver to impact damper Buf1 or Buf2.Must notice that all during the computer program stored code, memory control unit 231 will produce a selection signal S1 in impact damper Buf1 and impact damper Buf2.
Moreover multiplexer MUX is in order to receiving the data among two impact damper Buf1 or the Buf2, and according to selecting signal S1 to decide how to export described these data to microprocessor 21.
It is noted that, when microprocessor 21 require in regular turn first address of reading and second address, with follow-up third and fourth ... the address be continuous arrangement (for example, second address equals first address and adds 1) time, then memory control unit 231 enters consecutive access pattern (continuous read mode) with serial storage device 22, and promptly memory control unit 231 will utilize the data of selecting signal S1 control multiplexer MUX mutual (taking turns) to export to be stored in corresponding described these addresses among impact damper Buf1 and the Buf2.And require the discontinuous arrangement in first address and second address of reading (for example in regular turn when microprocessor 21, second address equals first address and adds n (n is a positive integer, n＞1)) time, then memory control unit 231 enters special read mode with serial storage device 22, described special read mode is meant that it reads the tupe of storage device 22 sequence of addresses to microprocessor 21 in change, for example the processing when instructions such as execution jump JMP, interrupt INT, mobile MOVC.
In addition, the label DI that indicates in Fig. 2 is meant the data such as instruction, address that inputed to storage device 22 by memory control unit 231; Label DO is meant the program code data that is exported to the S/P converting unit by storage device 22; And label CS is meant when having a plurality of storage devices 22 to exist simultaneously, and memory control unit 231 is used for selecting to use the drive signal of which storage device 22.
Below describe the function mode of memory control system 20 under continuous read mode of one embodiment of the invention in detail.
Fig. 3 be show the frequency period of microprocessor 21 of one embodiment of the invention and system's fundamental frequency frequency period waveform and under the consecutive access pattern memory control system 20 respectively install the synoptic diagram of operating state.
In the drawings, label MCUclk is the frequency period of microprocessor 21 runnings; Label xclk is the frequency period of system's fundamental frequency.Must notice that because the storage device of serial is when data transmission, the time of handling one (bit) is an xclk, and in the present embodiment, is that hypothesis microprocessor 21 is one or two cycle (2T) microprocessor.Therefore, it is the frequency period T0+T1=2T of two MCUclk that processor 21 is finished the acquisition data required time big or small with carrying out a byte (byte), i.e. eight xclk.So the execution speed of microprocessor 21 is xclk/4.
Please refer to Fig. 2, Fig. 3, and suppose that at this microprocessor 21 need read the continuation address 0,1,2 in the storage device 22 ... corresponding data DATA0, DATA1, DATA2 Certainly, the continuation address that read of microprocessor 21 is not limited to above-mentioned example.In addition, be simplified illustration, the conversion details of P/S converting unit and S/P converting unit be not described in detail in detail at this.
At first during time t0, the signal Rs that reads that address 0 is read in microprocessor 21 outputs one gives memory control unit 231, requires the data DATA0 of address 0 correspondence in the acquisition storage device 22.And under present framework, microprocessor 21 is for the first time during reading of data, and storage device 22 must spend the instruction (command) that eight xclk decipher to read eight (1byte) among the signal Rs (time t0～t1) and expend 24 xclk (time t1～t4) deciphers the address information that reads signal Rs 24 (3byte) earlier; Then, storage device 22 must read the data DATA0 of address 0 and by the S/P converting unit data DATA0 be delivered to the first impact damper Buf1 when time t4～t5; Afterwards, storage device 22 reads the data DATA1 of address 1 again and by the S/P converting unit data DATA1 is delivered to the second impact damper Buf2 when time t5～t6.Therefore, storage device 22 be ready to data DATA1 give microprocessor 22 before, time that altogether must cost t0～t6 is finished above-mentioned data warming-up exercise.The time of whole preparation DATA0 and DATA1 need be expended 48 xclk altogether, promptly occupies the processing time of 48/8=6 byte.
The memory control system 20 of one embodiment of the invention is for the processing speed of accelerating total system, keep the speed of microprocessor 21 and storage device 22 synchronous simultaneously, then when data DATA1 is still unripe, internal memory control device 22 can send the pseudo-order that consumes six bytes (byte) and give microprocessor 21, postpones the time that microprocessor 21 receives data.As shown in Figure 3, between time t0～t6, and when data DATA0 and DATA1 are still unripe, memory control unit 231 is met together and is sent three short skip instruction SJMP-2 to microprocessor 21, so that the address that microprocessor 21 sends repeats to return 0, be ready to just stop up to initial data DATA0 and DATA1.-2 instructions that its short-and-medium skip instruction SJMP accounts for a byte and makes the address counter (counter) of microprocessor 21 retreat for two steps account for a byte, and therefore three SJMP-2 consume the processing time of 6byte altogether.
And memory control system 20 cooperates the function mode of pseudo-order to be described in detail as follows:
Please refer to Fig. 2, Fig. 3, time t0～t1: memory control unit 231 sends first pseudo-order SJMP-2 and gives microprocessor 21, the instruction that this moment, signal Rs was read in storage device 22 decodings, and the address of the counter of microprocessor 21 (not icon) is 0.
Time t1～t2: microprocessor 21 is handled first-2 instruction, and automatically the address of its counter is added to 1 by 0, and the address information of signal Rs is read in storage device 22 decodings.
Time t2～t3: memory control unit 231 sends second pseudo-order SJMP-2 and gives microprocessor 21.And the counter of microprocessor 21 adds to 2 with the address automatically, but simultaneously microprocessor 22 also subtracts 2 according to first-2 instruction with the address 2 of counter, obtains address 0.At this moment, storage device 22 continues the address information that signal Rs is read in decoding.
Time t3～t4: microprocessor 21 is handled second-2 instruction, and automatically the address of its counter is added to 1 by 0, and storage device 22 continues the address information that signal Rs is read in decoding simultaneously.
Time t4～t5: memory control unit 231 sends the 3rd pseudo-order SJMP-2 and gives microprocessor 21.And the counter of microprocessor 21 adds to 2 with the address automatically, and simultaneously microprocessor 22 also can subtract 2 with the address 2 of counter according to second-2 instruction, obtains address 0.At this moment, storage device 22 has been deciphered and has been finished the address information that reads signal Rs, transfers to impact damper Buf1 according to the address 0 reading of data DATA0 that reads signal Rs and with described data by the S/P converting unit.
Time t5～t6: microprocessor 21 is handled the 3rd instruction-2, and the address with its counter adds to 1 by 0 automatically, simultaneously storage device 22 is according to the address 1 (being the address 1 of the counter of microprocessor 21) of reading signal Rs, and reading of data DATA1 also transfers to impact damper Buf2 with described data by the S/P converting unit.This moment, data were ready to complete, and multiplexer MUX receives data DATA0 and DATA1 simultaneously.
Then, time t6～t7: owing to all have data among impact damper Buf1, the Buf2, so memory control unit 231 just produces selection signal S1 to multiplexer MUX.Multiplexer MUX is according to selecting signal S1, and the data DATA0 of output corresponding address 0 gives microprocessor 21 in impact damper Buf1.Simultaneously, memory control unit 231 continues to read the data DATA2 of storage device 22 next addresses 2, and exports impact damper Buf1 to.Therefore, impact damper Buf1 has DATA2, Buf2 and has DATA1 in having.
Time t7～t8: all have data among impact damper Buf1, the Buf2 at this moment, so memory control unit 231 just produces selection signal S1 to multiplexer MUX.Multiplexer MUX is according to selecting signal S1, and the data DATA1 of output corresponding address 1 gives microprocessor 21 in impact damper Buf2.Simultaneously, memory control unit 231 continues to read the data DATA3 of storage device 22 next addresses 3, and exports impact damper Buf2 to.At this moment, impact damper Buf1 has DATA2, Buf2 and has DATA3 in having.
Time t8～t9: all have data among impact damper Buf1, the Buf2 at this moment, so memory control unit 231 just produces selection signal S1 to multiplexer MUX.Multiplexer MUX is according to selecting signal S1, and the data DATA2 of output corresponding address 2 gives microprocessor 21 in impact damper Buf1.Simultaneously, memory control unit 231 continues to read the data DATA4 of storage device 22 next addresses 4, and exports impact damper Buf1 to.Therefore, impact damper Buf1 has DATA4, Buf2 and has DATA3 in having.And after function mode all similar to time t8～t9, the rest may be inferred.
Mode under continuous read mode, is utilized the interworking of impact damper Buf1, Buf2 according to this, then can quicken the speed that storage device 22 is supplied with microprocessors 21 data.And after the time of the handling elongation, the processing speed of total system can reach convergence at xclk/4, then can solve prior art total system slow processing problem.
It is noted that if microprocessor 21 remains on the pattern that reads the continuation address data fully, the processing speed of memory control system 20 then of the present invention can be very fast, reach the speed of above-mentioned convergence at xclk/4.But in the practical application, microprocessor 21 still has the special status that reads discontinuous address data, described these special statuss is classified as the special processing pattern of above-mentioned microprocessor 21 at this.And may cause storage device 22 and microprocessor 21 nonsynchronous problems in order to solve described these special statuss, and below will provide three kinds of examples to illustrate, the function mode of memory control system 20 under special read mode of one embodiment of the invention is described in detail in detail.Certainly, be not limited to following three examples during practical application, the operator who is familiar with this area will be understood that, the situation that reads of other discontinuous address data, all can make an amendment slightly according to technology of the present invention and solve, described these settling modes also should be included in the claim of the present invention.
Fig. 4 A and Fig. 4 B are embodiment who shows the special read mode of memory control system 20 of the present invention.Shown in Fig. 4 A, suppose microprocessor 21 read continuation address (... 26, data 27,28) are after a period of time, need change into and read address 9,10,11 ... data, then it sends one at time t35 microprocessor 21 and comprises skip instruction JMP and give memory control unit 231 with the signal Rs that reads that reads address 9, requirement changes the address of reading into discontinuous address 9 by address 28, and then this moment, memory control unit 231 entered special read mode with storage device 22.Shown in 4B figure, under this special read mode, in order to allow the microprocessor 21 can normal operation and do not interrupt, between time t35～t41, memory control unit 231 is met together and is sent three short skip instruction SJMP-2 to microprocessor 21, so that the address that microprocessor 21 sends repeats 9 and 10, until the data-preparing of the data DATA9 of difference corresponding address 9 and 10 and DATA10 is good.T35～t41 will postpone the processing time of microprocessor 21 6 bytes this section period, and make storage device 22 can be ready to data earlier, to export data DATA9, DATA10, the DATA11 of the address 9,10,11 that microprocessor 21 requires respectively at time t41～t42, t42～t43, t43～t44.Therefore, microprocessor 21 can be when reading the data of discontinuous address, still can be synchronous with storage device 22.
Fig. 5 A, Fig. 5 B, with Fig. 5 C be another embodiment that shows the special read mode of memory control system 20 of the present invention.Shown in Fig. 5 A, suppose that microprocessor 21 execution skip instruction JMP desire to skip to address 30, and during execution command JMP, desire to read the data of address 3,4 correspondences again because other need for equipment makes microprocessor 21 send interrupt instruction INT, this moment, memory control unit 231 also entered special read mode with storage device 22.
Shown in Fig. 5 B, Fig. 5 C, under this special read mode, when time t45, memory control unit 231 receive microprocessor 21 send comprise short skip instruction JMP and address 30 read signal Rs, and read signal RS according to this and send pseudo-order SJMP-2 to microprocessor 21, to postpone the speed of microprocessor 21, make storage device 22 can have time enough to read the data of address 30,31.Yet, t45～t49 during the processing of skip instruction, microprocessor 21 sends interrupt instruction INT, requires preferentially to read the data of address 3,4.Therefore, memory control unit 231 just according to instruction INT, sends at time t49～t55 that totally three pseudo-order SJMP-2 postpone the speed of microprocessor 21, makes storage device 22 be ready to the data of address 3,4 correspondences.Therefore, when time t55～t56, t56～t57, storage device 22 just can with microprocessor 21 output data DATA3 and DATA4 synchronously and respectively.After, when time t57, microprocessor 21 can go back to continue to read the data of address 30 automatically.Therefore, memory control unit 231 is during time t57～t63, send three pseudo-order SJMP-2 equally, to make storage device 22 be ready to the data of address 30,31, and make storage device 21 at time t63～t64, t64～t65, t65～t66, t66～t67, can export the data of corresponding address 30,31,32,33 synchronously and give microprocessor 21.
Fig. 6 A, Fig. 6 B, with Fig. 6 C be another embodiment that shows the special read mode of memory control system 20 of the present invention.As shown in Figure 6A, suppose that microprocessor 21 execution skip instruction JMP skip to address 70, and when reading the data of address 70,71, because some demand makes microprocessor 21 send move MOVC and desires to read the data of address 99 in the plug-in internal memory, this moment, memory control unit 231 also entered special read mode with storage device 22.Shown in Fig. 5 B, Fig. 5 C, under this special read mode, when time t76, microprocessor 21 sends the data that move MOVC desires to read address 99 in the plug-in internal memory, this moment microprocessor 21 counter still in the address 72.(time t76) simultaneously, memory control unit 231 begin to send pseudo-order SJMP-2 and give microprocessor 21, to postpone the time of microprocessor 21.Until time t81～t82 storage device 22 reads the data DATA99 of address 99, and it is temporary to export DATA99 to impact damper Buf2.And in time t82～83 o'clock, microprocessor 21 can go back to continue to read the data of address 72, so memory control unit 231 can continue to send pseudo-order SJMP-2 in time t82～88 and give microprocessor 21, postpones the time of microprocessor 21.Must notice that when time t82～t88, the data of DATA99 can be not deleted, impact damper Buf2 can keep in described data always; And in time t86～87 o'clock, storage device 22 will read the data DATA72 of address 72 and export impact damper Buf1 to temporary; And in time t87～88, memory control unit 231 will suspend the frequency xclk of storage device 22, make storage device 22 at this moment between point stop to read or export any data, and make data among the impact damper Buf2 not by also moving, still be data DATA99.
Afterwards, during time t88～t89, owing to all have data among impact damper Buf1, the Buf2, so memory control unit 231 just produces and selects signal S1 to multiplexer MUX.Multiplexer MUX gives microprocessor 21 according to the data DATA72 that selects signal S1 OPADD 72, and storage device 22 reads the data of next address 73 and exports impact damper Buf1 to simultaneously.And next time t89～t90, because the setting of MOVC instruction, so reading the address, microprocessor 21 becomes 99, and make multiplexer MUX according to selecting signal S1, data by impact damper Buf2 OPADD 99 are given microprocessor 21, and storage device 22 reads the data DATA74 of the next address 74 of address 73 originally simultaneously, to keep in to impact damper Buf2.Next, when time t90～t91, t91～t92, microprocessor 21 is just got back to continuous read mode and storage device 22 synchronous operations, and makes microprocessor 21 read data DATA73 and DATA74 respectively.
In sum, even under the various special read modes that read discontinuous address, memory control system 20 of the present invention still can keep synchronously with the running of storage device 22.And because the running major part of general microprocessor is to read continuation address.Therefore, compare in prior art, memory control system of the present invention all can make the speed synchronization of storage device and microprocessor and reach the effect of also quick program code read data under any state.
Moreover Fig. 7 is the process flow diagram that shows the internal storage data read method of one embodiment of the invention.Described method comprises the following step:
Step S702: beginning.
Step S704: receive one first address and one second address and a three-address.
Step S706: judge whether first address and second address arrange continuously, if skip to step S708; If not, skip to step S710.
Step S708: read and first data and second data of temporary corresponding first address and second address to internal memory, and export first data and second data in regular turn to a microprocessor.
Step S710: provide a pseudo-order to postpone described microprocessor one Preset Time, and in described Preset Time, read and second data and the 3rd data of temporary corresponding described second address and described three-address to described internal memory, and export second data and the 3rd data in regular turn to a microprocessor.
Step S712: finish.
Palpus attention person, above-mentioned internal memory can be a serial ROM (read-only memory) or a serial flash ROM, and above-mentioned data can be rom program code (ROM Code).
The above only is preferred embodiment of the present invention, only is illustrative for the purpose of the present invention, and nonrestrictive.Those skilled in the art is understood, and can carry out many changes to it in the spirit and scope that claim of the present invention limited, revise, even equivalence, but all will fall within the scope of protection of the present invention.
Claims (12)
1. memory control system, it is characterized in that: it includes:
One microprocessor, it exports a plurality of addresses, and described these addresses comprise one first address and one second address or a three-address at least;
One storage device, it stores the data of corresponding described these addresses;
One first impact damper, it is in order to temporary one first data or one the 3rd data;
One second impact damper, it is in order to temporary one second data;
One memory control unit, it receives described first address, reads first data of corresponding described first address according to described first address to described storage device; And receive described second address, read second data of corresponding described second address according to described second address to described storage device; Or receive described three-address, read the 3rd data of corresponding described three-address according to described three-address to described storage device; Wherein, when all having arbitrary described data in described first, second impact damper, described memory control unit produces one and selects signal; And
One multiplexer, it receives described first data and described second data or described the 3rd data, exports described first data, second data or described the 3rd data to described microprocessor according to described selection signal.
2. according to the memory control system of claim 1 record, it is characterized in that: described storage device is a serial ROM (read-only memory) or a serial flash ROM.
3. according to the memory control system of claim 1 record, it is characterized in that: when described first address and described second address are when arranging continuously, described multiplexer is exported described first data and is exported described second data in the second phase according to described selection signal between the first phase.
4. according to the memory control system of claim 1 record, it is characterized in that: when the initial state of described microprocessor begins to read the data of described storage device, described memory control unit provides at least one pseudo-order to postpone described microprocessor between one third phase, till described first impact damper has described first data and described second impact damper and has described second data.
5. according to the memory control system of claim 1 record, it is characterized in that: when described first address and the discontinuous arrangement in described second address, described memory control unit provides at least one pseudo-order to postpone described microprocessor between one third phase, till described first impact damper has described the 3rd data and described second impact damper and has described second data.
6. according to the memory control system of claim 4 record, it is characterized in that: described storage device utilizes order code, the address code of the described microprocessor output of decoding between the described third phase and reads described first data and described second data.
7. according to the memory control system of claim 5 record, it is characterized in that: described storage device utilizes order code, the address of the described microprocessor output of decoding between the described third phase and reads described second data and described the 3rd data.
8. according to the memory control system of claim 1 record, it is characterized in that: also comprising one side by side to the serial conversion unit, is to be serial output in order to described these address translation that will import side by side.
9. according to the memory control system of claim 1 record, it is characterized in that: also comprising one and be serial to converting unit arranged side by side, is to be converted to output arranged side by side in order to described these data with the serial input.
10. according to the memory control system of claim 1 record, it is characterized in that: described data are the rom program code.
11. an internal storage data read method is characterized in that: its step that comprises has:
Receive one first address and one second address and a three-address;
Judge whether described first address and described second address arrange continuously, when arrange continuously described first address and described second address, read and first data and second data of temporary corresponding described first address and described second address to described internal memory, and export described first data and described second data in regular turn to a microprocessor; And when described first address and the discontinuous arrangement in described second address, provide a pseudo-order to postpone described microprocessor one Preset Time, and in described Preset Time, read and second data and the 3rd data of temporary corresponding described second address and described three-address to described internal memory, and export described second data and described the 3rd data in regular turn to described microprocessor.
12. the internal storage data read method according to claim 11 record is characterized in that: save as an a string capable ROM (read-only memory) or a serial flash ROM in described, and described data are the rom program code.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNA2008100827451A CN101251794A (en) | 2008-03-05 | 2008-03-05 | Recording internal memory data reading system and method |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNA2008100827451A CN101251794A (en) | 2008-03-05 | 2008-03-05 | Recording internal memory data reading system and method |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN101251794A true CN101251794A (en) | 2008-08-27 |
Family
ID=39955196
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CNA2008100827451A Pending CN101251794A (en) | 2008-03-05 | 2008-03-05 | Recording internal memory data reading system and method |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN101251794A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN106326138A (en) * | 2015-07-03 | 2017-01-11 | 比亚迪股份有限公司 | Flash memory and access control method for data in flash memory |
-
2008
- 2008-03-05 CN CNA2008100827451A patent/CN101251794A/en active Pending
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN106326138A (en) * | 2015-07-03 | 2017-01-11 | 比亚迪股份有限公司 | Flash memory and access control method for data in flash memory |
| CN106326138B (en) * | 2015-07-03 | 2019-11-05 | 比亚迪股份有限公司 | The access control method of flash memory and flash memory internal data |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN103034515B (en) | A kind of satellite navigation receiver FPGA rapid loading method | |
| US20150161019A1 (en) | Information processing apparatus with debugging unit and debugging method therefor | |
| CN103064805A (en) | Serial Peripheral Interface (SPI) controller and communication method | |
| CN101477443B (en) | NAND control system and control method | |
| CN102621478B (en) | Dynamic test device and system of radio-frequency front-end chip | |
| US20100272162A1 (en) | Synchronous serial programmable interface | |
| CN110488764A (en) | A kind of engraving machine motion controller and its engraving equipment and method based on FPGA | |
| CN106648758A (en) | Multi-core processor BOOT starting system and method | |
| CN102467472B (en) | System-on-chip (SoC) chip boot startup device and SoC chip | |
| CN106980587B (en) | General input/output time sequence processor and time sequence input/output control method | |
| US20120158394A1 (en) | Simulation apparatus and method for multicore system | |
| CN101421705A (en) | Multi media card with high storage capacity | |
| CN101702144A (en) | Control device and control method of DMA controller | |
| CN101251794A (en) | Recording internal memory data reading system and method | |
| CN101666855A (en) | Universal test system and method of integrated circuit | |
| CN103902303A (en) | Program solidifying method based on configuration table | |
| CN201444301U (en) | Device capable of unifying interfaces of multi-peripheral units to be one USB interface | |
| CN102542525A (en) | Information processing equipment and information processing method | |
| CN101799793A (en) | Flash memory control method and device | |
| CN103488601A (en) | Clock delay method, clock delay system, clock delay equipment, data access method, data access system and data access equipment | |
| CN101807049A (en) | Method of externally expanding parallel bus based on embedded ARM CPU | |
| CN102323903B (en) | SOC (system-on-chip) chip simulation system and method | |
| CN103760826B (en) | Towards the PCI multifunctional digital control system of high speed embedded control system | |
| CN102156629A (en) | Method for extending 32-bit instructions | |
| CN106444633B (en) | Motion control system |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| C12 | Rejection of a patent application after its publication | ||
| RJ01 | Rejection of invention patent application after publication |
Application publication date: 20080827 |