CN101246844A - Production method of hatch and interlayer window hatch - Google Patents
Production method of hatch and interlayer window hatch Download PDFInfo
- Publication number
- CN101246844A CN101246844A CNA200710079121XA CN200710079121A CN101246844A CN 101246844 A CN101246844 A CN 101246844A CN A200710079121X A CNA200710079121X A CN A200710079121XA CN 200710079121 A CN200710079121 A CN 200710079121A CN 101246844 A CN101246844 A CN 101246844A
- Authority
- CN
- China
- Prior art keywords
- opening
- manufacture method
- dry etching
- etching step
- dielectric layer
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Images
Abstract
The invention is a method for manufacturing an opening, comprising the steps that: a substrate is provided, which has a conducting part at least including a conductor layer and a protecting layer from bottom to top and a dielectric layer covering the conducting part; with reaction gas containing high polymer gas, a first dry etching is carried on the dielectric layer, an opening is formed on the protecting layer, the bottom part of the opening has an initial size, and the angle between the opening bottom and the inner wall of the opening is an obtuse angle; the opening is enlarged, so that the bottom part of the opening has the objective size larger than the initial size, and the opening at least does not bear the conductor layer.
Description
Technical field
The present invention is relevant for a kind of manufacture method of semiconductor structure, particularly relevant for the manufacture method of a kind of opening and interlayer hole opening.
Background technology
In integrated circuit flourish today, element downsizing and the integrated trend that is inevitable also are the important topics of all circles' develop actively.Integrated level increase when integrated circuit, make chip surface can't provide enough areas when making required intraconnections (interconnect), dwindle the intraconnections demand that the back is increased for adapting to semiconductor element, two-layer or even the above many integrated circuit components of metal level design just becoming the gradually institute of multilayer must employing mode.
In order not allow each conductor layer (as electrode and lead, or the lead of different layers) directly contact and being short-circuited between, usually isolated with dielectric layer, and formed contact hole connector (contactplug) or interlayer hole connector (via plug) therein, to connect two-layer conductor layer up and down.
Yet, the increase with integrated level of reducing along with the semiconductor technology live width, owing to may produce stacked (overlay) error between rete, or the design criterion of limited chemical wet etching (design rule),, aligning mistake (misalignment) very easily takes place or accurately do not connect the phenomenon of (un-landed) when forming opening at the definition dielectric layer.
Please refer to Fig. 1, is the section of structure that illustrates known interlayer hole opening.Substrate 100 is provided with aluminum conductor 110 and titanium nitride layer 120, and dielectric layer 130 covers titanium nitride layer 120 and substrate 100.In the process of etching interlayer hole opening 145,, make that interlayer hole opening 145 is not to be completed on titanium nitride layer 120 because the situation of (un-landed) that accurately do not connect takes place.And can etching penetrate dielectric layer 130, titanium nitride layer 120, and form depression 155 in aluminum conductor 110 sidewalls, expose the aluminum conductor 110 of titanium nitride layer 120 belows.Thus, in the cleaning (cleaning process) after can causing, residue such as aluminum fluoride (AlF3) that impurity and etching produce can't be removed totally, and then influence the rete of subsequent depositions in the interlayer hole opening 145, cause interlayer hole connector contact resistance value variation, reduce the electrical quality of element.After entering deep-sub-micrometer technology, the influence that these residues caused is obvious especially.
Summary of the invention
The object of the present invention is to provide a kind of manufacture method of opening, this method can be controlled the width and the degree of depth of opening, avoids producing after etching the residue that is difficult to remove.
Another object of the present invention is to provide a kind of manufacture method of interlayer hole opening, can avoid accurately not connecting the problem that causes, improve the electrical performance of element.
The object of the present invention is achieved like this, a kind of manufacture method of opening, and this manufacture method comprises:
One substrate is provided, has been formed with a conductive part and a dielectric layer on this substrate, this conductive part from bottom to top comprises a conductor layer and a protective layer at least, and this dielectric layer covers this conductive part;
The reacting gas that use contains a high polymer gas carries out one first dry etching step to this dielectric layer, forms an opening on this protective layer, and this open bottom has an original dimension, and this opening bottom surface and this opening inwall press from both sides an obtuse angle;
Carry out an opening expansion step, make this open bottom reach a target size, this target size is greater than this original dimension, and this opening does not expose this conductor layer at least.
Described this obtuse angle is greater than 93 °.
The difference in size of this target size and this original dimension is less than the thickness of this protective layer.
The material of this conductor layer comprises aluminium.
In this first dry etching step, attached to the polymer of this open top inwall more than polymer attached to this open bottom inwall.
This opening expansion step comprises one second dry etching step.
In this second dry etching step, the etching selection ratio of this protective layer and this dielectric layer is approximately between 0.92～1.2.
The reaction chamber pressure of this second dry etching step is higher than the reaction chamber pressure of this first dry etching step.
The reaction chamber pressure of this second dry etching step is between 60～200mT.
The power that this second dry etching step is used is approximately between 300～800W.
The material of this dielectric layer comprises silica.
The material of this protective layer comprises titanium/titanium nitride.
This high polymer gas comprises carbon monoxide, octafluorocyclobutane.
The flow of carbon monoxide is between 90～400sccm, and the flow of octafluorocyclobutane is between 12～20sccm.
This reacting gas more comprises a clean air.
This clean air comprises oxygen, and the flow of oxygen is less than 3sccm.
This reacting gas more comprises oxygen, argon gas and fluoroform.
The manufacture method of above-mentioned opening is utilized high polymer gas to carry out the first dry etching step earlier and is formed opening, utilizes the second dry etching step that opening is extended to target size again.The method can be controlled the degree of depth of the dielectric layer of institute's etching, avoids exposing the conductor layer of protective layer below, and then the generation of prevention residue, produces the preferable element of electrical quality.
Description of drawings
Fig. 1: the section of structure that is known interlayer hole opening.
Fig. 2 A to Fig. 2 C: the manufacturing process profile that is a kind of opening of one embodiment of the invention.
Drawing reference numeral:
100,200: substrate
110: aluminum conductor
120: titanium nitride layer
130: dielectric layer
145: the interlayer hole opening
155: depression
210: lead
213: conductor layer
216: protective layer
220: dielectric layer
230: the patterning photoresist layer
240: the interlayer hole opening
243: polymer
D: the original dimension of interlayer hole opening
D: the target size of interlayer hole opening
θ: obtuse angle
Embodiment
Shown in Fig. 2 A to Fig. 2 C, be the manufacturing process profile of a kind of opening of one embodiment of the invention.
Please refer to Fig. 2 A, present embodiment is that the manufacture method with the interlayer hole opening is that example explains, and the method for example is that substrate 200 is provided earlier, has been formed with lead 210 and dielectric layer 220 on the substrate 200.Wherein, substrate 200 for example is a silicon substrate.Lead 210 from bottom to top comprises one deck conductor layer 213 and layer protective layer 216 at least, and in the present embodiment, this layer protective layer can be one deck barrier layer.The material of conductor layer 213 for example is metal such as aluminium, copper or aluminium-containing alloy, is preferably aluminium or aluminium-containing alloy.The material of protective layer 216 for example is titanium, titanium nitride, chromium, titanium-tungsten, tantalum or tantalum nitride etc., is preferably titanium/titanium nitride.Dielectric layer 220 covers lead 210.The thickness of protective layer 216 for example is between 400～700 dusts.The material of dielectric layer 220 for example is insulating material such as silica, it for example is to carry out high density Plasma-activated Chemical Vapor Deposition technology earlier, fill the gap between the lead 210, then be that reacting gas carries out chemical vapor deposition method with silicon tetraethyl acid esters TEOS, carry out planarization more afterwards and form dielectric layer 220.
Then, please refer to Fig. 2 B, on dielectric layer 220, form one deck patterning photoresist layer 230.The formation method of patterning photoresist layer 230 for example is to form one deck positive photoetching rubber in rotary coating (spin coating) mode on dielectric layer 220 earlier, and the development of carrying out pattern after exposure forms.
Then be mask with patterning photoresist layer 230, use the reacting gas that contains high polymer gas that dielectric layer 220 is carried out the first dry etching step.The first dry etching step for example is the reactive ion etching method, and it for example is to form the interlayer hole opening 240 with original dimension d on protective layer 216.High polymer gas refers in etching process can produce the gas that is attached to the etching sidewall than heteropolymer 243, as octafluorocyclobutane (C4F8) and carbon monoxide (CO).The deposition of these polymer can make the profile change of interlayer hole opening 240 inwalls tiltedly contract toward in, and the bottom surface of interlayer hole opening 240 and its inwall press from both sides an obtuse angle θ, and obtuse angle θ for example is greater than 93 °.Because the less relation of original dimension d of interlayer hole opening 240 bottoms, interlayer hole opening 240 can be controlled on the protective layer 216 easily, can not exceed the scope of protective layer 216, also just can not cause the situation that does not accurately connect to take place.The reacting gas of the first dry etching step can also comprise other etching gas such as fluoroform (CHF3), inert gas such as argon gas (Ar) or nitrogen (N2) etc., with clean air such as oxygen (O2).
In one embodiment, the reacting gas of the first dry etching step comprises high polymer gas octafluorocyclobutane and carbon monoxide, and can also include clean air oxygen, inert gas argon gas and fluoroform.Wherein, the flow of octafluorocyclobutane for example is between 12～20sccm, the flow of carbon monoxide for example is between 90～400sccm, preferable for example be between between 100～330sccm, the flow of oxygen for example be between between 0～3sccm, the flow of argon gas for example is between 300～400sccm, and the flow of fluoroform for example is between 30～50sccm.In addition, the pressure of reaction chamber for example is between 20～60mT, and employed power for example is about 600～1800W.
Then, please refer to Fig. 2 C, carry out the second dry etching step, just the opening expansion step.For example being to use carbon tetrafluoride (CF4) in the second dry etching step is reacting gas, and heightens reaction chamber pressure, and it for example is to heighten to 60mT～200mT, is preferably 80～120mT.Low radio frequency power in the use is as between 300～800W.Because in the first dry etching step, polymer 243 is attached to interlayer hole opening 240 tops with middle more, the distribution of bottom is few, so can increase the critical dimension (bottom CD) of interlayer hole opening 240 bottoms after the second dry etching step, reaches target size D.
In one embodiment; material is that the dielectric layer etching rate of silica arrives 1.2nm/sec between 0.7; material be protective layer 216 etching rates of titanium/titanium nitride between 0.84 to 1.34nm/sec, the etching selection ratio of protective layer 216 and dielectric layer 220 is approximately between 0.92～1.2.Therefore, in the second dry etching step process, the size of horizontal expansion institute etching (difference in size of target size D and original dimension d just) is with vertically the size of degree of depth institute etching can be similar.Decide the length of etch period according to the target size D of interlayer hole opening 240; even if the result that opening enlarges; can make interlayer hole opening 240 surpass the scope of protective layer 216 slightly; and the downward etching of sidewall of past lead 210; but because the difference in size of target size D and original dimension d is less than the thickness of protective layer 216; therefore, the degree of depth that interlayer hole opening 240 does not accurately connect can't surpass the thickness of protective layer 216, and is avoided exposing conductor layer 213.
Said method not only can reach the target size D of interlayer hole opening 240, can also avoid interlayer hole opening 240 inside to produce the residue that is difficult to clean, and then exempt the trouble of follow-up cleaning.In addition, the film layer quality that deposition forms in interlayer hole opening 240 also can be improved afterwards, further improves the electrical performance of interlayer hole connector and the usefulness of integral member.
Though the foregoing description is to be that example explains with the interlayer hole opening, yet the manufacture method of opening proposed by the invention, be not limited to be used in the making of interlayer hole opening, other for example the formation of contact window, irrigation canals and ditches etc. also can be suitable for the method that the present invention proposes.
In sum, the manufacture method of the opening that the present invention proposes, utilizing high polymer gas is the reacting gas of the first dry etching step, forms the less opening of size earlier, guarantees that the position that opening forms is on protective layer.Utilize the second dry etching step again, opening is enlarged, to reach predetermined target size.
The manufacture method of this kind opening not only can reach the predetermined target size that needs, and accurately controls the width and the degree of depth of opening, exempts the situation that does not accurately connect, and avoids exposing the conductor layer of below.And can prevent to produce the residue that is difficult to remove after the etching, reach the advantage of lift elements electrical performance.
Though the present invention discloses with specific embodiment; but it is not in order to limit the present invention; any those skilled in the art; the displacement of the equivalent assemblies of under the prerequisite that does not break away from design of the present invention and scope, having done; or, all should still belong to the category that this patent is contained according to equivalent variations and modification that scope of patent protection of the present invention is done.
Claims (17)
1. the manufacture method of an opening is characterized in that this manufacture method comprises:
One substrate is provided, has been formed with a conductive part and a dielectric layer on this substrate, this conductive part from bottom to top comprises a conductor layer and a protective layer at least, and this dielectric layer covers this conductive part;
The reacting gas that use contains a high polymer gas carries out one first dry etching step to this dielectric layer, forms an opening on this protective layer, and this open bottom has an original dimension, and this opening bottom surface and this opening inwall press from both sides an obtuse angle;
Carry out an opening expansion step, make this open bottom reach a target size, this target size is greater than this original dimension, and this opening does not expose this conductor layer at least.
2. the manufacture method of opening as claimed in claim 1, it is characterized in that: described this obtuse angle is greater than 93 °.
3. the manufacture method of opening as claimed in claim 1, it is characterized in that: the difference in size of this target size and this original dimension is less than the thickness of this protective layer.
4. the manufacture method of opening as claimed in claim 1, it is characterized in that: the material of this conductor layer comprises aluminium.
5. the manufacture method of opening as claimed in claim 1 is characterized in that: in this first dry etching step, attached to the polymer of this open top inwall more than polymer attached to this open bottom inwall.
6. the manufacture method of opening as claimed in claim 1, it is characterized in that: this opening expansion step comprises one second dry etching step.
7. the manufacture method of opening as claimed in claim 6, it is characterized in that: in this second dry etching step, the etching selection ratio of this protective layer and this dielectric layer is approximately between 0.92～1.2.
8. the manufacture method of opening as claimed in claim 6, it is characterized in that: the reaction chamber pressure of this second dry etching step is higher than the reaction chamber pressure of this first dry etching step.
9. the manufacture method of opening as claimed in claim 6, it is characterized in that: the reaction chamber pressure of this second dry etching step is between 60～200mT.
10. the manufacture method of opening as claimed in claim 6 is characterized in that: the power that this second dry etching step is used is approximately between 300～800W.
11. the manufacture method of opening as claimed in claim 1 is characterized in that: the material of this dielectric layer comprises silica.
12. the manufacture method of opening as claimed in claim 1 is characterized in that: the material of this protective layer comprises titanium/titanium nitride.
13. the manufacture method of opening as claimed in claim 1 is characterized in that: this high polymer gas comprises carbon monoxide, octafluorocyclobutane.
14. the manufacture method of opening as claimed in claim 13 is characterized in that: the flow of carbon monoxide is between 90～400sccm, and the flow of octafluorocyclobutane is between 12～20sccm.
15. the manufacture method of opening as claimed in claim 1 is characterized in that: this reacting gas more comprises a clean air.
16. the manufacture method of opening as claimed in claim 15 is characterized in that: this clean air comprises oxygen, and the flow of oxygen is less than 3sccm.
17. the manufacture method of opening as claimed in claim 1 is characterized in that: this reacting gas more comprises oxygen, argon gas and fluoroform.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN200710079121XA CN101246844B (en) | 2007-02-13 | 2007-02-13 | Production method of hatch and interlayer window hatch |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN200710079121XA CN101246844B (en) | 2007-02-13 | 2007-02-13 | Production method of hatch and interlayer window hatch |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN101246844A true CN101246844A (en) | 2008-08-20 |
| CN101246844B CN101246844B (en) | 2010-08-18 |
Family
ID=39947195
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN200710079121XA Active CN101246844B (en) | 2007-02-13 | 2007-02-13 | Production method of hatch and interlayer window hatch |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN101246844B (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN113192825A (en) * | 2021-04-26 | 2021-07-30 | 广州粤芯半导体技术有限公司 | Manufacturing method of split-gate trench power device |
| CN114270525A (en) * | 2020-03-24 | 2022-04-01 | 京东方科技集团股份有限公司 | Display substrate, preparation method thereof and display panel |
Family Cites Families (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6146996A (en) * | 1998-09-01 | 2000-11-14 | Philips Electronics North America Corp. | Semiconductor device with conductive via and method of making same |
| CN1206709C (en) * | 2001-04-02 | 2005-06-15 | 华邦电子股份有限公司 | Etching method for opening with high height-to-width ratio |
| US7157380B2 (en) * | 2003-12-24 | 2007-01-02 | Intel Corporation | Damascene process for fabricating interconnect layers in an integrated circuit |
-
2007
- 2007-02-13 CN CN200710079121XA patent/CN101246844B/en active Active
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN114270525A (en) * | 2020-03-24 | 2022-04-01 | 京东方科技集团股份有限公司 | Display substrate, preparation method thereof and display panel |
| CN113192825A (en) * | 2021-04-26 | 2021-07-30 | 广州粤芯半导体技术有限公司 | Manufacturing method of split-gate trench power device |
Also Published As
| Publication number | Publication date |
|---|---|
| CN101246844B (en) | 2010-08-18 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| JP5122106B2 (en) | Carbon-containing film etching method and semiconductor device manufacturing method using the same | |
| US7745331B2 (en) | Method for fabricating contact plug in semiconductor device | |
| KR100415045B1 (en) | Semiconductor device and method of manufacturing the same | |
| CN101447448B (en) | Etching method and uses of hole formation in stack of layers | |
| CN101246844B (en) | Production method of hatch and interlayer window hatch | |
| KR100652791B1 (en) | Method for fabrication of semiconductor device | |
| US6083845A (en) | Etching method | |
| KR100464430B1 (en) | Method of etching aluminum layer using hard mask and metalization method for semiconductor device | |
| TW200824002A (en) | Method for fabricating semiconductor device | |
| US20090321940A1 (en) | Method for Manufacturing Contact Openings, Method for Manufacturing an Integrated Circuit, an Integrated Circuit | |
| US7341955B2 (en) | Method for fabricating semiconductor device | |
| US20080174029A1 (en) | semiconductor device and method of forming metal pad of semiconductor device | |
| KR100354282B1 (en) | Semiconductor device and manufacturing method thereof | |
| US7648910B2 (en) | Method of manufacturing opening and via opening | |
| TWI722058B (en) | Semiconductor structure and method for manufacturing the same | |
| CN101308809A (en) | Manufacture method of aluminum conductive wire | |
| KR100844029B1 (en) | Plasma etching method | |
| CN100499070C (en) | Making method for dual enchasing structure | |
| KR100997776B1 (en) | Method of manufacturing semiconductor device | |
| JP4257357B2 (en) | Manufacturing method of semiconductor device | |
| KR100613393B1 (en) | Method of manufacturing semiconductor device | |
| KR100672152B1 (en) | Method of manufacturing flash memory device | |
| US20060105573A1 (en) | Method for selective plasma etch of an oxide layer | |
| US8440557B2 (en) | Method for fabricating a semiconductor device by considering the extinction coefficient during etching of an interlayer insulating film | |
| US7842608B2 (en) | Method for manufacturing semiconductor device having via plug |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant |