CN101241671A

CN101241671A - Display driver and display panel module

Info

Publication number: CN101241671A
Application number: CNA2007101284941A
Authority: CN
Inventors: 森山诚一; 清家守; 末永纯一
Original assignee: Matsushita Electric Industrial Co Ltd
Current assignee: Panasonic Holdings Corp
Priority date: 2007-02-08
Filing date: 2007-07-26
Publication date: 2008-08-13
Also published as: KR20080074695A; JP2008216952A

Abstract

A display driver for reducing electric power consumption during driving a display panel, includes: a first memory circuit for storing a line of pixels constituting an image; a second memory circuit for storing pixels of the immediately previous line; an output terminal pair switch circuit which outputs voltages each corresponding to a value of a pixel stored in the first memory circuit to a plurality of output terminals respectively corresponding to the pixels; and an inter-terminal load determination circuit for determining, for every pair of selected columns of pixels constituting the image, whether or not a short circuit is to be established between two of the plurality of output terminals which respectively correspond to the two selected columns based on values of at least three out of four pixels belonging to the two selected columns which are stored in the first and second memory circuits. If the inter-terminal load determination circuit determines that a short circuit is to be established, the output terminal pair switch circuit temporarily establishes a short circuit between the two output terminals before the voltages corresponding to the values of the pixels are output to the two output terminals.

Description

Display drive apparatus and display module

Technical field

The present invention relates to be used for driving the display drive apparatus of display panel.

Background technology

In recent years, PDP (plasma display) receives publicity as the display panel of slim, big picture, high-resolution.PDP comprises and is arranged to rectangular a plurality of discharge cells as pixel, and luminous when utilizing the discharge cell discharge comes display image.

General A C type PDP has a plurality of show electrodes of be arrangeding in parallel and is set to a plurality of data electrodes vertical with these show electrodes.Because display drive apparatus drives these data electrodes, so can think with the capacity load to be driven object.

PDP just constantly towards big pictureization, high-definition, high brightness development, accompanies therewith, needs also to output to that output signal number in the display drive apparatus that drives PDP increases and the Towards Higher Voltage of output signal.Power consumption when therefore, suppressing the driving data electrode and follow its heating to become important.

When applying different current potentials between two data electrodes, these two electrodes rise used as an electric capacity.That is, owing between electrode, produced capacity load, so consume a lot of electric power when driving this capacity load.As the technology that reduces power consumption, known following Example.

Voltage between comparative electrode is certain, carry out setting in advance switch in the LCD drive g device of an inversion driving between lead-out terminal, makes short circuit between lead-out terminal.In view of the above, become mutually approaching value, the power consumption (for example with reference to patent documentation 1) after can reducing during display driver by the current potential of the lead-out terminal of short circuit.

In addition, also have in the LCD drive g device of carrying out the line inversion driving, on the common signal line that is positioned at as the medium voltage of the threshold voltage on a rough average that drives output voltage, connect the technology (for example with reference to patent documentation 2) of whole lead-out terminals.

In addition, set in advance respectively to form and be not to keep medium voltage, but kept and the nearer voltage of output voltage, promptly than the common potential line of higher voltage of medium voltage and lower voltage.The potential change direction of signal in the lead-out terminal is connected to lead-out terminal on any one common potential line before driving when changing according to display line.So, because reduced load, so can reduce power consumption (for example with reference to patent documentation 3).

[patent documentation 1] Japanese kokai publication hei 9-212137 communique (Fig. 1)

[patent documentation 2] TOHKEMY 2001-255857 communique (Fig. 1)

[patent documentation 3] TOHKEMY 2003-271105 communique (Fig. 1)

Summary of the invention

In the LCD drive g device of patent documentation 1, be prerequisite to carry out an inversion driving.In this case, because be AC driving, so on the terminal of adjacency, must apply opposite polarity current potential.In addition, when known line afterwards showed, lead-out terminal must be changed to opposite polarity current potential.Therefore the control of switch is not subjected to the influence of pixel data to be shown between terminal.

Yet, the data presentation drive unit of using as PDP, by under the situation of its former state output pixel data, the pixel whether pixel adjacent exists inverse relation, same pixel column whether online exist inverse relation to determine by pixel data.Because do not have systematicness between the pixel data of various images, so can not carry out the control identical with patent documentation 1.

In the LCD drive g device of patent documentation 2, must there be the relation of counter-rotating in the polarity that need impose on the signal of pixel between pixel adjacent.Otherwise, when driving power loss will take place on the contrary.In addition, need comprise extra large value capacitor that intermediate potential can be provided etc.

In the LCD drive g device of patent documentation 3, be prerequisite with the driving method that alternately applies predetermined high voltage and low-voltage.In addition, need comprise that generation is than the additional power supply circuit of higher voltage of medium voltage and lower voltage and extra large value capacitor etc.Be contained in them under the situation in the chip, area of chip has increased, and is doing to become in chip exterior to comprise that the number of components has increased under their situation.

In the display drive apparatus that PDP uses, though it is opposite to be not limited to be applied to the polarity of the current potential on the adjacent pixels, but as the LCD drive g device of patent documentation 3, just by its former state pixel data is imposed on data electrode, the situation that before driving data electrode is connected to the common potential line is a lot.

Power consumption when the objective of the invention is to reduce the display panel driving.

According to display drive apparatus of the present invention not only according to the variation of pixel value of row of the pixel that belongs to composing images, also according to the value that belongs to the pixel of another row, before according to pixel value voltage being outputed on described two lead-out terminals, respectively and temporary transient short circuit between corresponding two lead-out terminals of described two row.

More particularly, display drive apparatus according to the present invention comprises: the 1st memory circuit, the 1 row pixel that is used to store composing images; The 2nd memory circuit is used for storing the 1 row pixel that was right after before the 1 row pixel that described the 1st memory circuit is stored; On-off circuit between lead-out terminal is used for and will all outputs to respectively and the corresponding a plurality of lead-out terminals of pixel with the corresponding voltage of the value of the pixel that is stored in described the 1st memory circuit; And load judgment circuit between terminal, be used for per 2 row to selecting from the pixel that constitutes described image, value according at least 3 pixels in 4 pixels pixel of storing in the described the 1st or the 2nd memory circuit, that belong to the 1st and the 2nd row that are listed as 2 of described selection judges whether to set up short circuit respectively and between corresponding 2 lead-out terminals of the described the 1st and the 2nd row in described a plurality of lead-out terminals.Set up under the situation of short circuit in load judgment circuit judges between terminal, will be stored in before the corresponding voltage of value of pixel in described the 1st memory circuit, that belong to the described the 1st and the 2nd row outputs to described 2 lead-out terminals, on-off circuit is temporarily set up short circuit between described lead-out terminal between described 2 lead-out terminals.

In view of the above, because between lead-out terminal, set up short circuit, so before will outputing on these lead-out terminals, the current potential between lead-out terminal is become about equally with the corresponding voltage of the value of pixel.Diminish because can make, so can suppress power consumption and heating such as the variation that drives required lead-out terminal current potential such as display panel.

According to the present invention,,, can suppress the power consumption and the heating of display drive apparatus thus so the potential change of lead-out terminal when driving is diminished because the current potential that drives between preceding lead-out terminal is become about equally.In addition,, there is no need between the output electronics, to apply electric current wiring that does not therefore need for this reason to provide extra and power circuit etc. because current potential between lead-out terminal is become when equating.Thereby, the number of components of the electric power that can suppress to consume, circuit area and external circuit.

Description of drawings

Fig. 1 is the block diagram that illustrates according to the structure of the display drive apparatus of the embodiment of the invention.

Fig. 2 is the block diagram of structure that the display drive apparatus of Fig. 1 more specifically is shown.

Fig. 3 (a) is the synoptic diagram that the 1st example of the combination of pixels that the load judgment circuit is adopted in judgement between the terminal of Fig. 1 is shown, and Fig. 3 (b) is the synoptic diagram that the variation of Fig. 3 (a) is shown.

Fig. 4 (a) is the synoptic diagram that the 2nd example of the combination of pixels that the load judgment circuit adopts in judgement between the terminal of Fig. 1 is shown, and Fig. 4 (b) is the synoptic diagram that the variation of Fig. 4 (a) is shown.

Fig. 5 (a) is the synoptic diagram that the 3rd example of the combination of pixels that the load judgment circuit is adopted in judgement between the terminal of Fig. 1 is shown, and Fig. 5 (b) is the synoptic diagram that the variation of Fig. 5 (a) is shown.

Fig. 6 (a) is the synoptic diagram that the 4th example of the combination of pixels that the load judgment circuit adopts in judgement between the terminal of Fig. 1 is shown, and Fig. 6 (b) is the synoptic diagram that the variation of Fig. 6 (a) is shown.

Fig. 7 (a) is the synoptic diagram that the 5th example of the combination of pixels that the load judgment circuit adopts in judgement between the terminal of Fig. 1 is shown, and Fig. 7 (b) is the synoptic diagram that the variation of Fig. 7 (a) is shown.

Fig. 8 (a) is the synoptic diagram that the 6th example of the combination of pixels that the load judgment circuit adopts in judgement between the terminal of Fig. 1 is shown, and Fig. 8 (b) is the synoptic diagram that the variation of Fig. 8 (a) is shown.

Fig. 9 (a) is the synoptic diagram that the 7th example of the combination of pixels that the load judgment circuit adopts in judgement between the terminal of Fig. 1 is shown, and Fig. 9 (b) is the synoptic diagram that the variation of Fig. 9 (a) is shown.

Figure 10 is the mode chart of object lesson that the short circuiting switch work of Fig. 2 is shown.

Figure 11 is the block diagram of structure that the display drive apparatus variation of Fig. 1 is shown.

Figure 12 is the timing waveform of the control signal exported from 2 timing adjusting circuits of Figure 11.

Figure 13 is the mode chart that the 1st concrete example of the short circuiting switch of Figure 11 and the work that bridging line connects switch is shown.

Figure 14 is the mode chart that the 2nd concrete example of the short circuiting switch of Figure 11 and the work that bridging line connects switch is shown.

Figure 15 is the mode chart that the 3rd concrete example of the short circuiting switch of Figure 11 and the work that bridging line connects switch is shown.

Figure 16 is the mode chart that the 4th concrete example of the short circuiting switch of Figure 11 and the work that bridging line connects switch is shown.

Figure 17 is the block diagram of structure that the display drive apparatus variation of Figure 11 is shown.

Figure 18 is the block diagram of structure of other variation that the display drive apparatus of Fig. 1 is shown.

Figure 19 (a) is the structural drawing of modular assembly that has adopted the display drive apparatus of Fig. 1, and Figure 19 (b) is the structural drawing of display module that has adopted the modular assembly of Figure 19 (a).

Figure 20 is the example block diagram that the television receiver structure of the display module that has adopted Figure 19 (b) is shown.

The accompanying drawing explanatory note:

8 bridging lines 20 the 1st memory circuit

Load judgment circuit between 30 the 2nd memory circuits, 40,240 terminals

60, on-off circuit between 260 lead-out terminals

71A, 71B, 72A, 72B, 73A export switch

81～89,180～184 short circuiting switches

81C～89C, 180C～184C bridging line connects switch

100 display drive apparatus 112PDP

202 data timing adjusting circuits, 204 control timing adjusting circuits

Embodiment

Embodiments of the invention are described with reference to the accompanying drawings.

Fig. 1 is the block diagram that illustrates according to the structure of the display drive apparatus of the embodiment of the invention.The display drive apparatus 100 of Fig. 1 comprises between video data acquisition cuicuit the 10, the 1st memory circuit the 20, the 2nd memory circuit 30, terminal on-off circuit 60 and output terminal part 90 between load judgment circuit 40, lead-out terminal.Below as an example, display drive apparatus 100 is that AC type PDP display panel is carried out device driven.

Apply pixel data D0 on video data acquisition cuicuit 10, pixel data D0 representative constitutes the pixel value of image to be displayed.Video data acquisition cuicuit 10 is obtained the pixel data D0 of serial transfer in each pulse of pixel clock CK, make the pixel data D0 storage 1 row part when taking place to shift that obtains.Video data acquisition cuicuit 10 is exported to the 1st memory circuit 20 with the pixel data D0 of storage line by line as pixel data DS.

The 1st memory circuit 20 is obtained in the timing of the scanning pulse signal P1 of display panel and storage pixel data DS line by line, exports between the 2nd memory circuit 30, terminal on-off circuit 60 between load judgment circuit 40 and lead-out terminal line by line as pixel data D1 then.The one-period that the one-period of scanning pulse signal P1 is equivalent to pixel clock CK multiply by the length of the pixel count of 1 sweep trace.

The 2nd memory circuit 30 is obtained in the timing of scanning pulse signal P1 and storage pixel data D1 line by line, and the pixel data D2 that shows as previous row exports to load judgment circuit 40 between terminal line by line then.

Above result is, the pixel data D1 of the pixel (display pixel) of the 1 new row part that will show after in the 1st memory circuit 20, having stored, the 1 row part of in the 2nd memory circuit 30, having stored the pixel data D2 that is right after the previous row display pixel that before 1 row of pixel data D1, has shown.

Load judgment circuit 40 is handled the row of the pixel of composing images between terminal with per 2 row.Specifically, load judgment circuit 40 concentrates in the 1st memory circuit 20 2 pixels that belong to this 2 row among the pixel data D2 that belongs among the pixel data D1 of storage as storage in 2 pixels of 2 row of object and the 2nd memory circuit 30 between terminal.Load judgment circuit 40 is judged according to the relation between these 4 pixels between terminal, forms switch controlling signal SD according to its result and exports.

On output terminal part 90, connecting display panel.Output terminal part 90 comprises a plurality of lead-out terminals that are electrically connected respectively with a plurality of display panel electrodes, and load drive signal SO is outputed on the display panel electrode.These display panel electrodes are connected with a plurality of data electrodes respectively.

On-off circuit 60 perhaps stops the output of pixel data D1, and produce short circuit between the terminal of output terminal part 90 according to switch controlling signal SD output pixel data D1 line by line between lead-out terminal.Here, after scanning pulse signal P1 conversion display line, the switch controlling signal SD that is used for producing short circuit comes into force, from determining the judgement of load judgment circuit 40 between terminal, to effective between beginning to show.

Fig. 2 is the block diagram of structure that the display drive apparatus 100 of Fig. 1 more specifically is shown.Video data acquisition cuicuit 10 comprise

memory element

11,12,13 ...Memory element 11 obtains from the pixel data D0 of external series input in the pulse of each pixel clock CK individual element, and the pixel data D0 that will obtain output is in memory element 12.

Memory element

12,13 ... with pixel data D0 sequential transfer give memory element 13 ...

Memory element

11,12,13 ... carry out obtaining and shifting of data repeatedly, up to having obtained 1 row pixel data D0 fully.

The 1st memory circuit 20 comprise

memory element

21,22,23 ...

Memory element

21,22,23 ... respectively with scanning pulse signal P1 synchronously read and

store storage element

11,12,13 ... the pixel data D0 that is stored.The 2nd memory circuit 30 comprise

memory element

31,32,33 ...

Memory element

31,32,33 ... respectively with scanning pulse signal P1 synchronously read and

store storage element

21,22,23 ... the pixel data of being stored.

By scanning pulse signal P1 be stored in

memory element

21,22,23 ... in pixel data then by next scanning pulse signal P1 be stored in

memory element

31,32,33 ... in.Therefore,

memory element

31,32,33 ... in stored

memory element

21,22,23 ... the pixel data that the previous row of 1 row pixel data of middle storage shows.Two pixels that belong to same row in the pixel of composing images have been stored in the memory element 21,31.Stored in the

memory element

22,32 and belonged to the pixel that is adjacent row.

Between terminal load judgment circuit 40 comprise logical circuit 41,42,43 ... with timing adjusting circuit 51,52,53 ...Logical circuit 41 is according to the value of at least 3 pixels in 4 pixels of storage in the

memory element

31,32 of the

memory element

21,22 of the 1st memory circuit 20 and the 2nd memory circuit 30, judge whether and logical circuit 41 corresponding 2 lead-out terminals between produce short circuit, then with its result as judging signal output.Logical circuit 42 is according to the value of at least 3 pixels in 4 pixels of storage in

memory element

22,32 and the

memory element

32,33, judge whether and logical circuit 42 corresponding 2 lead-out terminals between produce short circuit, then with its result as judging signal output.Logical circuit 43 also carries out same work.

Timing adjusting circuit 51 is adjusted into only timing with the judgement signal of logical circuit 41 outputs, exports as control signal SD12, SE12 (switch controlling signal SD).Timing adjusting circuit 52 is adjusted into only timing with the judgement signal of logical circuit 42, exports as control signal SD23, SE23 (switch controlling signal SD).Timing adjusting circuit 53 also carries out same work.

Between lead-out terminal on-off circuit 60 comprise

output buffer

61,62,63 ... with

output switch

71A, 71B, 72A, 72B, 73A ... with

short circuiting switch

81,82,83 ...Output terminal part 90 comprise lead-out terminal 91,92,93 ...For example can with transistor as

output switch

71A, 71B, 72A, 72B, 73A ... and

short circuiting switch

81,82,83 ...

Output buffer

61,62,63 ... will according to

memory element

21,22,23 ... the output voltage of the pixel data of being stored is adjusted into suitable voltage, and with its result output to respectively lead-out terminal 91,92,93 ...

Output buffer

61,62,63 ... be adjusted to and have suitable load driving ability.

Output switch

71A, 71B control the output of

output buffer

61,62 respectively according to control signal

SD12.Output switch

72A, 72B control the output of

output buffer

62,63 respectively according to control signal SD23.Short circuiting switch 81 is set up short circuit according to control signal SE12 lead-out terminal 91 and 92.Short circuiting switch 82 is set up short circuit according to control signal SE23 lead-out

terminal

92 and 93.

Lead-

out terminal

91,92,93 ... be connected respectively on the PDP corresponding display panel electrode, and will output to display panel corresponding to the voltage of pixel data.Lead-

out terminal

91,92,93 ... respectively with

memory element

21,22,23 ... corresponding, the included corresponding voltage of continuous pixel value during output is gone with 1.

In addition, also can by three-state buffer constitute

output buffer

61,62,63 ...Under this situation, because

output buffer

61,62,63 ... also can have the function of switch concurrently, so there is no need to comprise

output switch

71A, 71B, 72A, 72B, 73A ...

With reference to Fig. 3 (a)～Fig. 5 (b), illustrate according to comprising 2 pixels in the previous row display pixel and belonging to 3 pixels in these 4 pixels of 2 pixels of 2 pixels of next line of same row, the judgement that load judgment circuit 40 is carried out between the terminal of Fig. 1 respectively with these 2 pixels.Logical circuit 41 grades all comprise the 1st and the 2nd comparator circuit and logical and circuit.

Fig. 3 (a) is the synoptic diagram that the 1st example of the combination of pixels that load judgment circuit 40 is adopted in judgement between the terminal of Fig. 1 is shown.Fig. 3 (b) is the synoptic diagram that the variation of Fig. 3 (a) is shown.For simply, the control about the lead-out terminal 91,92 of Fig. 2 is described here.

Pixel D11, the D12 of Fig. 3 (a), Fig. 3 (b) belong to same display line, and are stored in the 1st memory circuit 20.Pixel D21, D22 are the previous row display pixels that all belongs to adjacent with the display line of pixel D11, D12, and are stored in the 2nd memory circuit 30.In addition, pixel D11, D21 belong to row CA, and pixel D12, D22 belong to the adjacent row CB with row CA.

The the 1st and the 2nd comparator circuit of logical circuit 41 grades for example is the logical OR circuit.At first, the 1st comparator circuit relatively belongs to the value (being stored in respectively in memory element 31 and the memory element 32) of the pixel D21 and the pixel D22 of same display line.These two pixels (the combination G11 of Fig. 3 (a)) are corresponding with lead-out terminal 91,92 respectively.

Under the different situation of the value of these two pixels, when showing the previous row display pixel, there is potential difference (PD) 91,92 of 2 lead-out terminals, can think between these two terminals, to have capacity load LT1.Under this situation, the inconsistent comparative result of value of these 2 pixels of the 1st comparator circuit output expression.On the contrary, under the identical situation of the value of these two pixels, can think between these 2 lead-out terminals, not have capacity load, even because short circuit between terminal, electric charge does not move between these 2 lead-out terminals yet, can not tell on so can judge short circuit.Under this situation, the comparative result of the value unanimity of these 2 pixels of the 1st comparator circuit output expression.

The 2nd comparator circuit relatively belongs to the value (being stored in respectively in memory element 31 and the memory element 21) of the pixel D21 and the pixel D11 of same row.(combination G21) is all corresponding with lead-out terminal 91 for these 2 pixels.When the value difference of these 2 pixels meaned the conversion display line, the current potential of lead-out terminal 91 changed.The comparative result whether value of these 2 pixels of the 2nd comparator circuit output expression is consistent.

The logical and circuit is obtained the logical and of the comparative result of the 1st and the 2nd comparator circuit.Promptly, comparative result at the 1st comparator circuit shows inconsistent, and the comparative result of the 2nd comparator circuit shows that (it is different with the value of pixel D22 promptly to detect pixel D21 under the inconsistent situation, and under the pixel D21 situation different) with the value of pixel D11, the logical and circuit judges is for to set up short circuit at lead-out

terminal

91 and 92 of lead-out terminals, and signal is judged in output, so that make control signal SD12, SE12 effectively carry out short circuit control.So, carry out short circuit control, promptly

open output switch

71A, 71B, and close the control of short circuiting switch 81.Under this situation, between lead-out terminal 91 and lead-out terminal 92 with the current potential equalization.

Do not detect at the 2nd comparator circuit under the situation of difference, because before and after the conversion of display line, the pixel value of same row CA does not change, so even the 1st comparator circuit detects difference, also there is no need to carry out between terminal short circuit control, power consumption is less when not carrying out short circuit control thus.Even the 2nd comparator circuit detects difference, do not detect at the 1st comparator circuit under the situation of difference, because do not have potential difference (PD) between 2 lead-out terminals, so also do not have effect even carry out short circuit control between terminal, power consumption is less when not carrying out short circuit control thus.

Like this, do not detect under the situation of difference at the 1st or the 2nd comparator circuit, signal is judged in the output of logical and circuit, so that make control signal SD12, SE12 invalid.That is, former state is

closed output switch

71A, 71B, former state is opened short circuiting switch 81.

Timing adjusting circuit 51 is exported the judgement signal that logical circuit 41 generates as adjusting control signal SD12, SE12 regularly.Under the situation of carrying out short circuit control between terminal, timing adjusting circuit 51 at first input scan pulse signal P1 is determined the judgement of logical circuit 41, make control signal SD12 effectively

open output switch

71A, 71B then, make control signal SE12 effectively close short circuiting switch 81 then.

Reach equilibrium state through after the official hour, that is, the current potential of lead-out terminal 91,92 becomes roughly the same current potential.Therefore, be right after before beginning on the display panel to show, timing adjusting circuit 51 makes control signal SE12 invalid and open short circuiting switch 81, makes control signal SD12 invalid and

close output switch

71A, 71B then.

Output switch

71A, 71B and short circuiting switch 81 become common state, thereby lead-out terminal 91,92 is exported respectively and the corresponding voltage of pixel value of memory element 21,22.Regularly different by the control that makes control signal SD12, SE12 as mentioned above, and output can not enter any abnormality, thus between lead-out terminal, carry out short circuit control safely.

The electric power of additive decrementation is about the control electric power size that is used for switch control during short circuit control.After short circuit between lead-out terminal, when showing next line, the current potential of lead-out terminal 91,92 towards and lead-out terminal between the equidirectional that changes during short circuit further change.Therefore, by making the current potential equalization of lead-out terminal like this, can obtain with pre-charge or the identical effect of discharging in advance.Required 1/2 because of realizing that the potential change that needs with the corresponding current potential of value of pixel D11 is about under the common situation, so the heat that drives needed electric power of display panel and generation can be suppressed to about 1/2.

Next lead-out terminal 92,93 is carried out same control.Later also carry out same control for other 2 adjacent lead-out terminals.In addition, in each scanning impulse, carry out same operation repeatedly.Drive the electric power that display panel consumed by reducing as mentioned above.

Like this, by the display drive apparatus 100 of Fig. 1, according to 3 pixels, promptly 2 pixels in the previous row display pixel and with these 2 pixels in any one belong to 1 pixel of same row, can judge effectively whether the short circuit between lead-out terminal effective.Need between pixel, not be worth regular property.

Under the situation of Fig. 3 (b), the 2nd comparator circuit of logical circuit 41 relatively belongs to the value (being stored in respectively in memory element 32 and the memory element 22) of the pixel D22 and the pixel D12 of same row, and exports its comparative result.(combination G22) is all corresponding with lead-out terminal 92 for these 2 pixels.Others are identical with the situation of Fig. 3 (a).

In addition, also can not wait for load judgment circuit 40 between terminal logical circuit 41,42 ... judge, behind input scan signal P1, open at once all

output switch

71A, 71B, 72A ...Under this situation, if judgements such as logical circuit 41 should be carried out short circuit between a pair of corresponding lead-out terminal, then close corresponding short circuiting switch 81 etc., between terminal, to set up short circuit, and, then close corresponding output switch 71A etc. for being judged as pair of output that need not to set up short circuit.

In view of the above, because during between terminal, judging in the load judgment circuit 40, output switch concurrent working, longer during with the current potential equalization so can guarantee in short circuit between lead-out terminal.

In addition, for example also can be by the output switch 71B, the 72A that replace being connected to according to the logic of obtaining control signal SD12 and control signal SD23 and the output switch that carries out work on the same lead-out terminal 92.

In addition, in the situation of Fig. 3 (a), Fig. 3 (b), the 1st comparator circuit of logical circuit 41 also can not compare the value of pixel D21 and the value of pixel D22, and the value of the value of compared pixels D11 and pixel D12.

Fig. 4 (a) is the synoptic diagram that the 2nd example of the combination of pixels that load judgment circuit 40 adopts in judgement between the terminal of Fig. 1 is shown.Fig. 4 (b) is the synoptic diagram that the variation of Fig. 4 (a) is shown.For simply, control about the lead-out terminal 91,92 of Fig. 2 only is described at this.

The 1st comparator circuit of logical circuit 41 relatively belongs to the value (the combination G11 of Fig. 4 (a)) of the pixel D21 and the pixel D22 of same display line.The comparative result whether value of these 2 pixels of the 1st comparator circuit output expression is consistent.The 2nd comparator circuit relatively belongs to the value (combination G31) of the pixel D21 and the pixel D12 of different display lines and different display columns.The comparative result whether value of these 2 pixels of the 2nd comparator circuit output expression is consistent.Represent that at the comparative result of the 1st comparator circuit comparative result inconsistent and the 2nd comparator circuit represents under the consistent situation, the logical and circuit judges is for to set up short circuit at lead-out

terminal

91 and 92 of lead-out terminals, and output judges that signal is to carry out short circuit control.

Under the situation of Fig. 4 (b), the 2nd comparator circuit of logical circuit 41 relatively belongs to the value of the pixel D11 and the pixel D22 of different display lines and different lines, to export its comparative result (combination G32).Others are identical with the situation of Fig. 4 (a).

In addition, in the situation of Fig. 4 (a) and Fig. 4 (b), the 1st comparator circuit of logical circuit 41 also can not compare the value of pixel D21 and the value of pixel D22, and the value of the value of compared pixels D11 and pixel D12.

Fig. 5 (a) is the synoptic diagram that the 3rd example of the combination of pixels that load judgment circuit 40 is adopted in judgement between the terminal of Fig. 1 is shown.Fig. 5 (b) is the synoptic diagram that the variation of Fig. 5 (a) is shown.For simply, control about the lead-out terminal 91,92 of Fig. 2 only is described at this.

The 1st comparator circuit of logical circuit 41 relatively belongs to the value (the combination G31 of Fig. 5 (a)) of the pixel D21 and the pixel D12 of different display lines and different display columns.The comparative result whether value of these 2 pixels of the 1st comparator circuit output expression is consistent.The 2nd comparator circuit relatively belongs to the value (combination G22) of the pixel D22 and the pixel D12 of same display column.The comparative result whether value of these 2 pixels of the 2nd comparator circuit output expression is consistent.Represent that at the comparative result of the 1st comparator circuit the comparative result of unanimity and the 2nd comparator circuit represents under the inconsistent situation, the logical and circuit judges is for to set up short circuit at lead-out

terminal

Under the situation of Fig. 5 (b), the 1st comparator circuit of logical circuit 41 relatively belongs to the value of the pixel D11 and the pixel D22 of different display lines and different lines, exports its comparative result (combination D32).The 2nd comparator circuit of logical circuit 41 relatively belongs to the value of the pixel D21 and the pixel D11 of same row, exports its comparative result (combination G21).Others are identical with the situation of Fig. 5 (a).

With reference to Fig. 6 (a)～Fig. 9 (b), illustrate according to comprising 2 pixels in the previous row display pixel and belonging to 4 pixels of 2 pixels of the next line of same row, the judgement that load judgment circuit 40 is carried out between the terminal of Fig. 1 respectively with these 2 pixels.For simply, the control about the lead-out terminal 91,92 of Fig. 2 only is described.Also identical for other lead-out terminal.Logical circuit 41 grades all comprise the 1st, the 2nd and the 3rd comparator circuit and logical and circuit.

Fig. 6 (a) is the synoptic diagram that the 4th example of the combination of pixels that load judgment circuit 40 adopts in judgement between the terminal of Fig. 1 is shown.Fig. 6 (b) is the synoptic diagram that the variation of Fig. 6 (a) is shown.The 1st comparator circuit of logical circuit 41 relatively belongs to the value (the combination G11 of Fig. 6 (a)) of the pixel D21 and the pixel D22 of same display line.The comparative result whether value of these 2 pixels of the 1st comparator circuit output expression is consistent.The 2nd comparator circuit relatively belongs to the value (combination G21) of the pixel D21 and the pixel D11 of same row.The comparative result whether value of these 2 pixels of the 2nd comparator circuit output expression is consistent.

The 3rd comparator circuit relatively belongs to the value (combination G22) of the pixel D22 and the pixel D12 of same row.The comparative result whether value of these 2 pixels of the 3rd comparator circuit output expression is consistent.Represent all under the inconsistent situation that at the comparative result of the 1st～the 3rd comparator circuit the logical and circuit judges is for to set up short circuit at lead-out

terminal

Under the situation of Fig. 6 (b), the 1st comparator circuit of logical circuit 41 relatively belongs to the value of the pixel D11 and the pixel D12 of same display line, exports its comparative result (combination D12).Others are identical with the situation of Fig. 6 (a).

Fig. 7 (a) is the synoptic diagram that the 5th example of the combination of pixels that load judgment circuit 40 adopts in judgement between the terminal of Fig. 1 is shown.Fig. 7 (b) is the synoptic diagram that the variation of Fig. 7 (a) is shown.The 1st comparator circuit of logical circuit 41 relatively belongs to the value (the combination G21 of Fig. 7 (a)) of the pixel D21 and the pixel D11 of same row.The comparative result whether value of these 2 pixels of the 1st comparator circuit output expression is consistent.The 2nd comparator circuit relatively belongs to the value (combination G11) of the pixel D21 and the pixel D22 of same display line.The comparative result whether value of these 2 pixels of the 2nd comparator circuit output expression is consistent.

The 3rd comparator circuit relatively belongs to the value (combination G12) of the pixel D11 and the pixel D12 of same display line.The comparative result whether value of these 2 pixels of the 3rd comparator circuit output expression is consistent.Represent all under the inconsistent situation that at the comparative result of the 1st～the 3rd comparator circuit the logical and circuit judges is for to set up short circuit at lead-out

terminal

Under the situation of Fig. 7 (b), the 1st comparator circuit of logical circuit 41 relatively belongs to the value of the pixel D22 and the pixel D12 of same row, exports its comparative result (combination G22).Others are identical with the situation of Fig. 7 (a).

Fig. 8 (a) is the synoptic diagram that the 6th example of the combination of pixels that load judgment circuit 40 adopts in judgement between the terminal of Fig. 1 is shown.Fig. 8 (b) is the synoptic diagram that the variation of Fig. 8 (a) is shown.The 1st comparator circuit of logical circuit 41 relatively belongs to the value (the combination G21 of Fig. 8 (a)) of the pixel D21 and the pixel D11 of same row.The comparative result whether value of these 2 pixels of the 1st comparator circuit output expression is consistent.The 2nd comparator circuit relatively belongs to the value (combination G31) of the pixel D21 and the pixel D12 of different display lines and different lines.The comparative result whether value of these 2 pixels of the 2nd comparator circuit output expression is consistent.

The 3rd comparator circuit relatively belongs to the value (combination G32) of the display pixel D11 and the pixel D22 of different display lines and different lines.The comparative result whether value of these 2 pixels of the 3rd comparator circuit output expression is consistent.Represent inconsistent at the comparative result of the 1st comparator circuit, and the comparative result of the 2nd and the 3rd comparator circuit is represented under the consistent situation, the logical and circuit judges is for to set up short circuit at lead-out

terminal

Under the situation of Fig. 8 (b), the 1st comparator circuit of logical circuit 41 relatively belongs to the value of the pixel D22 and the pixel D12 of same row, exports its comparative result (combination G22).Others are identical with the situation of Fig. 8 (a).

Fig. 9 (a) is the synoptic diagram that the 7th example of the combination of pixels that load judgment circuit 40 adopts in judgement between the terminal of Fig. 1 is shown.Fig. 9 (b) is the synoptic diagram that the variation of Fig. 9 (a) is shown.The 1st comparator circuit of logical circuit 41 relatively belongs to the value (the combination G11 of Fig. 9 (a)) of the pixel D21 and the pixel D22 of same display line.The comparative result whether value of these 2 pixels of the 1st comparator circuit output expression is consistent.For the 2nd and the 3rd comparator circuit, since identical with the situation of Fig. 8 (a), so omitted explanation.Represent inconsistent at the comparative result of the 1st comparator circuit, and the comparative result of the 2nd and the 3rd comparator circuit is represented under the consistent situation, the logical and circuit judges is for to set up short circuit at lead-out

terminal

Under the situation of Fig. 9 (b), the 1st comparator circuit of logical circuit 41 relatively belongs to the value of the pixel D11 and the pixel D12 of same display line, exports its comparative result (combination G12).Others are identical with the situation of Fig. 9 (a).

Under the situation of Fig. 4 (a)～Fig. 9 (b), logical circuit 42 grades are also carried out the judgement identical with logical circuit 41 to other lead-out terminal, export according to its result and judge that signal is to carry out short circuit control.

In addition, with 2 pixels in the previous row display pixel and with 4 pixels or 3 pixels that these 2 pixels belong to respectively in 2 pixels of next line of same row be object, can adopt among Fig. 3 (a)～Fig. 9 (b) does not have illustrated combination yet.

In addition, in view of simple circuit configuration and effective circuit area, the row CA, the CB that describe in Fig. 3 (a)～Fig. 9 (b) are adjacent row.But row CA, CB also can be non-conterminous row.That is, 2 row CA, CB are so long as no matter different row are that the row how to select can.Under this situation, and corresponding 2 lead-out terminals of 2 row selected between have short circuiting switch, control this short circuiting switch and be connected to output switch on these two lead-out terminals according to judged result.

In addition, carrying out 1 row pixel data when handling, load judgment circuit 40 can repeatedly not select 2 to classify as and judge with row at every turn between terminal, can repeatedly select 2 to classify as and judge with row at every turn yet.Under the situation that does not repeat to select,, between lead-out terminal, carry out short circuit control for per 2 lead-out terminals.Under the situation that repeats to select, load judgment circuit 40 not only adopts the pixel of row CA, CB to judge between terminal, also adopts other row (if being row CC) and the pixel of row CB to judge.Under this situation,,, and carry out

short circuit control

91,92 and 93 of 3 lead-out terminals so just not only 92 of lead-out terminal 91 and lead-out terminals if for example row CA, CB, CC is corresponding with the lead-out terminal 91,92,93 of Fig. 2 respectively.Perhaps, load judgment circuit 40 also can carry out short circuit control between terminal between more lead-out terminal.

Figure 10 is the mode chart of object lesson that the short circuiting switch work of Fig. 2 is shown.Figure 10 illustrates N and the capable pixel of N-1 and short circuiting switch 81～89,180～184.The pixel that the capable pixel of N will show after being, the capable pixel of N-1 are the previous row display pixels that has shown.White circle expression illumination (corresponding lead-out terminal output high level " H " signal), black this pixel of circle expression does not have illumination (corresponding lead-out terminal output low level " L " signal).

In Fig. 2, repeat to comprise same circuit.Short circuiting switch 84～89,180～184 is included between lead-out terminal in the on-off circuit 60, and is present in the below of the short circuiting switch 81～83 of Fig. 2.Here, load judgment circuit 40 adopts the combination of pixels shown in Fig. 3 (a) between terminal in judgement.

For example, for the left side the 1st row of Figure 10 and 4 pixels of the 2nd row, because the value difference of capable 2 pixels of N-1, and the value difference of 2 pixels of the 1st row, so logical circuit 41 output control signals, so that carry out short circuit control.Thereby short circuiting switch 81 is connected.For the 2nd row of Figure 10 and 4 pixels of the 3rd row, because the value difference of capable 2 pixels of N-1, and the value difference of 2 pixels of the 2nd row, so logical circuit 42 output control signals, so that carry out short circuit control.Equally because short circuiting switch 83 also connects, so and the corresponding lead-out terminal of the 1st～the 4th row pixel between with the current potential equalization.

Figure 11 is the block diagram of structure that the display drive apparatus variation of Fig. 1 is shown.The display drive apparatus of Figure 11 replaces between terminal on-off circuit 60 between load judgment circuit 40 and lead-out terminal, has between terminal on-off circuit 260 between load judgment circuit 240 and lead-out terminal, and this point is different with the display drive apparatus of Fig. 1 and Fig. 2.

Between terminal load judgment circuit 240 comprise logical circuit 241,242,243 ... with timing adjusting circuit 251,252,253 ...On-off circuit 260 is except having between lead-out terminal the element in the on-off circuit 60 between lead-out terminal, also have bridging line 8 be connected with bridging

line switch

81C, 82C, 83C ...

Bridging line connect

switch

81C, 82C, 83C ... respectively with lead-out terminal 91,92,93 ... corresponding, between the lead-out terminal of correspondence and bridging line 8, connect.For example can adopt transistor as bridging line connect

switch

81C, 82C, 83C ...Power circuit on bridging line 8, apply with " H " and " L " on a rough average voltage (power supply power vd D about 1/2nd voltage).

Logical circuit 241 and logical circuit 41 roughly the same ground structures, but different on this point below.If it is invalid (promptly that logical circuit 241 detects control signal SE12, do not close short circuiting switch 81) and with the lead-out terminal 91 corresponding row of pixel in the value of pixel change (promptly the value of the pixel D21 of row CA and pixel D11 is different in Fig. 3 (a) etc.), signal is judged in logical circuit 241 outputs, so that control signal SF12 is become effectively.Under the effective situation of control signal SF12, bridging line connection switch 81C sets up the short circuit between lead-out terminal 91 and the bridging line 8.Logical circuit 242,243 ... and timing adjusting circuit 252,253 ... also be except relevant control signal difference, work in the same manner.

In addition, power circuit also can apply voltage for bridging line 8.Under this situation, in the lead-out terminal chien shih current potential equalization that is connected on the bridging line 8.In addition, also can on the large value capacitor of the voltage of keeping supply voltage VDD about 1/2nd, connect bridging line 8.

Figure 12 is the timing waveform of the control signal of output from 2 timing adjusting circuits 251,252 of Figure 11.Timing adjusting circuit 251 is exported the judgement signal that logical circuit 241 generates as adjusting control signal SD12, SE12 regularly, SF12 (switch controlling signal SD).Be judged as 91,92 of lead-out terminals at logical circuit 241 and carry out under the situation of short circuit control, timing adjusting circuit 251 at first input scan pulse signal P1 is determined the judgement of logical circuit 241, makes control signal SD12 effectively (" L ") and

open output switch

71A, 71B then.Timing adjusting circuit 251 makes control signal SE12 effective (" H ") and closes short circuiting switch 81 then.Because control signal SF12 in statu quo invalid (" L ") opens so bridging line connects switch 81C former state.

Through behind the official hour, timing adjusting circuit 251 makes control signal SE12 invalid (" L ") and opens short circuiting switch 81, makes control signal SD12 invalid (" H ") then and closes

output switch

71A, 71B.

Timing adjusting circuit 252 is exported the judgement signal that logical circuit 242 generates as adjusting control signal SD23, SE23 regularly, SF23 (switch controlling signal SD).Be judged as not 92,93 of lead-out terminals at logical circuit 242 and carry out short circuit control (do not make control signal SE23 effective) and detecting under the situation that the value of pixel in the lead-out terminal 92 corresponding row with pixel changes, timing adjusting circuit 252 makes control signal SF23 effectively (" H ") after the timing that the level of the signal of control short circuiting switches such as control signal SE12, SE23 changes.So, close bridging line and connect switch 82C.Because control signal SE23 former state invalid (" L ") is so short circuiting switch 82 former states are closed.

Then, the current potential of lead-out terminal 92 becomes the current potential that is substantially equal to bridging line 8.Before the timing that the level of the signal of control such as control signal SE12, SE23 short circuiting switch changes, timing adjusting circuit 252 makes control signal SF23 invalid (" L ") and opens bridging line connection switch 82C.So just make control that bridging line connects

switch

81C, 82C etc. regularly different with

short circuiting switch

81,82 etc.

Figure 13 is the mode chart that the 1st concrete example of the short circuiting switch of Figure 11 and the work that bridging line connects switch is shown.Figure 13 illustrates the capable pixel of N and N-1, short circuiting switch 81～89,180～184 and be connected switch 81C～89C, 180C～184C with bridging line.In Figure 11, repeat to comprise same circuit.Bridging line connects switch 84C～89C, 180C～184C and is included between lead-out terminal in the on-off circuit 260, and the bridging line that is present in Figure 11 connects the below of switch 81C～83C.In Figure 13～Figure 15, load judgment circuit 240 adopts the combination of pixels shown in Fig. 6 (a) between terminal in judgement.

Under the situation of Figure 13, though for any 2 row neighbors, all not short circuits between the terminal of correspondence for the capable pixel of the N-1 row different with the value of the capable pixel of N, are closed corresponding bridging line and are connected switch.That is, bridging line connects

switch

84C, 85C, 86C, 180C, 181C, 182C connection.Thereby, in pixel arrangement as shown in Figure 13, though the display drive apparatus of Fig. 2 can not make the current potential equalization of lead-out terminal, by the display drive apparatus of Figure 11, the current potential of the lead-out terminal that current potential changed when next line was shown is roughly VDD/2.

Figure 14 is the mode chart that the 2nd concrete example of the short circuiting switch of Figure 11 and the work that bridging line connects switch is shown.Voxel model is different with Figure 13 in Figure 14.Under this situation,, connect

switch

81C, 82C etc. but also close bridging line, so can make the current potential of more lead-out terminal be roughly VDD/2 because not only close

short circuiting switch

83,86,89,182.

Figure 15 is the mode chart that the 3rd concrete example of the short circuiting switch of Figure 11 and the work that bridging line connects switch is shown.Under this situation, not only close

short circuiting switch

81,82 etc., also close bridging line and connect

switch

84C, 180C.

Figure 16 is the mode chart that the 4th concrete example of the short circuiting switch of Figure 11 and the work that bridging line connects switch is shown.Here, load judgment circuit 240 adopts the combination of pixels shown in Fig. 3 (a) between short circuit when judging.Under this situation, not only close short circuiting switch 86,182, also close bridging line and connect

switch

84C, 85C etc.Like this, by the display drive apparatus of Figure 11, contiguous pixels has under the situation of identical value in 1 row, especially produces effect.

In the display drive apparatus of Figure 11,, can carry out switch control by fairly simple circuit because connect switch according to 2 row controls of pixel corresponding short circuiting switch and bridging line.But, should also can not close for example bridging line connection switch 84C of Figure 14, because if only close short circuiting switch 83, the current potential between terminal has just averaged out.Equally, also there is no need to close the bridging line that bridging line connects

switch

87C, 180C, 183C and Figure 15 and be connected switch 84C, 180C.Now the device of not closing the bridging line connection switch that need not to close is described.

Figure 17 is the block diagram of structure that the display drive apparatus variation of Figure 11 is shown.The display drive apparatus of Figure 17 except the element of the display drive apparatus that is included in Figure 11, also comprise AND

gate

52D, 53D ..., each bridging line connects switch and is controlled by the output of the AND gate of correspondence.In Figure 17, omitted components identical with Figure 11.

Be that " L " and control signal SF23 are under the situation of " H " at control signal SE12 only, AND gate 52D makes control signal SG23 export for " H ".Bridging line connects switch 82C and only closes when control signal SG23 is " H ".That is, can only under the situation of not closing short circuiting switch 81, close bridging line and connect switch 82C.AND gate 53D ... also according to the control signal of correspondence similarly control bridging line connect switch 82C ...So, do not close the bridging line connection switch 84C of Figure 14 and the bridging line of Figure 15 and be connected switch 84C etc., can carry out better control.

Figure 18 is the block diagram of structure of other variation that the display drive apparatus of Fig. 1 is shown.The display drive apparatus of Figure 18 also comprises data timing adjusting circuit 202 and control timing adjusting circuit 204 except the element of the display drive apparatus 100 that comprises Fig. 1.

Data timing adjusting circuit 202 is adjusted timing from the pixel data D1 of the 1st memory circuit 20 outputs adjusted pixel data is outputed to on-off circuit 60 between lead-out terminal.Control timing adjusting circuit 204 is adjusted timing from the switch controlling signal SD of 40 outputs of load judgment circuit between terminal adjusted signal is outputed to on-off circuit 60 between lead-out terminal.

Here, in order to be applied between lead-out terminal on the on-off circuit 60 at switch controlling signal SD after, pixel data D1 is applied between terminal on the on-off circuit 60, data timing adjusting circuit 202 and control timing adjusting circuit 204 are adjusted regularly.In view of the above, can just before the display line conversion, between lead-out terminal, carry out short circuit control really.

In addition, display drive apparatus also can only comprise one of them of data timing adjusting circuit 202 and control timing adjusting circuit 204.

Figure 19 (a) illustrates the structure of the modular assembly of the display drive apparatus that has adopted Fig. 1.Figure 19 (b) illustrates the structure of the display module of the modular assembly that has adopted Figure 19 (a).

The modular assembly 120 of Figure 19 (a) comprises display drive apparatus 100, flexible wiring board 122, input signal terminal portion 124 and output signal terminal portion 126.The signal that flexible wiring board 122 will be applied in the input signal terminal portion 124 is sent to display drive apparatus 100, and the output of display drive apparatus 100 is sent to output signal terminal portion 126.

The display module of Figure 19 (b) comprises PDP 112, shared wiring plate 114, panel LSI 116 and a plurality of modular assembly 120 as display panel.PDP 112 comprise a plurality of pixels and with the corresponding data electrode of each pixel.In addition, PDP 112 has a plurality of block of pixels, and each modular assembly 120 is corresponding with each block of pixels.

Panel LSI 116 has the circuit that carries out signal Processing control, and in order to control the demonstration of PDP 112, the control signal of the modular assembly that panel LSI 116 is to be driven with picture signal, display control signal, expression etc. outputs on the shared wiring plate 114.Shared wiring plate 114 comprises the signal wire of the signal that transmission is exported from panel LSI 116.The input signal terminal portion 124 of each modular assembly 120 is electrically connected with shared wiring plate 114, and output signal terminal portion 126 is electrically connected with PDP 112.The picture signal that applies output from panel LSI 116 on display drive apparatus 100 is as pixel data D0.The output of display drive apparatus 100 is applied on the data electrode of PDP 112.

Like this, because in the display module of Figure 19 (b), adopted a plurality of modular assemblies 120, can drive the PDP of big picture.In addition, because each modular assembly 120 adopts display drive apparatus 100, so can subdue power consumption.

In addition, among Figure 19 (a), Figure 19 (b), replace the display drive apparatus 100 of Fig. 1, also can adopt the display drive apparatus of Figure 11, Figure 17 or Figure 18.

Figure 20 is the block diagram that the television receiver structure example of the display module that has adopted Figure 19 (b) is shown.The television receiver of Figure 20 comprises: signal Processing LSI602, the image quality LSI 604, LVDS sending part 606 and the panel block 610 that are used to obtain and handle picture signal VS.Panel block 610 comprises LVDS acceptance division 612, discharge control part 614, scanner driver 616, secondary CPU 608, display module 620, power MOSFET 632 and keeps driver 634.

Display module 620 is display modules of Figure 19 (b), comprises PDP 112, panel LSI116 and data driver 624.Data driver 624 is equivalent to a plurality of display drive apparatus 100 shown in Figure 19 (b).

Like this, display drive apparatus of the present invention can easily be assembled in image display systems such as the television receiver assembling of having adopted display panels such as PDP.Power consumption when the television reception function of Figure 20 reduces display driver greatly, the heat that produces in the time of also can reducing display driver simultaneously.

In addition, in the above embodiments, illustrated and adopted the situation of PDP, but so long as have the display panel of capacity load, also can adopt such as other display panels such as EL (electroluminescence) panels as display panel.

As above illustrated, because the present invention can suppress power consumption, can also suppress heating, so the display panel that has such as capacity loads such as PDP and EL panels for driving is useful.

Claims

1. display drive apparatus comprises:

The 1st memory circuit, the 1 row pixel that is used to store composing images;

The 2nd memory circuit is used for storing the 1 row pixel that was right after before the 1 row pixel that described the 1st memory circuit is stored;

On-off circuit between lead-out terminal is used for and will all outputs to respectively and the corresponding a plurality of lead-out terminals of pixel with the corresponding voltage of the value of the pixel that is stored in described the 1st memory circuit; And

Load judgment circuit between terminal, be used for per 2 row to selecting from the pixel that constitutes described image, value according at least 3 pixels in 4 pixels pixel of storing in the described the 1st or the 2nd memory circuit, that belong to the 1st and the 2nd row that are listed as 2 of described selection, judge whether in described a plurality of lead-out terminals, to set up short circuit respectively and between corresponding 2 lead-out terminals of the described the 1st and the 2nd row

Under situation of short circuit is set up in judgement, will be stored in before the corresponding voltage of value of pixel in described the 1st memory circuit, that belong to the described the 1st and the 2nd row outputs to described 2 lead-out terminals, on-off circuit is temporarily set up short circuit between described lead-out terminal between described 2 lead-out terminals.

2. display drive apparatus according to claim 1 is characterized in that, for per 2 row of described selection, on-off circuit has the short circuiting switch that can independently control that is used for setting up short circuit between described 2 lead-out terminals between described lead-out terminal.

3. display drive apparatus according to claim 2, it is characterized in that, on-off circuit also has a plurality of output switches between described lead-out terminal, and whether each described output switch control exports the corresponding voltage of value with described pixel between lead-out terminal that is connected with described short circuiting switch and described the 1st memory circuit.

4. display drive apparatus according to claim 3 is characterized in that, between described terminal the load judgment circuit will control each described short circuiting switch signal and control each described output switch signal export as switch controlling signal.

5. display drive apparatus according to claim 4, it is characterized in that, the load judgment circuit is under situation of short circuit is set up in judgement between described terminal, export described switch controlling signal, thereby be connected to the scanning pulse signal of the display panel on described a plurality of lead-out terminal from reception, in during till on described display panel, begin to show, described short circuiting switch between described 2 lead-out terminals cuts out, and the described output switch on each that is connected in described 2 lead-out terminals was opened before described short circuiting switch cuts out.

6. display drive apparatus according to claim 4, it is characterized in that, the load judgment circuit is exported described switch controlling signal between described terminal, thereby before judging whether to set up short circuit, makes the described output switch opens on each that is connected in described 2 lead-out terminals.

7. display drive apparatus according to claim 1 is characterized in that, the described the 1st and the 2nd row are adjacent row.

8. display drive apparatus according to claim 1 is characterized in that, the described the 1st and the 2nd row are to allow 2 row repeatedly selected from the row of the pixel that constitutes described image.

9. display drive apparatus according to claim 1 is characterized in that, the described the 1st and the 2nd row are 2 row of repeatedly not selecting from the row of the pixel that constitutes described image.

10. display drive apparatus according to claim 1 is characterized in that, also comprises:

Bridging line; And

A plurality of bridging lines connect switches, are connected between each and the described bridging line of the described lead-out terminal that connects described short circuiting switch,

Short circuit is not set up in the on-off circuit judgement between described lead-out terminal, and belong to described the 1st row and be stored in the value of the pixel in described the 2nd memory circuit and belong to described the 1st row and be stored under the different situation of the value of the pixel in described the 1st memory circuit, control with the described the 1st bridging line that is listed as between corresponding lead-out terminal and the described bridging line and be connected switch so that it is closed.

11. display drive apparatus according to claim 10 is characterized in that, is applying the high level voltage that applies on described a plurality of lead-out terminal and the average voltage of low level voltage on the described bridging line.

12. display drive apparatus according to claim 10, it is characterized in that, and described the 1st corresponding lead-out terminal of row and and the lead-out terminal of described the 2nd row outside the corresponding lead-out terminal between set up under the situation of short circuit, on-off circuit is controlled with the corresponding lead-out terminal of described the 1st row and is connected switch so that it is not closed with bridging line between described bridging line between described lead-out terminal.

13. display drive apparatus according to claim 1, it is characterized in that, between described the 1st memory circuit and described lead-out terminal between the on-off circuit, and at least one between the on-off circuit between load judgment circuit and described lead-out terminal between described terminal, also comprise and adjusting and the timing adjusting circuit of the timing of output signal.

14. display drive apparatus according to claim 1 is characterized in that,

Be stored in the value of 2 pixels in described the 2nd memory circuit between described terminal in more described 4 pixels of load judgment circuit, obtain the 1st comparative result, the value that belongs to 2 pixels of described the 1st row in more described 4 pixels, obtain the 2nd comparative result, all represent at the described the 1st and the 2nd comparative result to be judged as between described 2 lead-out terminals and not set up short circuit under the inconsistent situation of value of comparison.

15. display drive apparatus according to claim 1 is characterized in that,

Be stored in the value of 2 pixels in described the 2nd memory circuit between described terminal in more described 4 pixels of load judgment circuit, obtain the 1st comparative result, relatively belong to described the 1st row and be stored in the value of the pixel in described the 2nd memory circuit and belong to described the 2nd row and be stored in the value of the pixel in described the 1st memory circuit, obtain the 2nd comparative result, represent at inconsistent and described the 2nd comparative result of the value that described the 1st comparative result is represented comparison to be judged as between described 2 lead-out terminals and to set up short circuit under the situation of value unanimity of comparison.

16. display drive apparatus according to claim 1 is characterized in that,

The load judgment circuit relatively belongs to described the 1st row and is stored in the value of the pixel in described the 2nd memory circuit and belongs to described the 2nd row and be stored in the value of the pixel in described the 1st memory circuit between described terminal, obtain the 1st comparative result, the value that belongs to 2 pixels of described the 2nd row in more described 4 pixels, obtain the 2nd comparative result, represent to be judged as between described 2 lead-out terminals and to set up short circuit under the value unanimity of comparison and the inconsistent situation of value that described the 2nd comparative result is represented comparison at described the 1st comparative result.

17. display drive apparatus according to claim 1 is characterized in that,

Be stored in the described the 1st and the 2nd memory circuit value of 2 pixels in any one between described terminal in more described 4 pixels of load judgment circuit, obtain the 1st comparative result, the value that belongs to 2 pixels of described the 1st row in more described 4 pixels, obtain the 2nd comparative result, the value that belongs to 2 pixels of described the 2nd row in more described 4 pixels, obtain the 3rd comparative result, all represent at described the 1st～the 3rd comparative result to be judged as between described 2 lead-out terminals and to set up short circuit under the inconsistent situation of value of comparison.

18. display drive apparatus according to claim 1 is characterized in that,

The value that belongs to 2 pixels of described the 1st row between described terminal in more described 4 pixels of load judgment circuit, obtain the 1st comparative result, be stored in the value of 2 pixels in described the 1st memory circuit in more described 4 pixels, obtain the 2nd comparative result, be stored in the value of 2 pixels in described the 2nd memory circuit in more described 4 pixels, obtain the 3rd comparative result, all represent at described the 1st～the 3rd comparative result to be judged as between described 2 lead-out terminals and to set up short circuit under the inconsistent situation of value of comparison.

19. display drive apparatus according to claim 1 is characterized in that,

The value that belongs to 2 pixels of described the 1st row between described terminal in more described 4 pixels of load judgment circuit, obtain the 1st comparative result, relatively belong to described the 1st row and be stored in the value of the pixel in described the 2nd memory circuit and belong to described the 2nd row and be stored in the value of the pixel in described the 1st memory circuit, obtain the 2nd comparative result, relatively belong to described the 2nd row and be stored in the value of the pixel in described the 2nd memory circuit and belong to described the 1st row and be stored in the value of the pixel in described the 1st memory circuit, obtain the 3rd comparative result, inconsistent in the value that described the 1st comparative result is represented comparison, and the described the 2nd and the 3rd comparative result is represented to be judged as between described 2 lead-out terminals and to set up short circuit under the situation of value unanimity of comparison.

20. display drive apparatus according to claim 1 is characterized in that,

Be stored in the described the 1st and the 2nd memory circuit value of 2 pixels in any one between described terminal in more described 4 pixels of load judgment circuit, obtain the 1st comparative result, relatively belong to described the 1st row and be stored in the value of the pixel in described the 2nd memory circuit and belong to described the 2nd row and be stored in the value of the pixel in described the 1st memory circuit, obtain the 2nd comparative result, relatively belong to described the 2nd row and be stored in the value of the pixel in described the 2nd memory circuit and belong to described the 1st row and be stored in the value of the pixel in described the 1st memory circuit, obtain the 3rd comparative result, inconsistent in the value that described the 1st comparative result is represented comparison, and the described the 2nd and the 3rd comparative result is represented to be judged as between described 2 lead-out terminals and to set up short circuit under the situation of value unanimity of comparison.

21. a display module comprises:

Display panel with a plurality of block of pixels; And

Drive a plurality of display drive apparatus of each block of pixels of described display panel respectively; ,

Wherein said display drive apparatus has respectively:

The 1st memory circuit, the 1 row pixel that is used to store composing images;

Load judgment circuit between terminal, be used for per 2 row to selecting from the pixel that constitutes described image, according to the pixel of storing in the described the 1st or the 2nd memory circuit, the value that belongs at least 3 pixels in the 1st and the 2nd 4 pixels that are listed as that are listed as 2 of described selection, judge whether in described a plurality of lead-out terminals, to set up short circuit respectively and between corresponding 2 lead-out terminals of the described the 1st and the 2nd row, under situation of short circuit is set up in judgement, will be stored in described the 1st memory circuit, the corresponding voltage of value that belongs to the pixel of the described the 1st and the 2nd row outputs to before described 2 lead-out terminals, and on-off circuit is temporarily set up short circuit between described lead-out terminal between described 2 lead-out terminals.