CN101221492B - Floating point exception handling device and method for handling exception using the same - Google Patents
Floating point exception handling device and method for handling exception using the same Download PDFInfo
- Publication number
- CN101221492B CN101221492B CN2008100173607A CN200810017360A CN101221492B CN 101221492 B CN101221492 B CN 101221492B CN 2008100173607 A CN2008100173607 A CN 2008100173607A CN 200810017360 A CN200810017360 A CN 200810017360A CN 101221492 B CN101221492 B CN 101221492B
- Authority
- CN
- China
- Prior art keywords
- floating
- point
- exception
- instruction
- micro
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
Images
Abstract
The present invention discloses a floating point exception handling device and an exception handling method using the device. The device of the present invention comprises a floating point control register, a floating point exception register, a floating point interrupt control circuit and a floating point interrupt generating circuit. The device is characterized in that: the device also comprises a non-shielding exception generating circuit and a floating point field register; the floating point interrupt control circuit is a microprogram RAM. The method of the present invention comprises the following steps that: microinstructions in the microprogram RAM are executed after initialization; a first microinstruction detects whether a floating point coprocessor is idle or not; a second microinstruction detects whether non-shielding exception exists or not; if non-shielding exception exists, interrupt is triggered; if non-shielding exception does not exist, subsequent microinstructions are executed and a floating point unit is started; exception occurring can be stored during operation; an instruction field is recorded when the last microinstruction is executed. As the floating point interrupt control circuit of the present invention is replaced with the alterable microprogram RAM which is simple in structure, once a design error occurs, the error can be corrected even after the tape-out of chips.
Description
Technical field
The present invention relates to a kind of floating-point exception treating apparatus, also relate to and utilize this device to carry out the method for abnormality processing.
Background technology
Document " patent No. is 6826682 United States Patent (USP) " discloses a kind of floating-point exception detection method, and this method is at first taked a process, and this process can be added the special instruction that is used to test floating-point exception in instruction sequence of carrying out of trend.Secondly in the execution of this instruction sequence, come handling unusually by instruction sequence being reset to a known correct status.Be that a formation is carried out separately according to each single instruction at last.This method can realize the detection of floating-point exception, but owing to need add special instruction to normal instruction sequence, the decoding of special instruction and execution have consumed a large amount of processor time, and extra time, expense was very bigger.
Document " patent No. is 5257214 United States Patent (USP) " discloses a kind of abnormality detection trigger mechanism of self-timing.Trigger logic by non-edge, this invention obtains abnormal information with little time-delay.But should trigger effectively filtering of logic, so poor anti jamming capability of system, there is a little burr to occur all being considered to unusual because of external disturbance in the ifs circuit, in addition under the situation of floating point instruction and fixed point executing instructions, this mode needs a large amount of memory access cost of cost owing to need preservation fixed point scene to come floating-point exception is handled.
Document " patent No. is 5410657 United States Patent (USP) " discloses a kind of abnormality detection disposal route.When the floating point instruction computing, the fixed point unit is the effective instruction in the executive routine no longer, but carry out " dummy instruction " that produces by system, this dummy instruction is without any valid function, just when launching, floating point instruction returns the address of this floating point instruction, if this floating point instruction produces unusually like this, system just can accurately locate and distinguish is the floating-point exception that floating point instruction produces.This method can effectively be distinguished unusual between floating point instruction, but the term of execution of floating point instruction, the fixed point instruction needs to carry out a dummy instruction that is specifically designed to report floating point instruction address, the fixed point instruction that is equivalent to program is stagnated fully, become a kind of order between floating-point and the fixed point instruction and carry out relation, had a strong impact on instruction degree of parallelism (ILP).The present invention is provided with the special on-the-spot floating-point context register of preserving, and can accurately locate by hardware unusual floating point instruction takes place, and can guarantee the executed in parallel of floating point instruction and fixed point instruction fully.
With reference to Fig. 5, known floating-point exception treating apparatus comprises that floating-point control register, floating-point exception register, floating-point interrupt control circuit and floating-point interrupt producing circuit, the floating-point control register is used to preserve control on Abnormal information, the floating-point exception register is used to preserve the floating-point exception that has taken place, the floating-point interrupt control circuit interrupts producing circuit according to floating-point exception and control register content control floating-point, whether triggers interruption with decision.If certain class floating-point exception takes place, and such floating-point exception is not shielded in the control register, this device just allows to trigger to interrupt.There is following problem in this device: in a single day floating-point interrupt control circuit more complicated, and the mistake that designs, just can't correct.
Summary of the invention
In order to overcome the deficiency that the prior art floating-point exception is handled floating-point interrupt control circuit design complexity in cost height and the floating-point exception treating apparatus, made a mistake and can not correct, the invention provides a kind of floating-point exception treating apparatus, the floating-point interrupt control circuit is replaced with a rewritable microprogram RAM, this microprogram RAM simple structure, and the mistake that in a single day designs, even after the chip flow, also can correct.
The present invention also provides and utilizes this device to carry out the method for abnormality processing.In carrying out floating point instruction, abnormal information is stored in the floating-point exception register, and the instruction scene is stored in the floating-point context register.Article one, floating point instruction is finished, and begins carrying out the second floating point instruction, and whether at first detect article one floating point instruction has unusual generation, if unusual generation is arranged, then floating-point exception detects micro-order and triggers an aborted, and quotes interrupt vector number; Otherwise do not produce interruption.
The technical solution adopted for the present invention to solve the technical problems: a kind of floating-point exception treating apparatus, comprise the floating-point control register, the floating-point exception register, floating-point interrupt control circuit and floating-point interrupt producing circuit, be characterized in also comprising that non-shielding produces circuit and floating-point context register unusually, described floating-point interrupt control circuit is microprogram RAM, the user writes the floating-point control information in the floating-point control register, processor is carried out floating point instruction, in the implementation, being kept at unusually in the floating-point exception register of floating point instruction, floating point instruction address and data address are stored in the floating-point context register, the control abnormity instruction; The content of floating-point control register and floating-point exception register is input to non-shielding and produces circuit unusually, judged whether that non-shielding is unusual, and the result is input to floating-point interrupt produces circuit, simultaneously corresponding micro-order also is input to floating-point and interrupts producing circuit, control interrupt request singal or interrupt vector.
A kind of method of utilizing said apparatus to carry out abnormality processing is characterized in may further comprise the steps:
(a) content of floating-point control register is initialized to 1111111b, the wherein unusual conductively-closed of 1 expression; The content of floating-point exception register is initialized to 0000000b, and wherein 0 expression is not unusual takes place;
(b) read and carry out article one micro-order in this instruction microprogram from microprogram RAM, promptly floating-point is finished the detection micro-order;
(c) from microprogram RAM, read and carry out second micro-order in this instruction microprogram, be that floating-point exception detects micro-order, this micro-order control floating-point interrupts producing circuit non-shielding is judged unusually, if there is non-shielding unusual, this circuit sends an interrupt request to processor, if there is not non-shielding unusually then do not send;
(d) start floating-point coprocessor, when floating-point exception took place, the floating-point exception register carried out record;
(e) carry out the last item micro-order, the floating-point microprogram is finished micro-order, and the floating-point context register is preserved current instruction scene of carrying out after receiving this micro-order;
(f) floating-point is finished the micro-order detection, forwards step (b) to, and is complete up to program.
The invention has the beneficial effects as follows: because floating-point interrupt control circuit of the present invention is replaced with a rewritable microprogram RAM, this microprogram RAM simple structure, can programme to the triggering mode of aborted, and the mistake that in a single day designs, even after the chip flow, also can correct; The floating-point exception of comparing software detects, processing mode, and processing cost of the present invention is very little.
Below in conjunction with drawings and Examples the present invention is elaborated.
Description of drawings
Fig. 1 is the structured flowchart of floating-point exception treating apparatus of the present invention.
Fig. 2 is the further explanatory drawings of floating-point exception register and floating-point control register among Fig. 1.
Fig. 3 is the further explanatory drawings of microprogram among Fig. 1.
Fig. 4 is the further explanatory drawings that floating-point interrupts producing circuit among Fig. 1.
Fig. 5 is known floating-point exception treating apparatus
Embodiment
With reference to Fig. 1～4, the present invention is at the textural devices at full hardware floating-point exception treating apparatus that has adopted microprogram to add hardwired, whole device produces circuit unusually by floating-point exception register, floating-point control register, non-shielding, the floating-point context register, microprogram RAM, floating-point interrupts producing circuit four most of compositions, microprogram RAM has substituted the floating-point interrupt control circuit, the floating-point exception register holds now with existing different floating-point exceptions, the floating-point control register is used for control and whether shields that certain is unusual, and non-shielding produces circuit unusually and generates non-shielding abnormal signal; The floating-point context register is preserved the program address pointer and the data address pointer of the floating point instruction that each bar carrying out; Microprogram RAM preserves the microprogram of different floating point instructions, and each microprogram is finished the detection micro-order by floating-point, and floating-point exception detects micro-order, and other micro-orders and floating-point are finished micro-order and formed according to the order of sequence; It is hardwired that floating-point interrupts producing circuit, at first import non-shielding unusually and the micro-order of carrying out, if it is unusual that non-shielding has taken place, and the micro-order of carrying out is that floating-point exception detects micro-order, and then this circuit can trigger floating-point and interrupts producing circuit and send floating point unit aborted signal and interrupt vector number to processor.
The information flow direction of entire circuit is: the user writes the floating-point control information in control register, processor begins to carry out floating point instruction then, in commission, being kept at unusually in the floating-point exception register of floating point instruction, floating point instruction address and data address are stored in the floating-point context register.The content of floating-point control register and floating-point exception register is input to non-shielding and produces circuit unusually, whether this circuit judges has non-shielding unusual, and the result is input to floating-point interrupt produces circuit, whether simultaneously corresponding micro-order also is input to floating-point and interrupts producing circuit, control this circuit and will interrupt to the processor generation.
The floating-point exception treating apparatus carries out the method for abnormality processing, and is specific as follows:
(1) start.
(2) initialization.The content of floating-point control register is initialized to 1111111b, wherein 1 this unusual conductively-closed of expression; The content of floating-point exception register is initialized to 0000000b, the wherein unusual generation of this kind of 0 expression.
(3) carry out floating point instruction.What at first read and carry out from microprogram RAM is article one micro-order in this instruction microprogram: floating-point is finished the detection micro-order.
(4) read and carry out second micro-order in this instruction microprogram from microprogram RAM: floating-point exception detects micro-order, this micro-order control floating-point interrupts producing circuit non-shielding is judged unusually, if there is non-shielding unusual, this circuit sends a unusual request to processor, if there is not non-shielding unusually then do not send.
(5) micro-order of execution back starts floating-point coprocessor and starts working.If coprocessor generation floating-point exception in the computing, the floating-point exception register can carry out record.
(6) carry out the last item micro-order: the floating-point microprogram is finished micro-order.The floating-point context register is preserved current instruction scene of carrying out after receiving this micro-order.
(7) forwarded for (3) step to.
From carrying out on the flow process, this device has following characteristics: at first whole unusual on-the-spot preservation, aborted generate all and are controlled by microprogram, and microprogram can change by rewriteeing RAM, and whole execution flow process can become very flexible.Secondly the execution of microprogram and the execution of floating-point coprocessor are independently, after processor starts floating-point coprocessor by microprogram, can carry out the micro-order of other fixed point instruction, thereby can executed in parallel floating point instruction and fixed point instruction.What the floating-point microprogram in other (6) step finished that micro-order represents is that the floating-point microprogram is finished, do not represent that floating point instruction is finished, floating-point coprocessor may also move, therefore all need to be provided with the test floating-point in the beginning of every instruction microprogram and finish the detection micro-order, this micro-order guarantees that last floating point instruction judges just whether last floating point instruction has unusual generation after being finished, and guaranteed the correctness of judging.
Claims (3)
1. floating-point exception treating apparatus, comprise the floating-point control register, the floating-point exception register, floating-point interrupt control circuit and floating-point interrupt producing circuit, it is characterized in that: comprise that also non-shielding produces circuit and floating-point context register unusually, described floating-point interrupt control circuit is microprogram RAM, the user writes the floating-point control information in the floating-point control register, processor is carried out floating point instruction, in the implementation, being kept at unusually in the floating-point exception register of floating point instruction, floating point instruction address and data address are stored in the floating-point context register, the control abnormity instruction; The content of floating-point control register and floating-point exception register is input to non-shielding and produces circuit unusually, judged whether that non-shielding is unusual, and the result is input to floating-point interrupt produces circuit, simultaneously corresponding micro-order also is input to floating-point and interrupts producing circuit, control interrupt request singal or interrupt vector.
2. a method of utilizing the described floating-point exception treating apparatus of claim 1 to carry out abnormality processing is characterized in that comprising the steps:
(a) content of floating-point control register is initialized to 1111111b, the wherein unusual conductively-closed of 1 expression; The content of floating-point exception register is initialized to 0000000b, and wherein 0 expression is not unusual takes place;
(b) read and carry out article one micro-order in this instruction microprogram from microprogram RAM, promptly floating-point is finished the detection micro-order;
(c) from microprogram RAM, read and carry out second micro-order in this instruction microprogram, be that floating-point exception detects micro-order, this micro-order control floating-point interrupts producing circuit non-shielding is judged unusually, if there is non-shielding unusual, this circuit sends an interrupt request to processor, if there is not non-shielding unusually then do not send;
(d) start floating-point coprocessor, when floating-point exception took place, the floating-point exception register carried out record;
(e) carry out the last item micro-order, the floating-point microprogram is finished micro-order, and the floating-point context register is preserved current instruction scene of carrying out after receiving this micro-order;
(f) floating-point is finished the micro-order detection, forwards step (b) to, and is complete up to program.
3. method according to claim 2 is characterized in that: the last abnormal information of just preserving this floating point instruction in that floating point instruction is carried out guarantees not cover last the scene that the unusual floating point instruction of non-shielding is arranged; The beginning of every instruction microprogram all is provided with the test floating-point and finishes the detection micro-order, guarantees that last floating point instruction is finished afterwards to judge just whether last floating point instruction has unusual generation; Micro-order and non-shielding jointly control the triggering opportunity of interruption unusually.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN2008100173607A CN101221492B (en) | 2008-01-22 | 2008-01-22 | Floating point exception handling device and method for handling exception using the same |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN2008100173607A CN101221492B (en) | 2008-01-22 | 2008-01-22 | Floating point exception handling device and method for handling exception using the same |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN101221492A CN101221492A (en) | 2008-07-16 |
| CN101221492B true CN101221492B (en) | 2010-07-21 |
Family
ID=39631356
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN2008100173607A Expired - Fee Related CN101221492B (en) | 2008-01-22 | 2008-01-22 | Floating point exception handling device and method for handling exception using the same |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN101221492B (en) |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN111782269B (en) * | 2020-06-04 | 2023-12-12 | 珠海格力电器股份有限公司 | Interrupt processing method and interrupt processing equipment |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5862066A (en) * | 1997-05-01 | 1999-01-19 | Hewlett-Packard Company | Methods and apparatus for fast check of floating point zero or negative zero |
| US6014743A (en) * | 1998-02-05 | 2000-01-11 | Intergrated Device Technology, Inc. | Apparatus and method for recording a floating point error pointer in zero cycles |
| CN1415087A (en) * | 1999-10-29 | 2003-04-30 | 英特尔公司 | Mechanism to detect IEEE underflow exceptions on speculative floating-point operations |
-
2008
- 2008-01-22 CN CN2008100173607A patent/CN101221492B/en not_active Expired - Fee Related
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5862066A (en) * | 1997-05-01 | 1999-01-19 | Hewlett-Packard Company | Methods and apparatus for fast check of floating point zero or negative zero |
| US6014743A (en) * | 1998-02-05 | 2000-01-11 | Intergrated Device Technology, Inc. | Apparatus and method for recording a floating point error pointer in zero cycles |
| CN1415087A (en) * | 1999-10-29 | 2003-04-30 | 英特尔公司 | Mechanism to detect IEEE underflow exceptions on speculative floating-point operations |
Non-Patent Citations (1)
| Title |
|---|
| JP特开2005-18606A 2005.01.20 |
Also Published As
| Publication number | Publication date |
|---|---|
| CN101221492A (en) | 2008-07-16 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US10339322B2 (en) | Method and apparatus for identifying security vulnerability in binary and location of cause of security vulnerability | |
| CN109508536B (en) | Detection method and device for tampering program flow attack | |
| US7975130B2 (en) | Method and system for early instruction text based operand store compare reject avoidance | |
| US5321698A (en) | Method and apparatus for providing retry coverage in multi-process computer environment | |
| US7752427B2 (en) | Stack underflow debug with sticky base | |
| KR101249693B1 (en) | Selecting subroutine return mechanisms | |
| US8806447B2 (en) | Step-type operation processing during debugging by machine instruction stepping concurrent with setting breakpoints | |
| JP5815596B2 (en) | Method and system for accelerating a procedure return sequence | |
| US11429392B2 (en) | Secure predictors for speculative execution | |
| US6735688B1 (en) | Processor having replay architecture with fast and slow replay paths | |
| CN104520868B (en) | For detecting the system that allocating stack is distorted | |
| US8347066B2 (en) | Replay instruction morphing | |
| US6189093B1 (en) | System for initiating exception routine in response to memory access exception by storing exception information and exception bit within architectured register | |
| US9575852B2 (en) | Failure recovery apparatus of digital logic circuit and method thereof | |
| CN101221492B (en) | Floating point exception handling device and method for handling exception using the same | |
| CN107111525B (en) | System error handling in a data processing apparatus | |
| US7684973B2 (en) | Performance improvement for software emulation of central processor unit utilizing signal handler | |
| CN105573814A (en) | Method for analysis and execution of local variable byte code of JAVA card by applying chip hardware | |
| CN201188216Y (en) | Apparatus for processing exception of floating point | |
| WO2001061480A1 (en) | Processor having replay architecture with fast and slow replay paths | |
| AU1490888A (en) | Apparatus and method for synchronization of arithmetic exceptions in parallel pipelined execution units | |
| US7404069B2 (en) | Branch tracing generator device and method for a microprocessor supporting predicated instructions and expanded instructions | |
| US20230401313A1 (en) | Processor with In-Band Fault-Injection Detection in the Presence of Exceptions | |
| JP2002312240A (en) | Circuit device and method for detecting access disturbance in micro controller | |
| US20070156387A1 (en) | Reliability improvement using signal handler for fault recovery in software emulator |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant | ||
| CF01 | Termination of patent right due to non-payment of annual fee |
Granted publication date: 20100721 Termination date: 20130122 |
|
| CF01 | Termination of patent right due to non-payment of annual fee |