CN101217341A - A fast velocity matching method - Google Patents
A fast velocity matching method Download PDFInfo
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- CN101217341A CN101217341A CNA2008100000877A CN200810000087A CN101217341A CN 101217341 A CN101217341 A CN 101217341A CN A2008100000877 A CNA2008100000877 A CN A2008100000877A CN 200810000087 A CN200810000087 A CN 200810000087A CN 101217341 A CN101217341 A CN 101217341A
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- matching method
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- speed
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Abstract
The invention provides a quick speed matching method, which comprises the following steps: step S102, a perforation rate and consecutive repeated bits in a speed matching process are judged; step S104, under the situations that the perforation rate is smaller than a predefined value or the consecutive repeated bits do not appear, data is divided into two independent data sets according to data parity positions; and step S106, the two divided data sets are processed in parallel. The invention doubles the matching speed of DSP perforation speed in the situation that the perforation rate is smaller than 50 percent, and doubles the matching speed of DSP repeated speed under the situations that consecutive repeat does not appear and an initial value of e is larger than zero.
Description
Technical field
The present invention relates to the communications field, relate in particular to a kind of fast velocity matching method.
Background technology
Third generation partner program (3rd Generation Partnership Project, abbreviation 3GPP) the multiplexing and chnnel coding of describing in technical specification 25.212 agreements is handled, comprise cyclic redundancy check (CRC) code (Cyclic Redundancy Check, be called for short CRC) add, chnnel coding, rate-matched, interweave for the first time, discontinuous emission (DiscontinuousTransmission, abbreviation DTX) insertion, wireless frame segmentation, with interweave for the second time etc., usually utilize digital signal processor (Digital Signal Processor is called for short DSP) to realize.Rate-matched is that data behind the coding of input are punched or repeated, to adapt to the bearer rate requirement of physical channel.
For punching and repetition rate coupling, the algorithm that 3GPP agreement (seeing 25212-6704.2.7.5) requires is as follows, and the core of algorithm is the calculating of parameter e (n).
if?puncturing?is?to?be?performed
e＝eini --initial?error?between?current?and?desired?puncturing
ratio
m＝1 --index?of?current?bit
do?while?m＜＝Xi
e＝e-eminus --update?error
if?e＜＝0?then --check?if?bit?number?m?should?be
punctured
set?bit?xi，m?to?δwhere?δ{0，1}
e＝e+eplus --update?error
end?if
m＝m+1 --next?bit
end?do
else
e＝eini --initial?error?between?current?and?desired
puncturing?ratio
m＝1 --index?of?current?bit
do?while?m＜＝Xi
e＝e-eminus --update?error
do?while?e＜＝0 --check?if?bit?number?m?should?be?repeated
repeat?bit?xi，m
e＝e+eplus--update?error
end?do
m＝m+1 --next?bit
end?do
end?if
Wherein, Xi is a bit length for the treatment of the rate-matched data; Eini is the initial value of parameter e; Eminus is the value that bit e of every input deducts; The value that e increased when eplus was each punching or repetition.Eini is used to control the position of initial punching or repetition; Eminus and eplus have determined punching or the density that repeats.
The core cyclic part of punching rate matching algorithm extracts as follows:
if?e(n)＜＝eminus?then
e(n+1)＝e(n)+(eplus-eminus)
else
e(n+1)＝e(n)-eminus
end?if
Wherein, n equals 0,1......Xi-1.Corresponding text description is as follows:
If current e is smaller or equal to eminus, then:
E adds that eplus subtracts the poor of eminus
Otherwise:
E deducts eminus
The core cyclic part of repetition rate matching algorithm extracts as follows:
If (current output bit is not repetition bit) then
e(n+1)＝e(n)-eminus
else
e(n+1)＝e(n)+eplus
end?if
if?e(n+1)＞0?then
Next output bit is not repetition bit
else
Next output bit is repetition bit
end?if
Wherein, n equals 0,1...... (repetition rate coupling output length-1).Corresponding WD is as follows:
If current output bit is not a repetition bits, then:
E deducts eminus
Otherwise:
E adds eplus
If e is greater than 0, then:
Next output bit is not a repetition bits
Otherwise:
Next output bit is a repetition bits
Realize that according to above-mentioned algorithm because variable e (n) must calculate one by one successively, dependence before and after existing promptly will be calculated e (n+1) and must calculate e (n) earlier, the least limit time that DSP finishes the rate-matched of a bit is 2 instruction cycles.
Because rate-matched is in whole chnnel coding is handled, elapsed time is maximum, so, how, adopts appropriate fast algorithm according to the characteristic of DSP, improve the execution efficient of rate-matched, just very important for the number of users that DSP supports.
Summary of the invention
One or more problems in view of the above the present invention proposes a kind of fast velocity matching method, can carry out the fast velocity coupling on DSP, can significantly improve the speed of DSP punching rate matching.
Fast velocity matching method according to the present invention may further comprise the steps: step S102, judge punching rate and continuous repetition bits in the rate-matched process; Step S104 less than predetermined value or do not occur under the situation of continuous repetition bits, is divided into independently two sets of data according to the odd even position of data with data at punching rate; And step S106, concurrently two sets of data after dividing are handled.
Wherein, predetermined value is 50%.Fast velocity matching method is used to carry out chnnel coding.Fast velocity matching method is realized by Digital Signal Processing.
By the present invention, punching rate less than 50% situation under, the speed of DSP punching rate matching is doubled, do not occur repeating continuously and the e initial value greater than 0 situation under, the speed of DSP repetition rate coupling is doubled.
Description of drawings
Accompanying drawing described herein is used to provide further understanding of the present invention, constitutes the application's a part, and illustrative examples of the present invention and explanation thereof are used to explain the present invention, do not constitute improper qualification of the present invention.In the accompanying drawings:
Fig. 1 is the flow chart of fast velocity matching method according to an embodiment of the invention.
Embodiment
Below with reference to accompanying drawing, describe the specific embodiment of the present invention in detail.
Fig. 1 is the flow chart of fast velocity matching method according to an embodiment of the invention.As shown in Figure 1, this method may further comprise the steps:
Step S102 judges punching rate and continuous repetition bits in the rate-matched process.
Step S104 less than predetermined value or do not occur under the situation of continuous repetition bits, is divided into independently two sets of data according to the odd even position of data with data at punching rate.
Step S106 handles two sets of data after dividing concurrently.
Wherein, predetermined value is 50%.Fast velocity matching method is used to carry out chnnel coding.Fast velocity matching method is realized by Digital Signal Processing.
In an embodiment according to the present invention, for the modal situation of rate-matched, promptly, punching rate is less than 50% or the rate-matched that repeats continuously do not occur, according to the odd even position that inputs or outputs data, the calculating of parameter e is divided into separate two cover e (2n) and e (2n+1) calculates, make full use of the parallel processing capability of many functional units of DSP, improved rate matching speed.
The precondition of punching rate matching is fast: eplus-2*eminus＞0, and the core is achieved as follows:
if?e(n)＜＝2*eminus?then
e(n+2)＝e(n)+(eplus-2*eminus)
else
e(n+2)＝e(n)-2*eminus
end?if
Wherein: n equals 0,1......Xi-2.Corresponding text description is as follows:
If current e is smaller or equal to twice eminus, then:
The e of a position of being separated by equals current e and adds that eplus deducts the poor of twice eminus
Otherwise:
The e of a position of being separated by equals current e and deducts twice eminus
The precondition of repetition rate coupling is fast: eplus-eminus＞0 and e (0)＞0, and the core is achieved as follows:
if?e(n)＜＝eminus?then
e(n+2)＝e(n)+(eplus-eminus)
else
e(n+2)＝e(n)-2*eminus
end?if
Wherein, n equals 0,1...... repetition rate coupling output length-2.Corresponding text description is as follows:
If current e is smaller or equal to eminus, then:
The e of a position of being separated by equals current e and adds that eplus deducts the poor of eminus
Otherwise:
The e of a position of being separated by equals current e and deducts twice eminus
When on DSP, realizing, two overlap any cover in the e parameter independently, the e calculation of parameter of each position is still wanted 2 instruction cycles, but two covers can parallel computation, as long as on average get off the e calculation of parameter of each position just 1 instruction cycle, and the parallel processing capability that has made full use of many functional units of DSP improves processing speed.
By the present invention, punching rate less than 50% situation under, the speed of DSP punching rate matching is doubled, do not occur repeating continuously and the e initial value greater than 0 situation under, the speed of DSP repetition rate coupling is doubled.
The above is the preferred embodiments of the present invention only, is not limited to the present invention, and for a person skilled in the art, the present invention can have various changes and variation.Within the spirit and principles in the present invention all, any modification of being done, be equal to replacement, improvement etc., all should be included within protection scope of the present invention.
Claims (4)
1. a fast velocity matching method is characterized in that, said method comprising the steps of:
Step S102 judges punching rate and continuous repetition bits in the rate-matched process;
Step S104 less than predetermined value or do not occur under the situation of continuous repetition bits, is divided into independently two sets of data according to the odd even position of data with data at described punching rate; And
Step S106 handles two sets of data after dividing concurrently.
2. fast velocity matching method according to claim 1 is characterized in that, described predetermined value is 50%.
3. fast velocity matching method according to claim 2 is characterized in that, described fast velocity matching method is used to carry out chnnel coding.
4. according to each described fast velocity matching method in the claim 1 to 3, it is characterized in that described fast velocity matching method is realized by Digital Signal Processing.
Priority Applications (1)
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|---|---|---|---|
| CN2008100000877A CN101217341B (en) | 2008-01-03 | 2008-01-03 | A fast velocity matching method |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN2008100000877A CN101217341B (en) | 2008-01-03 | 2008-01-03 | A fast velocity matching method |
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| Publication Number | Publication Date |
|---|---|
| CN101217341A true CN101217341A (en) | 2008-07-09 |
| CN101217341B CN101217341B (en) | 2011-11-30 |
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2010028567A1 (en) * | 2008-09-12 | 2010-03-18 | 中兴通讯股份有限公司 | Method and apparatus for rate matching |
| WO2011000308A1 (en) * | 2009-07-01 | 2011-01-06 | 中兴通讯股份有限公司 | Circuit and method for parallel perforation in speed rate matching |
Family Cites Families (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1581722B (en) * | 2003-07-31 | 2011-11-09 | 上海贝尔阿尔卡特股份有限公司 | Dynamic distributing method for digital signal processor (DSP) and digital signal processor cluster |
| EP1826937A1 (en) * | 2006-02-27 | 2007-08-29 | STMicroelectronics S.r.l. | Transmitter and receiver with efficient memory management in rate matching processes |
| CN101079678B (en) * | 2007-06-29 | 2012-11-21 | 重庆重邮信科通信技术有限公司 | A speed matching algorithm for computing and identifying hole/repeated bit position |
-
2008
- 2008-01-03 CN CN2008100000877A patent/CN101217341B/en not_active Expired - Fee Related
Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2010028567A1 (en) * | 2008-09-12 | 2010-03-18 | 中兴通讯股份有限公司 | Method and apparatus for rate matching |
| CN101674150B (en) * | 2008-09-12 | 2013-06-12 | 中兴通讯股份有限公司 | Rate matching method and device |
| US8738797B2 (en) | 2008-09-12 | 2014-05-27 | Zte Corporation | Method and apparatus for rate matching |
| WO2011000308A1 (en) * | 2009-07-01 | 2011-01-06 | 中兴通讯股份有限公司 | Circuit and method for parallel perforation in speed rate matching |
| CN101938323B (en) * | 2009-07-01 | 2013-01-16 | 中兴通讯股份有限公司 | Circuit and method for parallel perforation in rate matching |
| US8694874B2 (en) | 2009-07-01 | 2014-04-08 | Zte Corporation | Circuit and method for parallel perforation in rate matching |
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|---|---|
| CN101217341B (en) | 2011-11-30 |
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Effective date of registration: 20170823 Address after: 151100, No. two, No. 20, 27 Committee, Chang five town, Zhaodong, Heilongjiang Patentee after: Ma Shuai Address before: 518057 Nanshan District science and Technology Industrial Park, Guangdong high tech Industrial Park, ZTE building Patentee before: ZTE Corporation |
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Granted publication date: 20111130 Termination date: 20180103 |