CN101212451A - Firewall chip data packet buffer management method - Google Patents
Firewall chip data packet buffer management method Download PDFInfo
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Abstract
The invention discloses a method for managing the data packet caching of a firewall chip, which comprises the following steps: a memory is distributed in the inner of the chip; the memory is also divided into a plurality of plates with same size and each plate can store a data packet. A tag queue of free memory is built and each lag correspondingly stores an initial address of the data packet plate. If a data packet enters, a lag is taken form the tag queue of the free memory. The data packet is stored into the data packet plate according to the initial address of the data packet plate indicated by the lag; an analysis data packet builds a data packet lag; a process module which determines to process the data packet writes the data packet lag into the data lag queue of the module; the module takes out the data packet lag from the data packet lag queue of the module and carries out a corresponding process according the content of the data packet lag to realize the function possessed by a common firewall. The invention avoids the frequent flitting of the data packet inside the chip, thus enhancing process efficiency of the data packet.
Description
Technical field
The present invention relates to network security and networking technology, relate in particular to a kind of firewall chip data packet buffer management method.
Background technology
Along with the continuous development of network technology, people are more and more higher to the requirement of response speed, packet throughput and the network security of network, need to postpone the security firewall little, that flow is big.This just needs chip (FPGA/ASIC) to realize the performance of hardware-accelerated raising fire compartment wall, and chip is mainly realized parsing, filtration and the forwarding of transceive data bag.This just need carry out cache management to the data pack buffer of the chip of coming in and going out.
At present, the fire compartment wall speed-up chip realizes that the method for data pack buffer management is: each inter-process module is all given an internal memory, be used for storing pending packet, processing module is taken out packet in a certain order, then this packet is analyzed and handled, then result is transferred in the internal memory of correspondence of next processing module so that next module is handled.The method of this data pack buffer management is fairly simple, but packet moves in internal memory repeatedly, and efficient is low, and committed memory is a lot, and each packet processing time in chip is longer.
Summary of the invention
Therefore technical problem to be solved by this invention provides a kind of by setting up the method for processing and data collection bag label realization firewall chip data packet buffer management, this method can avoid packet frequently to move at chip internal, improves processing data packets efficient.
The present invention specifically is achieved in that
1, a kind of firewall chip data packet buffer management method comprises the steps:
1-1, distribute an internal memory at chip internal, this piece internal memory is divided into some onesize pieces again, can deposit a packet, be called the data enclosed mass for every;
1-2, set up a free memory tag queue, each label correspondence is deposited the initial address of a data enclosed mass;
If 1-3 has packet to enter, then from the free memory tag queue, take out a label, according to the data enclosed mass initial address of this label indication, packet is put in the data enclosed mass;
1-4, resolution data bag are set up the packet label, comprise data enclosed mass initial address, data packet length, packet feature and result in this label;
1-5, definite processing module of handling this packet are written to this packet label in the packet tag queue of this module;
1-6, module are taken out the packet label from the packet tag queue of this module, analyze the packet label, handle accordingly according to the content in the packet label, realize the function that general fire compartment wall has, after handling, result is write in the zone of depositing result of packet label;
1-7, definite next processing module of handling this packet, the packet label that will comprise result is written in the packet tag queue of next module;
1-8, next processing module begin downward execution from step 1-6, up to each module finishing dealing with to packet.
2, as 1 described data packet buffer management method, among the described step 1-3, for the packet that enters from chip exterior, check at first whether the packet internal memory is full, if the packet internal memory is full, then wait for the idle data enclosed mass occurring,, just carry out later step up to the condition that satisfies the distribute data enclosed mass.
3, as 1 described data packet buffer management method, among the described step 1-6, according to the content in the packet label, revise packet if desired, then from the data enclosed mass, find packet and revise packet according to the initial address in the packet label, and then handle accordingly, realize the function that general fire compartment wall has.
4, as 1 described data packet buffer management method, among the described step 1-6, module according to the sign of packet label, if this packets need abandons, then discharges the internal memory that this packet takies after handling accordingly and realizing function that general fire compartment wall has.
5, as 4 described data packet buffer management methods, according to the packet label, obtain data enclosed mass initial address, write a free memory label then in corresponding free memory tag queue, discharge the internal memory that this packet takies by the releasing idling label memory.
6, as 1 described data packet buffer management method, among the described step 1-6, after module handles accordingly and realizes function that general fire compartment wall has, sign according to the packet label, if this packets need is transmitted, then transmit this packet, wait to transmit the internal memory that this packet of release takies after finishing.
7, as 6 described data packet buffer management methods, at first revise packet packet header bag tail according to the result in the packet label, transmit this packet then.
8, as 6 described data packet buffer management methods, according to the packet label, obtain data enclosed mass initial address, write a free memory label then in corresponding free memory tag queue, discharge the internal memory that this packet takies by the releasing idling label memory.
9, as any described data packet buffer management method in 1 to 8, among described step 1-5 or the 1-7, after determining to handle the processing module of this packet, if there is plural module to write the packet label simultaneously, then adopt arbitration mechanism to make wherein any one module write operation effective, this packet label is written in the packet tag queue of this module, other modules are in wait state, and the module that wait is writing is finished and write.
10, as 5 or 8 described data packet buffer management methods, write or read a free memory label in corresponding free memory tag queue the time, if have plural module to write simultaneously or read the free memory tag queue, then adopt arbitration mechanism that any one module is write or read operation effective, other modules are in wait state, and the module that wait is writing or reading is finished and write or read.
Owing to adopted above-mentioned processing procedure, the present invention compared with prior art has the following advantages:
1, in network, most packet sizes are all between 64 byte to 1518 bytes, and the packet label that the present invention sets up only comprises data enclosed mass initial address, data packet length, packet feature and result, generally has only 32 bytes.What the present invention adopted the packet label moves moving of surrogate data method bag, and therefore the data total amount of moving can reduce greatly, thereby has reduced the chip memory cost, improved memory usage; By reducing packet the moving of chip, also reduced the time-delay of each resume module packet of chip internal, reduced chip power-consumption; The present invention has finally reduced the exploitation and the production cost of fire wall chip.
2, the result of packet and packet feature have all left the appointed position of packet label in, so each module only needs visit data bag label can finish most of operation, thereby have reduced the complexity of each resume module packet.
3, utilize the present invention only need do the change that minor modifications can adapt to the chip system framework.When system architecture need be adjusted, increase or reduce some processing modules, data pack buffer management mechanism remains unchanged, and only needs to increase or reduce the outlet and the inlet of corresponding packet tag queue and formation, just can realize the memory management of new framework.
4, after each module is finished processing data packets, be not to discharge internal memory (data enclosed mass) at once, give back the free memory label, unless after all processing operations of this packet are all finished, the data enclosed mass just is released, and the free memory label is just put back in the free memory tag queue.
Description of drawings
Fig. 1 is the operational flowchart of system initialization and packet parsing module among the present invention;
Fig. 2 is the operational flowchart of other inside modules among the present invention;
Fig. 3 is the structured flowchart of data processing in the embodiments of the invention.
Embodiment
Below in conjunction with accompanying drawing concrete enforcement of the present invention is further described:
The present invention proposes the method for a kind of fire wall chip, to improve the internal memory service efficiency by inner label queue management internal data buffer memory and external data buffer memory.Its overall technical architecture is: the first step, initialization memory pool, set up the free memory label; Second step, to each allocation of packets internal memory, corresponding free memory label extracts the packet feature simultaneously, sets up the packet label, and transmits, revises the packet label in each processing module; The 3rd step, basis comprise each resume module result's packet label, abandon or transmit packet, discharge the internal memory that this packet takies then.
As shown in Figure 1 and Figure 2, the present invention includes following treatment step:
1, system initialization distributes an internal memory at chip internal, and this piece internal memory is divided into some onesize pieces again, can deposit a packet, be called the data enclosed mass for every.Set up a free memory tag queue, each label is deposited the initial address of a data enclosed mass.
2, for the packet that enters from chip exterior, at first check the condition that whether satisfies the distribute data enclosed mass, promptly whether the data enclosed mass all uses up (the packet internal memory is full).If the packet internal memory is full, then wait for the idle data enclosed mass occurring.If satisfy the condition of distribute data enclosed mass, then from the free memory tag queue, take out a label, according to the data enclosed mass initial address of label indication, packet is put in the data enclosed mass then.
3, resolution data bag extracts the packet feature, sets up the packet label, comprises data enclosed mass initial address, data packet length, packet feature and result in this label.Go out this packet according to the packet feature calculation then and should do next step processing, this label is written in the packet tag queue of this module (be without loss of generality, claim that this module is a module 1) by which module.
4, module 1 is taken out the packet label from the packet tag queue of this module, analyze the packet label, judge whether to revise packet according to the content in the packet label, revise if desired, then from the data enclosed mass, find packet and revise packet according to the initial address in the packet label, handle accordingly then, otherwise only handle accordingly according to the content in the packet label, described respective handling is meant the function that realizes that general fire compartment wall has, such as VLAN (Virtual Local Area Network, VLAN) checks, MAC (Media Access Control, medium access control system) address check, NAT (Network AddressTranslation, network address translation), check sum etc.; After handling, result is write in the zone of depositing result of packet label.Determine to handle next processing module of this packet then, the packet label that will comprise result is write in the packet tag queue of next module (be without loss of generality, claim that this module is a module 2).
5, according to the needs of chip system, each module can be handled according to step 4, up to finishing data packet analysis and processing.
After the processing of finishing packet, can also carry out following operation:
6,, judge that this packets need forwarding still abandons according to the sign of packet label.Abandon if desired, then execution in step 7; Transmit if desired, then execution in step 8.
If 7 packets needs abandon, then according to the packet label, obtain data enclosed mass initial address, write a free memory label then in corresponding free memory tag queue, discharge the internal memory that this packet takies by the releasing idling label memory.
If 8 packets needs are transmitted, at first revise packet packet header bag tail according to the result in the packet label, as vlan ID, ip address, check sum etc., transmit then.Wait to transmit finish after according to the packet label, obtain data enclosed mass initial address, write a free memory label then in corresponding free memory tag queue, discharge the internal memory that this packet takies by the releasing idling label memory.
The sign of packet label judges may have only a kind of or judge that not for example module does not indicate judgement in any one module, directly determines to handle next processing module of this packet, perhaps only abandons sign and judges or have only the judgement of the sign of forwarding.These modules can be connected in series, and constitute complication system.
Below be a concrete embodiment according to above-mentioned treatment step, the structured flowchart of data processing is as shown in Figure 3, and is as follows according to the concrete handling process of Fig. 3:
1, system initialization distributes an internal memory at chip internal, is called memory pool, and memory pool is divided into the individual onesize piece of N (N can decide according to actual conditions) again, can deposit a packet, be called the data enclosed mass for every.Set up a free memory tag queue, include N free memory label, each label correspondence is deposited the initial address of a data enclosed mass.The free memory label is corresponding one by one with the data enclosed mass.
2, for the packet that enters from chip exterior, at first enter the data packet analysis module and handle, check the condition that whether satisfies the distribute data enclosed mass, promptly whether the data enclosed mass all uses up (memory pool is full).If memory pool is full, then wait for the idle data enclosed mass occurring.If satisfy the condition of distribute data enclosed mass, then from the free memory tag queue, take out a label, according to the data enclosed mass initial address of label indication, packet is put in the data enclosed mass of memory pool then.
3, data packet analysis module parses packet extracts the packet feature, sets up the packet label, comprises data enclosed mass initial address, data packet length, packet feature and result in this label.Go out this packet according to the packet feature calculation then and should do next step processing by which module.If be module 1, the packet label just is written in the packet tag queue of module 1 so, and execution in step 4; If be module 2, the packet label just is written in the packet tag queue of module 2 so, and jumps to step 5 and carry out.
4, module 1 is taken out the packet label successively from the packet tag queue of this module, handles accordingly according to the content in the packet label then, and the back of finishing dealing with judges whether the packet of this packet label correspondence needs to transmit.Transmit if desired, transmit packet so,, obtain data enclosed mass initial address, write a free memory label in corresponding free memory tag queue then according to the packet label.If do not need to transmit, the packet label that then will comprise result is write in the packet tag queue of module 2.
5, module 2 is taken out the packet label successively from the packet tag queue of this module, handle accordingly according to the content in the packet label then, also can do some modifications to the corresponding data bag by the data enclosed mass of revising in the memory pool simultaneously, the packet label that will comprise result after finishing dealing with is write in the packet tag queue of module 3.
6, module 3 is taken out the packet label successively from the packet tag queue of this module, handles accordingly according to the content in the packet label then, also will transmit packet after finishing dealing with.According to the packet label, obtain data enclosed mass initial address then, write a free memory label in corresponding free memory tag queue.
In above-mentioned resume module, if packets need abandons,, obtain data enclosed mass initial address then according to the packet label, write a free memory label then in corresponding free memory tag queue, discharge the internal memory that this packet takies by the releasing idling label memory.
A free memory label takes out, and corresponding data enclosed mass just can be used.In the processing procedure afterwards, though packet in the data enclosed mass and corresponding data label by a plurality of resume module, this data enclosed mass is taken by packet always, is not released.After this packet is forwarded or abandons, a free memory label could be put back in the free memory tag queue, the internal memory of finishing packet discharges.
Except packet entered chip or forwards or abandon, packet was placed in the data enclosed mass and no longer moves, but can be modified in the data enclosed mass.The corresponding data label transmits at each intermodule, the conflict of having avoided module simultaneously a packet to be visited.Can guarantee a plurality of module parallel processings again, promptly each module is handled different packets simultaneously respectively, has improved treatment effeciency on the whole.
If there is plural module to write the packet label simultaneously, it is effective by which module operation to need the arbitration mechanism ruling, as long as it is effective to guarantee that any time has only a module to write the packet tag operational at most, arbitration mechanism can adopt any one routine techniques to realize, other modules are in wait state, and the module that wait is writing is finished and write.
If there is plural module to write (giving back) free memory label simultaneously, it is effective by which module operation to need the arbitration mechanism ruling, as long as it is effective to guarantee that any time has only a module to write the free memory tag operational at most, arbitration mechanism can adopt any one routine techniques to realize, other modules are in wait state, and the module that wait is writing is finished and write.
If being arranged, plural module reads (taking away) free memory label simultaneously, it is effective by which module operation to need the arbitration mechanism ruling, as long as it is effective to guarantee that any time has only a module to read the free memory tag operational at most, arbitration mechanism can adopt any one routine techniques to realize, other modules are in wait state, and the module that wait is being read is finished read operation.
The above is an illustrative examples of the present invention only, is not limited to the present invention, and for a person skilled in the art, the present invention can have various changes and variation.Within the spirit and principles in the present invention all, any modification of being done, be equal to replacement, improvement etc., all should be included within protection scope of the present invention.
Claims (10)
1. a firewall chip data packet buffer management method comprises the steps:
1-1, distribute an internal memory at chip internal, this piece internal memory is divided into some onesize pieces again, can deposit a packet, be called the data enclosed mass for every;
1-2, set up a free memory tag queue, each label correspondence is deposited the initial address of a data enclosed mass;
If 1-3 has packet to enter, then from the free memory tag queue, take out a label, according to the data enclosed mass initial address of this label indication, packet is put in the data enclosed mass;
1-4, resolution data bag are set up the packet label, comprise data enclosed mass initial address, data packet length, packet feature and result in this label;
1-5, definite processing module of handling this packet are written to this packet label in the packet tag queue of this module;
1-6, module are taken out the packet label from the packet tag queue of this module, analyze the packet label, handle accordingly according to the content in the packet label, realize the function that general fire compartment wall has, after handling, result is write in the zone of depositing result of packet label;
1-7, definite next processing module of handling this packet, the packet label that will comprise result is written in the packet tag queue of next module;
1-8, next processing module begin downward execution from step 1-6, up to each module finishing dealing with to packet.
2. data packet buffer management method as claimed in claim 1, it is characterized in that, among the described step 1-3, for the packet that enters from chip exterior, check at first whether the packet internal memory is full,, then wait for the idle data enclosed mass occurring if the packet internal memory is full, up to the condition that satisfies the distribute data enclosed mass, just carry out later step.
3. data packet buffer management method as claimed in claim 1, it is characterized in that, among the described step 1-6, according to the content in the packet label, revise packet if desired, then from the data enclosed mass, find packet and revise packet, and then handle accordingly, realize the function that general fire compartment wall has according to the initial address in the packet label.
4. data packet buffer management method as claimed in claim 1 is characterized in that, among the described step 1-6, after module handles accordingly and realizes function that general fire compartment wall has, according to the sign of packet label,, then discharge the internal memory that this packet takies if this packets need abandons.
5. data packet buffer management method as claimed in claim 4, it is characterized in that, according to the packet label, obtain data enclosed mass initial address, write a free memory label then in corresponding free memory tag queue, discharge the internal memory that this packet takies by the releasing idling label memory.
6. data packet buffer management method as claimed in claim 1, it is characterized in that, among the described step 1-6, after module handles accordingly and realizes function that general fire compartment wall has, sign according to the packet label, if this packets need is transmitted, then transmit this packet, wait to transmit the internal memory that this packet of release takies after finishing.
7. data packet buffer management method as claimed in claim 6 is characterized in that, at first revises packet packet header bag tail according to the result in the packet label, transmits this packet then.
8. data packet buffer management method as claimed in claim 6, it is characterized in that, according to the packet label, obtain data enclosed mass initial address, write a free memory label then in corresponding free memory tag queue, discharge the internal memory that this packet takies by the releasing idling label memory.
9. as any described data packet buffer management method in the claim 1 to 8, it is characterized in that, among described step 1-5 or the 1-7, after determining to handle the processing module of this packet, if there is plural module to write the packet label simultaneously, then adopt arbitration mechanism to make wherein any one module write operation effective, this packet label is written in the packet tag queue of this module, other modules are in wait state, and the module that wait is writing is finished and write.
10. as claim 5 or 8 described data packet buffer management methods, it is characterized in that, write or read a free memory label in corresponding free memory tag queue the time, if have plural module to write simultaneously or read the free memory tag queue, then adopt arbitration mechanism that any one module is write or read operation effective, other modules are in wait state, and the module that wait is writing or reading is finished and write or read.
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Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN102638412A (en) * | 2012-05-04 | 2012-08-15 | 杭州华三通信技术有限公司 | Cache management method and device |
| WO2015113291A1 (en) * | 2014-01-29 | 2015-08-06 | 华为技术有限公司 | Wireless network data processing device and wireless network system |
| WO2016055004A1 (en) * | 2014-10-10 | 2016-04-14 | Huawei Technologies Co., Ltd. | System and method for system on a chip |
| CN105591979A (en) * | 2015-12-15 | 2016-05-18 | 曙光信息产业(北京)有限公司 | Message processing system and method |
| US10496622B2 (en) | 2015-10-09 | 2019-12-03 | Futurewei Technologies, Inc. | System and method for real-time data warehouse |
| US10783160B2 (en) | 2015-10-09 | 2020-09-22 | Futurewei Technologies, Inc. | System and method for scalable distributed real-time data warehouse |
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| CN100358320C (en) * | 2003-12-24 | 2007-12-26 | 华为技术有限公司 | A data packet storage management method and apparatus |
| CN100452761C (en) * | 2004-04-27 | 2009-01-14 | 华为技术有限公司 | Method of data packet storage in communication equipment |
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Cited By (10)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102638412A (en) * | 2012-05-04 | 2012-08-15 | 杭州华三通信技术有限公司 | Cache management method and device |
| CN102638412B (en) * | 2012-05-04 | 2015-01-14 | 杭州华三通信技术有限公司 | Cache management method and device |
| WO2015113291A1 (en) * | 2014-01-29 | 2015-08-06 | 华为技术有限公司 | Wireless network data processing device and wireless network system |
| CN105075191A (en) * | 2014-01-29 | 2015-11-18 | 华为技术有限公司 | Wireless network data processing device and wireless network system |
| CN105075191B (en) * | 2014-01-29 | 2018-09-21 | 华为技术有限公司 | Wireless network data processing unit and Radio Network System |
| US10129792B2 (en) | 2014-01-29 | 2018-11-13 | Huawei Technologies Co., Ltd | Data processing apparatus in wireless network, and wireless network system |
| WO2016055004A1 (en) * | 2014-10-10 | 2016-04-14 | Huawei Technologies Co., Ltd. | System and method for system on a chip |
| US10496622B2 (en) | 2015-10-09 | 2019-12-03 | Futurewei Technologies, Inc. | System and method for real-time data warehouse |
| US10783160B2 (en) | 2015-10-09 | 2020-09-22 | Futurewei Technologies, Inc. | System and method for scalable distributed real-time data warehouse |
| CN105591979A (en) * | 2015-12-15 | 2016-05-18 | 曙光信息产业(北京)有限公司 | Message processing system and method |
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