CN101211318A - Rapid virtual-to-physical address converting device and its method - Google Patents
Rapid virtual-to-physical address converting device and its method Download PDFInfo
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Abstract
The invention discloses a rapid virtual/physical address conversion device, which comprises an instruction fetching and coding component, an emission component, an execution unit, an address calculation unit, a cache, a rapid virtual/physical address conversion component and a data selection component, as well as an enhanced memory access queue which comprises a memory access queue and a selection unit; the rapid virtual/physical address conversion component comprises a rapid virtual/physical address conversion table unit and a physical address generation unit; wherein the instruction fetching and coding component is electrically connected with the emission component which is connected with the execution unit and the address calculation unit; the execution unit is connected with the address calculation unit in parallel; the execution unit is connected with a result bus; the address calculation unit is electrically connected with the enhanced memory access queue; the enhanced memory access queue is connected with the cache and the rapid virtual/physical address conversion component; the cache and the rapid virtual/physical address conversion component are connected with the data selection component in parallel; and the data selection component is connected with the result bus. The invention also discloses a rapid virtual/physical address conversion method.
Description
Technical field
The present invention relates to micro-processor architecture, particularly a kind of processor that in having the processor of pipeline organization, accessing operation corresponding virtual address is converted to fast method and this method of use of corresponding physical address.
Background technology
In the design of the processor of main flow, rapid virtual-to-physical address translation parts have become a ring indispensable in the streamline as the core component of memory access part, are designed to independently pipelining-stage usually.Virtual address can be converted to physical address fast by rapid virtual-to-physical address translation parts, can improve the performance of memory access to a great extent so use rapid virtual-to-physical address translation parts to carry out the actual situation address translation, now in the design of main flow general processor without exception employing rapid virtual-to-physical address translation parts as its core component.
The expense that the hit rate of rapid virtual-to-physical address translation parts and rapid virtual-to-physical address translation parts are heavily filled out is the key factor that influences entire process device performance, and most processors are all the approach of these two problems of solution as raising processor memory access partial properties and even entire process device performance.
In the system that adopts paged memory management, access instruction in the application program is used virtual address, after application program is operated system loads, distribute corresponding page directory and page table by operating system for it, page directory and page table have been preserved the virtual address of application program and the mapping relations between the physical address, finish the conversion of virtual address to physical address by query page catalogue and page table.In the program of 32 bit address space, article one, accessing operation need take out the page directory item from page directory, read page table according to this page directory item, obtain page table entry, according to the physical page plot in the page table entry, consistent with the physical address low level again as the virtual address low level of page or leaf bias internal, do not need to participate in mapping, calculate the physical address that accessing operation ultimate demand is visited, three memory access of whole process need according to the page or leaf bias internal in physical page plot and the virtual address; For the program of using greater than 32 bit address space, the table that its accessing operation need be inquired about needs more multistage page directory and page table just can obtain physical address corresponding.There is a large amount of accessing operations in the application program,, will increases the burden of memory access parts greatly, have a strong impact on the speed that processor is carried out if each accessing operation all carries out the above-mentioned process of tabling look-up.
In the process that program is carried out, the access instruction in program itself needs the memory access, and getting of processor refers to that operation also needs memory access, and the accessing operation of general procedure all has locality preferably.Rapid virtual-to-physical address translation parts mainly are spatial locality and the temporal localities that has utilized accessing operation, and the actual situation address mapping relation that some page query page catalogue and page table are obtained carries out buffer memory; When visiting this page content once more, utilize the content in the buffer memory, finish the conversion of virtual address fast to physics, avoid each accessing operation all to carry out complicated page directory and page table walks.The hardware of rapid virtual-to-physical address translation parts is formed and generally is divided into CAM (Content-AddressableMemory) and RAM two parts.Wherein CAM is the memory module according to content search, is used for depositing the high position of virtual address; RAM is the memory module according to search index, is used for depositing the high position of physical address, and some zone bits relevant with the actual situation physical address map also leave among the RAM.
When accessing operation is flowed through rapid virtual-to-physical address translation parts in streamline, virtual address inquiry rapid virtual-to-physical address translation parts CAM according to memory access, if hit wherein one, then obtain this index, index among the rapid virtual-to-physical address translation parts R AM according to this and read corresponding physical address; If inquiry rapid virtual-to-physical address translation parts CAM does not hit, rapid virtual-to-physical address translation parts disappearance has then taken place.
Need heavily fill out operation to rapid virtual-to-physical address translation parts during rapid virtual-to-physical address translation parts disappearance, and heavily fill out action need query page catalogue and page table, this is the main expense source of rapid virtual-to-physical address translation parts.So in order to reduce the expense that rapid virtual-to-physical address translation parts disappearance is brought, method is exactly to improve the hit rate of rapid virtual-to-physical address translation parts and improve the speed that rapid virtual-to-physical address translation parts are heavily filled out the most intuitively.
Reducing the load-to-use delay is the key that improves processor memory access performance, the introducing of high-speed cache is exactly in order to alleviate this problem, by this layer stored logic between processor main flow waterline and storer, processor can in most of the cases be avoided direct access memory, has improved the performance of memory access.Nearly all main flow general processor all comprises the high-speed cache logic in streamline, and the high-speed cache logic often is used as independently pipelining-stage.Under the situation that other conditions are determined, the bandwidth that increases the memory access path is the effective way that reduces that load-to-use postpones, but increases the logical complexity that bandwidth means increases the memory access path, and the RAM logic on the memory access path all needs to provide dual-port.Increase on these complexities will certainly increase the time delay and the power consumption of memory access path.
Postpone in order to reduce memory access, the main flow processor generally is placed on identical pipelining-stage with high-speed cache with rapid virtual-to-physical address translation parts, adopt the high-speed cache of virtual address index, accessing operation is access cache and rapid virtual-to-physical address translation parts simultaneously, so the width of the memory access streamline of high bandwidth needs rapid virtual-to-physical address translation parts that the ability of simultaneously a plurality of accessing operations being carried out the actual situation address translation is provided.A kind of simple processing mode is to make rapid virtual-to-physical address translation parts that a plurality of access ports are provided, visit respectively corresponding access port of a plurality of accessing operations of rapid virtual-to-physical address translation parts simultaneously, but this directly causes the RAM module of rapid virtual-to-physical address translation parts that the access port of respective number need be provided, and has a strong impact on the area and the power consumption of rapid virtual-to-physical address translation parts.
Summary of the invention
The objective of the invention is when a plurality of access port is provided, can have a strong impact on the area of rapid virtual-to-physical address translation parts and the defective of power consumption for the RAM module that overcomes existing rapid virtual-to-physical address translation parts, thus the processor that a kind of rapid virtual-to-physical address conversion method is provided and uses this method.
To achieve these goals, the invention provides a kind of rapid virtual-to-physical address converting device, comprise getting referring to and decoding unit 101, emission element 102, performance element 103, address calculation 104, high-speed cache 106, rapid virtual-to-physical address translation parts 107 and data alternative pack 108; Also comprise strengthening access queue 801, described enhancing access queue 801 comprises access queue 105 and selected cell 802; Described rapid virtual-to-physical address translation parts 107 comprise rapid virtual-to-physical address translation table unit 600 and at least two physical address generation units 806;
Wherein, described getting refers to and decoding unit 101 is electrically connected on the described emission element 102,102 of described emission elements link to each other with address calculation 104 with described performance element 103 respectively, be connected in parallel between described performance element 103 and the address calculation 104, described performance element 103 all is connected on the result bus in the device, described address calculation 104 all is electrically connected with described enhancing access queue 801,801 of described enhancing access queues are connected respectively on described high-speed cache 106 and the rapid virtual-to-physical address translation parts 107, described high-speed cache 106 and rapid virtual-to-physical address translation parts 107 are parallel-connected on the described data alternative pack 108, and 108 of data alternative packs are connected with result bus in the device;
In described rapid virtual-to-physical address translation parts 107, described rapid virtual-to-physical address translation table unit 600 directly links to each other with selected cell 802 in the described enhancing access queue 801, and be connected respectively on described at least two physical address generation units 806, described physical address generation unit 806 also directly is connected with described selected cell 802, and is connected with described data alternative pack 108.
In the technique scheme, described selected cell 802 is selected a plurality of accessing operations of corresponding identical virtual page number, and sends to described rapid virtual-to-physical address translation parts 107 and high-speed cache 106.
In the technique scheme, described physical address generation unit 806 usefulness virtual page numbers inquiry rapid virtual-to-physical address translation parts 107 obtain the physical page start address, page or leaf bias internal according to the virtual address of the accessing operation of the identical virtual page number of correspondence obtains a page bias internal, page or leaf bias internal amalgamation with physical page start address and virtual address obtains required physical address.
In the technique scheme, the number of described at least two physical address generation units 806 is identical with the maximum number of the accessing operation of described selected cell 802 each corresponding identical virtual page numbers of selecting from described access queue 105.
The present invention also provides a kind of rapid virtual-to-physical address conversion method, comprising:
Step 701), accessing operation through described get refer to and decoding unit 101 decodings after be sent on the emission element 102, by emission element 102 this accessing operation is transmitted into address calculation 104;
Step 702), described address calculation 104 is calculated the needed virtual address of accessing operation, and result calculated is sent in the described enhancing access queue 801;
Step 703), 801 pairs of accessing operations of being stored of described enhancing access queue search, check whether to have the known but accessing operation of physical address the unknown of virtual address, if there is not execution in step 710), otherwise, carry out next step;
Step 704), from described enhancing access queue 801, select one or more groups to have the accessing operation of identical virtual page number;
Step 705), from step 704) select one group the selected accessing operation group that goes out, calculate the start address of the pairing virtual page number of this group accessing operation;
Step 706), utilize step 705) in the start address of the virtual page number that calculated, on the rapid virtual-to-physical address translation table unit 600 of described rapid virtual-to-physical address translation parts 107, search whether there is the corresponding virtual address, if have, then carry out next step, otherwise execution in step 709);
Step 707), according to the start address of virtual page number, obtain the start address of physical page;
Step 708), each accessing operation on the same group all can be according to step 707) in the start address of the physical page that obtains, and the page or leaf bias internal amount of the virtual address that is had itself calculates physical address corresponding separately, calculates and finishes back execution in step 710);
Step 709), rapid virtual-to-physical address translation parts disappearance takes place, handle accordingly by processor;
Step 710), end operation.
The invention has the advantages that:
1, the present invention has utilized the locality of accessing operation, i.e. the often corresponding identical virtual page number of a plurality of accessing operations in the access queue; When the accessing operation of one group of corresponding identical virtual page number is addressed to rapid virtual-to-physical address translation parts at the same time in the access queue, only need to take an access port of rapid virtual-to-physical address translation parts, so just saved the access port of rapid virtual-to-physical address translation parts.
2, the present invention reduces the area and the power consumption of fast address converting member by the mode of saving access port, helps the design of high bandwidth memory access path.
Description of drawings
Fig. 1 in the existing processor with the structural drawing of rapid virtual-to-physical address translation relevant portion;
Fig. 2 is for allowing the pipeline organization of many simultaneously treated memory access parts of accessing operation;
Fig. 3 a is for to writing the synoptic diagram of the formation that accessing operation manages independently;
Fig. 3 b is for to reading the synoptic diagram of the formation that accessing operation manages independently;
Fig. 4 is for to writing accessing operation and reading the synoptic diagram of the formation that the accessing operation unification manages;
Fig. 5 is for including the synoptic diagram of many accessing operations in the access queue;
Fig. 6 is the synoptic diagram of the actual situation page address table of comparisons;
Fig. 7 is the process flow diagram of rapid virtual-to-physical address conversion method of the present invention;
Fig. 8 is for strengthening the structural drawing of access queue and rapid virtual-to-physical address translation parts;
Fig. 9 is the structural drawing of rapid virtual-to-physical address converting device of the present invention.
The drawing explanation
101 get finger and decoding unit 102 emission elements 103 performance elements
104 address calculation, 105 access queues, 106 high-speed caches
107 rapid virtual-to-physical address translation parts, 108 data alternative packs 801 strengthen access queue
802 selected cells, 806 physical address generation units
600 rapid virtual-to-physical address translation table units
Embodiment
The invention will be further described below in conjunction with the drawings and specific embodiments.
Fig. 2 is the pipeline organization that can allow many simultaneously treated memory access parts of accessing operation; Access queue 105 can be selected many accessing operations that virtual address is known at every turn, and the accessing operation of selecting sent to high-speed cache 106 and rapid virtual-to-physical converting member 107, this just requires high-speed cache 106 and rapid virtual-to-physical converting member 107 to have the ability of handling many accessing operations simultaneously, obtains a plurality of Query Results simultaneously.Correspondingly, data alternative pack 108 also needs to generate simultaneously the result of many accessing operations.And therefore rapid virtual-to-physical converting member 107 need overcome this defective by the present invention owing to can be subjected to the restriction of area and power consumption, thereby handles when realizing many accessing operations.
Fig. 1 is the cut-away view of an existing processor, comprising the part relevant, in this part, comprise getting referring to and decoding unit 101, emission element 102, performance element 103, address calculation 104, access queue 105, high-speed cache 106, rapid virtual-to-physical address translation parts 107 and data alternative pack 108 with the rapid virtual-to-physical address translation.Wherein, getting finger and decoding unit 101 is electrically connected on the emission element 102,102 of emission elements link to each other with address calculation 104 with performance element 103 respectively, performance element 103 and address calculation 104 can have a plurality of in processor, be connected in parallel between each performance element and address calculation, described performance element 103 all is connected on the result bus in the processor, described address calculation 104 all is connected with access queue 105,105 of access queues are connected respectively on high-speed cache 106 and the rapid virtual-to-physical address translation parts 107, high-speed cache 106 and rapid virtual-to-physical address translation parts 107 are parallel-connected on the data alternative pack 108, and 108 of data alternative packs are connected with result bus in the processor.
Compare with processor of the prior art, as shown in Figure 9, rapid virtual-to-physical address converting device of the present invention is converted to access queue 105 and strengthens access queue 801, and for the structure in the rapid virtual-to-physical address translation parts 107 certain change is arranged also.Below the various piece in apparatus of the present invention is done detailed explanation:
Get and refer to and decoding unit 101: get the instruction that finger and decoding unit 101 will be carried out according to next bar of pc value taking-up that provides, decoding logic in the parts is deciphered the microcode form that generates one or more processor internal representation to the instruction of getting, this macro instruction is the instruction set form of alignment processing device compatibility, CICS format order as x86 architecture processor correspondence, perhaps such as the order format of RISC frameworks such as PowerPC, Alpha, inner microcode form all is the form of class RISC generally then.The realization of getting finger and decoding unit 101 is same as the prior art.
Emission element 102: the microcode of internal format enters emission element 102 after decoding, this module is responsible for selecting current several that can launch from the microoperation that enters into emission element 102, and delivers to follow-up functional part (performance element 103 and address calculation 104) and go to carry out.
Performance element 103: performance element 103 is used for handling fixed point and Floating-point Computation, and the result who calculates is sent on the result bus.
Address calculation 104: address calculation 104 is used to calculate the virtual address of accessing operation, and accessing operation is sent to access queue 105.
The realization of above-mentioned emission element 102, performance element 103 and address calculation 104 is all same as the prior art.
Strengthen access queue 801: strengthen access queue 801 and have the storage accessing operation, and select the function of accessing operation and transmission according to condition.As shown in Figure 8, strengthen access queue 801 and comprise access queue 105 and selected cell 802.Access queue 105 wherein is identical with the function of access queue of the prior art, does not elaborate in the present embodiment.The function of selected cell 802 is to select a plurality of accessing operations of corresponding identical virtual page number and send to rapid virtual-to-physical address translation parts 107 and high-speed cache 106.
High-speed cache 106: high-speed cache 106 is being stored the needed data of accessing operation.
Rapid virtual-to-physical address translation parts 107: stored the transformational relation between virtual address and physical address in the rapid virtual-to-physical address translation parts 107, can obtain physical address by virtual address by rapid virtual-to-physical address translation parts 107.Compare with rapid virtual-to-physical address translation parts of the prior art, rapid virtual-to-physical address translation parts 107 of the present invention exist difference.As shown in Figure 8, rapid virtual-to-physical address translation parts 107 comprise rapid virtual-to-physical address translation table unit 600 and at least two physical address generation units 806, and the number of physical address generation unit 806 is identical with the maximum number of the accessing operation of selected cell 802 each corresponding identical virtual page numbers of selecting from access queue 105.Wherein, rapid virtual-to-physical address translation table unit 600 directly links to each other with selected cell 802, and be connected respectively on described at least two physical address generation units 806, described physical address generation unit 806 also directly is connected with selected cell 802, and is connected with rapid virtual-to-physical address translation parts 107 data alternative pack 108 outward.
Physical address generation unit 806: physical address generation unit 806 obtains required physical address according to the page or leaf bias internal of the virtual address of the accessing operation (501 and 502) of the physical page start address 810 that obtains with virtual page number inquiry rapid virtual-to-physical address translation parts 107, corresponding identical virtual page number with the two amalgamation.
Data alternative pack 108: the physical address that the data of the accessing operation that data alternative pack 108 obtains according to query caching 106 and inquiry rapid virtual-to-physical address translation parts 107 obtain, two-part Query Result formation net result and send on the result bus.
After processor partly is described, again rapid virtual-to-physical address conversion method of the present invention is further described.As shown in Figure 7, rapid virtual-to-physical address conversion method of the present invention may further comprise the steps:
Step 701, an accessing operation are sent on the emission element 102 after getting finger and decoding unit 101 decodings, by emission element 102 this accessing operation are transmitted into address calculation 104;
Step 702, address calculation 104 are calculated the needed virtual address of accessing operation, and result calculated is sent in the enhancing access queue 801;
Step 703, strengthen 801 pairs of accessing operations of being stored of access queue and search, check whether there is virtual address oneself knows but the accessing operation of physical address the unknown, if do not exist, execution in step 710, otherwise, carry out next step;
Step 704, from strengthen access queue 801, select one or more groups to have the accessing operation of identical virtual page number;
Because the locality that has of memory access behavior, the situation of continuous accessing operation visit same page is very general in the program, and access queue can many accessing operations of buffer memory, and the probability of accessing operation of therefrom selecting many identical virtual page numbers of correspondence is very big.And the accessing operation of corresponding identical virtual page number in the access queue is considered as one group, the certain corresponding identical physical page of this group accessing operation.Therefore from an accessing operation group, select an accessing operation can calculate the physical page of all accessing operations in this group arbitrarily, in this case, 600 needs of rapid virtual-to-physical address translation table unit in the rapid virtual-to-physical address translation parts 107 are organized accessing operation for this provides an inquiry port to get final product.
Shown in Figure 5 is the access queue scene at a time of Fig. 4 correspondence, comprises the read operation and the write operation of many corresponding different virtual addresses.For the system that adopts the 4KB size page, preceding 20 in the virtual address is virtual page address, and back 12 is the interior address offset amount of virtual page number.Therefore, for 7 accessing operations that are labeled as 501 to 507, be labeled as 502 with the corresponding identical virtual page number (their virtual page address is all 0x34523) of 504 accessing operation, be labeled as 503 virtual page numbers (their virtual page address be all 0x33056) corresponding identical with 505 accessing operation.Therefore, in step 704, just can select two groups of accessing operations with identical virtual page number.
Step 705, from the selected accessing operation group that goes out of step 704, select one group, calculate the start address of the pairing virtual page number of this group accessing operation.
To be labeled as 502 and 504 accessing operation group is example, and the start address of virtual page number is exactly 0x34523.
The start address of step 706, the virtual page number that utilizes in the step 705 to be calculated, on the rapid virtual-to-physical address translation table unit 600 of rapid virtual-to-physical address translation parts 107, search whether there is the corresponding virtual address, if have, then carry out next step, otherwise execution in step 709.
Step 707, according to the start address of virtual page number, obtain the start address of physical page.
As shown in Figure 6, the actual situation page address table of comparisons 600 mainly comprises three parts: the high position 602 of significance bit 601, virtual page number start address, the high position 603 of physical page start address.In the start address of the regulation page must be that 602 and 603 only need to preserve the high position of address, do not need to preserve the page or leaf bias internal part of address in the system of integral multiple of page size.In the system that adopts 32 bit address space and the 4KB size page, 602 and 603 width is 20.High position according to the virtual page number start address is searched 602, and hitting the back can be 603 kinds of high position of finding corresponding physical page start address according to the index that obtains.The high position of the physical page start address that obtains and the skew in the industry of original virtual are spliced, can obtain the accessing operation physical address corresponding.Be example to be labeled as 502 and 504 accessing operation group still, the start address of the virtual page number of this registers group is 0x34523, can find the start address 0x7915 of the corresponding physical page from table.
Step 708, each accessing operation on the same group all can be according to the start addresses of the physical page that obtains in the step 707, and the page or leaf bias internal amount of the virtual address that is had itself calculates physical address corresponding separately, calculate and finish back execution in step 710;
To be labeled as 502 and 504 accessing operation group is example, and the start address of the physical page of accessing operation 502 is 0x7915, and the page or leaf bias internal amount of virtual address is 784, and the physical address that therefore obtains accessing operation 502 at last is 0x7915784.
Step 710, end operation.
Claims (5)
1. a rapid virtual-to-physical address converting device comprises getting referring to and decoding unit (101), emission element (102), performance element (103), address calculation (104), high-speed cache (106), rapid virtual-to-physical address translation parts (107) and data alternative pack (108); It is characterized in that also comprise strengthening access queue (801), described enhancing access queue (801) comprises access queue (105) and selected cell (802); Described rapid virtual-to-physical address translation parts (107) comprise rapid virtual-to-physical address translation table unit (600) and at least two physical address generation units (806);
Wherein, described getting refers to and decoding unit (101) is electrically connected on the described emission element (102), described emission element (102) then is electrically connected with described performance element (103) and address calculation (104) respectively, be connected in parallel between described performance element (103) and the address calculation (104), described performance element (103) all is connected on the result bus in the device, described address calculation (104) all is electrically connected with described enhancing access queue (801), described enhancing access queue (801) then is connected respectively on described high-speed cache (106) and the rapid virtual-to-physical address translation parts (107), described high-speed cache (106) and rapid virtual-to-physical address translation parts (107) are parallel-connected on the described data alternative pack (108), data alternative pack (108) then with the device in result bus be connected;
In described rapid virtual-to-physical address translation parts (107), described rapid virtual-to-physical address translation table unit (600) links to each other with the selected cell (802) in the described enhancing access queue (801) is electric, and be electrically connected to respectively on described at least two physical address generation units (806), described physical address generation unit (806) also is electrically connected with described selected cell (802), and is electrically connected with described data alternative pack (108).
2. rapid virtual-to-physical address converting device according to claim 1, it is characterized in that, described selected cell (802) is selected a plurality of accessing operations of corresponding identical virtual page number, and sends to described rapid virtual-to-physical address translation parts (107) and high-speed cache (106).
3. rapid virtual-to-physical address converting device according to claim 1, it is characterized in that, described physical address generation unit (806) obtains the physical page start address with virtual page number inquiry rapid virtual-to-physical address translation parts (107), page or leaf bias internal according to the virtual address of the accessing operation of the identical virtual page number of correspondence obtains a page bias internal, page or leaf bias internal amalgamation with physical page start address and virtual address obtains required physical address.
4. rapid virtual-to-physical address converting device according to claim 1, it is characterized in that the maximum number of the accessing operation of the corresponding identical virtual page number that the number of described at least two physical address generation units (806) and described selected cell (802) are selected at every turn is identical from described access queue (105).
5. one kind is applied to the described rapid virtual-to-physical address converting device of claim 1, carries out the method for rapid virtual-to-physical address translation, comprising:
Step 701), accessing operation through described get refer to and decoding unit (101) decoding after be sent on the emission element (102), by emission element (102) this accessing operation is transmitted into address calculation (104);
Step 702), described address calculation (104) is calculated the needed virtual address of accessing operation, and result calculated is sent in the described enhancing access queue (801);
Step 703), described enhancing access queue (801) searches the accessing operation of being stored, check whether to have the known but accessing operation of physical address the unknown of virtual address, if there is not execution in step 710), otherwise, carry out next step;
Step 704), from described enhancing access queue (801), select one or more groups to have the accessing operation of identical virtual page number;
Step 705), from step 704) select one group the selected accessing operation group that goes out, calculate the start address of the pairing virtual page number of this group accessing operation;
Step 706), utilize step 705) in the start address of the virtual page number that calculated, on the rapid virtual-to-physical address translation table unit (600) of described rapid virtual-to-physical address translation parts (107), search whether there is the corresponding virtual address, if have, then carry out next step, otherwise execution in step 709);
Step 707), according to the start address of virtual page number, obtain the start address of physical page;
Step 708), each accessing operation on the same group all can be according to step 707) in the start address of the physical page that obtains, and the page or leaf bias internal amount of the virtual address that is had itself calculates physical address corresponding separately, calculates and finishes back execution in step 710);
Step 709), rapid virtual-to-physical address translation parts disappearance takes place, handle accordingly by processor;
Step 710), end operation.
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| CN102339267A (en) * | 2010-06-04 | 2012-02-01 | 英特赛尔美国股份有限公司 | I2C address translation |
| CN102426554A (en) * | 2011-11-04 | 2012-04-25 | 杭州中天微系统有限公司 | Interface converter for controlling translation lookaside buffers (TLBs) |
| CN106415574A (en) * | 2014-06-23 | 2017-02-15 | 英特尔公司 | Employing intermediary structures for facilitating access to secure memory |
| CN106775587A (en) * | 2016-11-30 | 2017-05-31 | 上海兆芯集成电路有限公司 | The execution method of computer instruction and the device using the method |
| US10437733B2 (en) | 2014-12-23 | 2019-10-08 | Intel Corporation | Method and apparatus to allow secure guest access to extended page tables |
| CN114528022A (en) * | 2015-04-24 | 2022-05-24 | 优创半导体科技有限公司 | Computer processor implementing pre-translation of virtual addresses |
| CN116339916A (en) * | 2023-03-17 | 2023-06-27 | 摩尔线程智能科技(北京)有限责任公司 | Memory virtualization method and device, electronic equipment and storage medium |
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| US7134005B2 (en) * | 2001-05-04 | 2006-11-07 | Ip-First, Llc | Microprocessor that detects erroneous speculative prediction of branch instruction opcode byte |
| US20020194462A1 (en) * | 2001-05-04 | 2002-12-19 | Ip First Llc | Apparatus and method for selecting one of multiple target addresses stored in a speculative branch target address cache per instruction cache line |
| CN1203402C (en) * | 2003-02-21 | 2005-05-25 | 中国航天科技集团公司第九研究院七七一研究所 | System architecture of 16 bits microprocessor |
| CN1280735C (en) * | 2003-12-04 | 2006-10-18 | 中国科学院计算技术研究所 | Initiator triggered remote memory access virtual-physical address conversion method |
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| US9477634B2 (en) | 2010-06-04 | 2016-10-25 | Intersil Americas LLC | I2C address translation |
| CN102426554A (en) * | 2011-11-04 | 2012-04-25 | 杭州中天微系统有限公司 | Interface converter for controlling translation lookaside buffers (TLBs) |
| CN106415574B (en) * | 2014-06-23 | 2020-06-16 | 英特尔公司 | Employing an intermediary structure for facilitating access to secure memory |
| US10558584B2 (en) | 2014-06-23 | 2020-02-11 | Intel Corporation | Employing intermediary structures for facilitating access to secure memory |
| CN106415574A (en) * | 2014-06-23 | 2017-02-15 | 英特尔公司 | Employing intermediary structures for facilitating access to secure memory |
| US10437733B2 (en) | 2014-12-23 | 2019-10-08 | Intel Corporation | Method and apparatus to allow secure guest access to extended page tables |
| CN114528022A (en) * | 2015-04-24 | 2022-05-24 | 优创半导体科技有限公司 | Computer processor implementing pre-translation of virtual addresses |
| CN106775587A (en) * | 2016-11-30 | 2017-05-31 | 上海兆芯集成电路有限公司 | The execution method of computer instruction and the device using the method |
| CN106775587B (en) * | 2016-11-30 | 2020-04-14 | 上海兆芯集成电路有限公司 | Method for executing computer instructions and device using same |
| CN116339916A (en) * | 2023-03-17 | 2023-06-27 | 摩尔线程智能科技(北京)有限责任公司 | Memory virtualization method and device, electronic equipment and storage medium |
| CN116339916B (en) * | 2023-03-17 | 2023-11-10 | 摩尔线程智能科技(北京)有限责任公司 | Memory virtualization method and device, electronic equipment and storage medium |
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