CN101207835B - Monitor for monitoring video signal power level - Google Patents
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Abstract
The invention discloses a monitor for monitoring a video signal electrical level, A function module circuit board is arranged between a television mainboard and a screen mainboard, the television mainboard outputs a LVDS video signal to a LVDS receiving chip and then a RGB video signal group is output after decoding; a line number and column number identify circuit obtains the line number and the column number of a current pixel according to the RGB video signal group, the line number and the column number of the current pixel are sent into a frame memory control circuit and a video signal synthesis circuit, under the control of CLK, the frame memory control circuit controls the writing and reading operation of a double-port frame memory 5 according to the line number and the column number of the current pixel, a signal peak detection circuit detects the average peak value of a signal in a frame according to a received signal to be detected and the average peak value enters the video signal synthesis circuit through an AD converting circuit and an N shift register group, and the video signal synthesis circuit selectively realizes the monitoring of the video signal electrical level according to data and displays the detection results through the screen mainboard, thus the invention has the function of monitoring the video signal electrical level.
Description
Technical field
The present invention relates to digital video signal processing technology, relate in particular to the video level monitoring technology
Background technology
In television program designing processes such as TV station studio, floor, detect and the quality of control of video particularly important, if video quality is bad, gently then snow storm appears in image, and is heavy then occur asynchronously, image rolls or twists, color distorts.In order to obtain high-quality TV programme, stability requirement to the video level peak-to-peak value is very high, if just monitor one tunnel vision signal, can monitor with waveform monitor, but in the television program designing process, tens tunnel even tens road video images show by monitor often, and these video levels of requirement monitoring simultaneously, obviously it is unpractical using tens waveform monitor monitoring video signals, operate also very inconvenient, shooting occasion particularly.
So, be necessary to provide the professional monitor of a kind of price well below waveform monitor, promptly easy to operate, greatly reduce the expense that produces TV shows again.
Summary of the invention
The invention provides a kind of monitor with monitoring video signal power level, make monitor promptly have Presentation Function, have the function of monitoring video signal power level again, save the waveform monitor that price is several times as much as monitor, promptly easy to operate, greatly reduce the expense that produces TV shows again.
A kind of monitor with monitoring video signal power level, wherein, between TV motherboard and the screen body mainboard function module circuit plate is set, this function module circuit plate comprises the LVDS receiving chip, row number row identification circuit, crystal oscillator, controller of frame storage, twoport type frame memory, the signal peak testing circuit, A/D convertor circuit, N bit shift register group, video signal synthesis circuit and LVDS send chip, the LVDS vision signal of TV motherboard output is sent into the LVDS receiving chip with decoding output rgb video signal group, this rgb video signal group comprises field sync signal Vsync, line synchronizing signal Hsync, data clock signal DCLK, data useful signal DEN, the view data rgb signal, row number row identification circuit is according to Vsync, Hsync, DCLK and DEN signal obtain the row number of current pixel and row number, the row of current pixel number and row number are sent into frame and are deposited control circuit and video signal synthesis circuit, crystal oscillator clocking CLK, frame deposit control circuit under CLK control according to the row of current pixel number and row number, " writing " and " reading " operation of control twoport type frame memory, the signal peak testing circuit detects the average peak peak value of signal in the frame according to the measured signal that receives, through A/D convertor circuit input N bit shift register group, N bit shift register group is shifted as clock signal with field sync signal Vsync, the average peak peak value that N bit shift register group is exported the measured signal of N field continuously enters video signal synthesis circuit, video signal synthesis circuit selects to realize monitoring video signal power level according to data, and monitoring result is shown by screen body mainboard.
Described row number row identification circuit comprises row identification circuit and row identification circuit composition, and they are counter, and wherein, as the count resets signal, Hsync is as counting clock with Vsync for the row identification circuit, and count value is the row number of current pixel; As the count resets signal, DEN is as count enable signal with Hsync for the row identification circuit, and DCLK is as counting clock, and count value is the row number of current pixel.
Described peak detection circuit is an integral operation amplifier, the average peak peak value produces DVpp and sends in the N bit shift register group after the A/D convertor circuit digitlization, N bit shift register group is shifted as clock signal with field sync signal Vsync, be every and move 1, N moves the field N position, from N bit shift register group, can export the average peak peak value DVpp of the measured signal of N field continuously, N bit shift register group is made of 8 N bit shift register, and each N bit shift register is formed by N D flip-flop.
Described video signal synthesis circuit is according to the current pixel ranks sent here of row number row identification circuit number, the current pixel ranks number are in that the R1～R2 is capable, during the wicket zone between the C1～C2 row, select the peak-to-peak value signal DVpp of N bit shift register group output, data select to comprise both direction: column direction and line direction.
The view data of described video signal synthesis circuit output has certain delay, after the DEN signal carried out phase delay, the DEN signal of while output image data and delay, send into LVDS and send chip, Vsync, Hsync that the LVDS receiving chip produces and DCLK also send into LVDS and send chip, and LVDS sends chip generation LVDS vision signal and sends.
Described column direction is selected: preceding 1 DVpp is got in the C1 column selection, and preceding 2 DVpp is got in the C1+1 column selection ..., the DVpp of N field before the C2 column selection is got requires to satisfy relation: N=C2-C1+1; Line direction is selected: DVpp is the logical signal of one 8 bit wide, and minimum value is 0, and maximum is 255, related with capable number in proportion, when promptly DVpp is minimum value 0, capable corresponding the classifying as of R2 " bright spot ", other row is " dim spot ", when DVpp is maximum 255, and capable corresponding the classifying as of R1 " bright spot ", other row is " dim spot ", when DVpp is median 128, middle row corresponding the classifying as " bright spot " between the R1～R2, other row is " dim spot ", ..., the rest may be inferred.
Described data through column direction and line direction are selected, and per 1 row have only one " bright spot ", the waveform that shows to be the level peak-to-peak value of measured signal in preceding N field in the wicket zone.
Outside the described wicket zone, the RGB data that the video signal synthesis circuit selection is exported from twoport type frame memory show normal image; When closing function circuit board function, wicket disappears, the RGB data that video signal synthesis circuit is all read from twoport type frame memory, and described monitor does not have the function of monitoring video signal power level.
Described row number row identification circuit, controller of frame storage, N bit shift register group, video signal synthesis circuit all can be edited on the gate array at the scene and realize.
It is application-specific integrated circuit (ASIC) that described LVDS receiving chip, twoport type frame memory, LVDS send chip.
Compared with prior art, the present invention's the monitor with monitoring video signal power level is because between TV motherboard and screen body mainboard, insert the function module circuit plate, the LVDS vision signal 1 of TV motherboard output is sent into the function module circuit plate, after digital video signal processing, output LVDS vision signal 2 is sent into screen body mainboard and is shown, realize received image signal is carried out optionally interpolation by function module circuit, and be reduced to the LVDS vision signal.Make monitor promptly have Presentation Function, have the function of monitoring video signal power level again, save the waveform monitor that price is several times as much as monitor, promptly easy to operate, greatly reduce the expense that produces TV shows again.
Description of drawings
Fig. 1 is the internal circuit block diagram of common monitor;
Fig. 2 is the position view of function module circuit plate in monitor of better embodiment of the present invention;
Fig. 3 is the function module circuit plate its internal circuit block diagram of better embodiment of the present invention;
Fig. 4 is a better embodiment trip of the present invention number row identification circuit interior block diagram;
Fig. 5 is the 0th N bit shift register electrical schematic diagram of better embodiment of the present invention;
Fig. 6 is the video signal synthesis circuit operation principle schematic diagram of better embodiment of the present invention.
Embodiment
For the purpose, technical scheme, the advantage that make the present invention is clearer and more definite, clear, the present invention's technical scheme is described in further detail below in conjunction with embodiment, accompanying drawing.
A kind of monitor with monitoring video signal power level is provided, can be used for multiple monitor, as with liquid crystal (LCD, Liquid Crystal Display) or plasma (PDP, Plasma Display Panel) monitor is an example, as shown in Figure 1, internal circuit block diagram for common monitor, circuit beyond the monitor inside power supply can be divided into two major parts, one is TV movement mainboard 11 (being called for short the movement mainboard), another piece is monitor panel body mainboard 12 (being called for short screen body mainboard), connect by low-voltage differential (LVDS) vision signal between two mainboards, monitor panel body mainboard 12 also comprises LVDS receiving chip 13, and this LVDS receiving chip 13 is used to receive low-voltage differential (LVDS) vision signal that TV movement mainboard 11 sends, TV motherboard and screen body mainboard belong to prior art, no longer apply and state.
In the better embodiment of the present invention, between TV movement mainboard 11 and monitor panel body mainboard 12, insert function module circuit plate 14, as shown in Figure 2, the position view of function module circuit plate in monitor for better embodiment of the present invention, the LVDS vision signal 1 of TV movement mainboard 11 outputs is sent into function module circuit plate 14, after digital video signal processing, output LVDS vision signal 2, send into monitor panel body mainboard 12 and show, this annexation can not change TV motherboard and the original all functions of screen body mainboard.
As shown in Figure 3, be the function module circuit plate its internal circuit block diagram of better embodiment of the present invention, this function module circuit plate comprises that mainly LVDS receiving chip 31, row number row identification circuit 32, crystal oscillator 33, controller of frame storage 34, twoport type frame memory (DPRAM) 35, signal peak testing circuit 36, A/D convertor circuit 37, N bit shift register group 38, video signal synthesis circuit 39 and LVDS send chip 40 and form.
The LVDS vision signal 1 that TV motherboard produces is sent into LVDS receiving chip 31, and LVDS receiving chip 31 can adopt application-specific integrated circuit (ASIC), as DS90CF386.LVDS receiving chip 31 is through handling decoding output rgb video signal group, and this rgb video signal group comprises: field sync signal Vsync, line synchronizing signal Hsync, data clock signal DCLK, data useful signal DEN, and view data rgb signal.
4 road signal Vsync, Hsync, DCLK and DEN send into row number row identification circuit 32, obtain the row number of current pixel and row number, row number row identification circuit is made up of row identification circuit and row identification circuit, they are counter, as shown in Figure 4, be better embodiment trip of the present invention number row identification circuit interior block diagram.Wherein, as the count resets signal, Hsync is as counting clock with Vsync for row counter 41, and count value is exactly the row number of current pixel; As the count resets signal, DEN is as count enable signal with Hsync for row counter 42, and DCLK is as counting clock, and count value is exactly the row number of current pixel.The row of current pixel number row number are sent into frame and are deposited control circuit 34 and video signal synthesis circuit 39 so that current pixel is operated accordingly, its concrete work can such as the back description.
Crystal oscillator 33 produces a stable clock signal CLK, send into frame and deposit control circuit 34, frame is deposited control circuit 34 under CLK control, " writing " and " reading " operation of control twoport type frame memory 35, promptly, send " writing " and " reading " order simultaneously to twoport type frame memory 35, owing to be twoport type frame memory according to the ranks of current pixel number, " write " with " reading " and can carry out simultaneously, twoport type frame memory 35 is an application-specific integrated circuit (ASIC).
Measured signal input signal peak detection circuit 36, detect the average peak peak value Vpp of signal in the frame, peak detection circuit 36 is a kind of integral operation amplifiers, average peak peak value Vpp produces DVpp[7:0 after A/D convertor circuit 37 digitlizations] (establishing AD conversion quantification gradation is 8), send in the N bit shift register group 38, N bit shift register group 38 is shifted as clock signal with field sync signal Vsync, be every and move 1, N moves the field N position, because of a little, from N bit shift register group 38, can export the average peak peak value DVpp[7:0 of the measured signal of N field continuously], N bit shift register group 38 is made of 8 N bit shift register, each N bit shift register is formed by N D flip-flop, as shown in Figure 5, the 0th N bit shift register electrical schematic diagram for better embodiment of the present invention has provided the 0th N bit shift register, and the electrical schematic diagram of the 1st～7 N bit shift register is identical with Fig. 5.
The measured signal peak-to-peak value DVpp[7:0 of N bit shift register group 38 outputs] send in the video signal synthesis circuit 39, the vision signal of reading from twoport type frame memory 35 is also sent in the video signal synthesis circuit 39, video signal synthesis circuit 39 is actually a data selector, its operation principle can be the video signal synthesis circuit operation principle schematic diagram of better embodiment of the present invention as shown in Figure 6.
Video signal synthesis circuit 39 is according to the current pixel ranks sent here of row number row identification circuit 32 number, the current pixel ranks number are in that the R1～R2 is capable, during the wicket zone between the C1～C2 row, select the peak-to-peak value signal DVpp of N bit shift register group 38 outputs, data select to comprise both direction: column direction and line direction.
Column direction is selected: preceding 1 DVpp (see figure 5) is got in the C1 column selection, and preceding 2 DVpp is got in the C1+1 column selection ..., the DVpp of N field before the C2 column selection is got requires to satisfy relation: N=C2-C1+1 here.
Line direction is selected: DVpp is the logical signal of one 8 bit wide, and minimum value is 0, and maximum is 255, related with capable number in proportion, when promptly DVpp is minimum value 0, capable corresponding the classifying as of R2 " bright spot ", other row is " dim spot ", when DVpp is maximum 255, and capable corresponding the classifying as of R1 " bright spot ", other row is " dim spot ", when DVpp is median 128, middle row corresponding the classifying as " bright spot " between the R1～R2, other row is " dim spot ", ..., the rest may be inferred.
Data through column direction and line direction are selected, and per 1 row have only one " bright spot ", the waveform that shows to be the level peak-to-peak value of measured signal in preceding N field in the wicket zone, and N is big more, and window is wide more.Outside the wicket zone, the RGB data that video signal synthesis circuit 39 selections are read from twoport type frame memory 35 show normal image.
When closing function circuit board function, wicket disappears, and during RGB data that video signal synthesis circuit 39 is all read from select frame memory, is exactly the monitor that a Daepori leads to, and described monitor does not have the function of monitoring video signal power level.
The view data of video signal synthesis circuit 39 outputs has certain delay, after the DEN signal carried out phase delay, the DEN signal of while output image data and delay, send into LVDS and send chip 40, Vsync, Hsync that LVDS receiving chip 31 produces and DCLK also send into LVDS and send chip 40, produce LVDS vision signal 2, LVDS sends chip 40 and adopts application-specific integrated circuit (ASIC), as DS90CF386.As can be seen, function module circuit is realized received image signal is carried out optionally interpolation, and is reduced to the LVDS vision signal.Wherein, modular circuits such as row number row identification circuit 32, controller of frame storage 34, N bit shift register group 38, video signal synthesis circuit 39 all can be edited gate array (FPGA) at the scene and be gone up realization, and all the other modular circuits are application-specific integrated circuit (ASIC).In FPGA design, serve as to handle unit with single pixel, can not increase the image noise, to original image content without any infringement.
In sum, technical characterstic of the present invention is:
1, function module circuit is based on Field Programmable Gate Array (FPGA) design, has the advantage that digital circuit is handled, and promptly antijamming capability is strong, and stability is high.
2, serve as to handle unit with single pixel, can not increase the image noise, to original image content without any infringement.
3, when closing function circuit board function (promptly straight-through), have former monitor all functions, when opening function circuit board function, monitor has monitoring picture and monitoring of level of signal dual-use function simultaneously.
Though the present invention is described with reference to current better embodiment; but those skilled in the art will be appreciated that; above-mentioned better embodiment only is used for illustrating the present invention; be not to be used for limiting protection scope of the present invention; any within the spirit and principles in the present invention scope; any modification of being done, equivalence replacement, improvement etc. all should be included within the scope of the present invention.
Claims (6)
1. monitor with monitoring video signal power level, it is characterized in that: between TV motherboard and the screen body mainboard function module circuit plate is set, this function module circuit plate comprises the LVDS receiving chip, row number row identification circuit, crystal oscillator, controller of frame storage, twoport type frame memory, the signal peak testing circuit, A/D convertor circuit, N bit shift register group, video signal synthesis circuit and LVDS send chip, TV motherboard output LVDS vision signal is sent into the LVDS receiving chip with decoding output rgb video signal group, and this rgb video signal group comprises field sync signal Vsync, line synchronizing signal Hsync, data clock signal DCLK, data useful signal DEN, the view data rgb signal; Row number row identification circuit obtains the row number of current pixel and row number according to Vsync, Hsync, DCLK and DEN signal, the row of current pixel number and be listed as and number send into frame and deposit control circuit and video signal synthesis circuit; Crystal oscillator clocking CLK; Frame is deposited control circuit and is operated according to the row of current pixel number and row number control twoport type frame memory " writing " and " reading " under CLK control; Twoport type frame memory is used to store the rgb video signal group of LVD receiving chip decoding output; The signal peak testing circuit goes out the average peak peak value of signal in the frame according to the current video input that receives, through A/D convertor circuit input N bit shift register group, N bit shift register group is shifted as clock signal with field sync signal Vsync, the average peak peak value that N bit shift register group is exported the measured signal of N field continuously enters video signal synthesis circuit, video signal synthesis circuit selects to realize monitoring video signal power level according to data, and monitoring result shown that by screen body mainboard the data selection mode is as follows:
Described video signal synthesis circuit is according to the current pixel ranks sent here of row number row identification circuit number, the current pixel ranks number are in that the R1～R2 is capable, during the wicket zone between the C1～C2 row, select the peak-to-peak value signal DVpp of N bit shift register group output, data select to comprise both direction: column direction and line direction;
Described column direction is selected: preceding 1 DVpp is got in the C1 column selection, and preceding 2 DVpp is got in the C1+1 column selection ..., the DVpp of N field before the C2 column selection is got requires to satisfy relation: N=C2-C1+1; Line direction is selected: DVpp is the logical signal of one 8 bit wide, and minimum value is 0, and maximum is 255, related with capable number in proportion, when promptly DVpp is minimum value 0, capable corresponding the classifying as of R2 " bright spot ", other row is " dim spot ", when DVpp is maximum 255, and capable corresponding the classifying as of R1 " bright spot ", other row is " dim spot ", when DVpp is median 128, middle row corresponding the classifying as " bright spot " between the R1～R2, other row is " dim spot ", ..., the rest may be inferred;
Described data through column direction and line direction are selected, and per 1 row have only one " bright spot ", the waveform that shows to be the level peak-to-peak value of measured signal in preceding N field in the wicket zone;
Outside the described wicket zone, the RGB data that the video signal synthesis circuit selection is exported from twoport type frame memory show normal image; When closing function circuit board function, wicket disappears, the RGB data that video signal synthesis circuit is all read from twoport type frame memory, and described monitor does not have the function of monitoring video signal power level.
2. the monitor with monitoring video signal power level as claimed in claim 1, it is characterized in that: described row number row identification circuit comprises row identification circuit and row identification circuit composition, they are counter, wherein, the row identification circuit with Vsync as the count resets signal, Hsync is as counting clock, and count value is the row number of current pixel; As the count resets signal, DEN is as count enable signal with Hsync for the row identification circuit, and DCLK is as counting clock, and count value is the row number of current pixel.
3. the monitor with monitoring video signal power level as claimed in claim 1, it is characterized in that: described peak detection circuit is an integral operation amplifier, the average peak peak value produces DVpp and sends in the N bit shift register group after the A/D convertor circuit digitlization, N bit shift register group is shifted as clock signal with field sync signal Vsync, be every and move 1, N moves the field N position, from N bit shift register group, can export the average peak peak value DVpp of the measured signal of N field continuously, N bit shift register group is made of 8 N bit shift register, and each N bit shift register is formed by N D flip-flop.
4. the monitor with monitoring video signal power level as claimed in claim 1, it is characterized in that: the view data of described video signal synthesis circuit output has certain delay, after the DEN signal carried out phase delay, the DEN signal of while output image data and delay, send into LVDS and send chip, Vsync, Hsync that the LVDS receiving chip produces and DCLK also send into LVDS and send chip, and LVDS sends chip generation LVDS vision signal and sends.
5. the monitor with monitoring video signal power level as claimed in claim 1 is characterized in that: described row number row identification circuit, controller of frame storage, N bit shift register group, video signal synthesis circuit all can be edited on the gate array at the scene and realize.
6. the monitor with monitoring video signal power level as claimed in claim 1 is characterized in that: it is application-specific integrated circuit (ASIC) that described LVDS receiving chip, twoport type frame memory, LVDS send chip.
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| CN2006101578457A CN101207835B (en) | 2006-12-22 | 2006-12-22 | Monitor for monitoring video signal power level |
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| CN2006101578457A CN101207835B (en) | 2006-12-22 | 2006-12-22 | Monitor for monitoring video signal power level |
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| CN103024367B (en) * | 2011-09-21 | 2017-02-22 | 瑞萨集成电路设计(北京)有限公司 | Low-voltage differential signaling (LVDS) receiver, transmitter and method for receiving and transmitting LVDS |
| CN103024430B (en) * | 2012-12-07 | 2015-06-03 | 广东威创视讯科技股份有限公司 | Control display method and system for simulating red, green and blue (RGB) signal |
| CN106157859A (en) | 2016-09-27 | 2016-11-23 | 京东方科技集团股份有限公司 | For detecting the method and device of Low Voltage Differential Signal |
| WO2021035643A1 (en) * | 2019-08-29 | 2021-03-04 | 深圳市大疆创新科技有限公司 | Monitoring image generation method, apparatus, device, system, and image processing device |
| CN112509525B (en) * | 2020-12-02 | 2022-04-26 | Tcl华星光电技术有限公司 | Control method and control device for liquid crystal display backlight module |
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