CN101202634A

CN101202634A - Single board improving data utilization ratio and system and method of data transmission

Info

Publication number: CN101202634A
Application number: CNA2007101784073A
Authority: CN
Inventors: �田�浩
Original assignee: Hangzhou H3C Technologies Co Ltd
Current assignee: New H3C Technologies Co Ltd
Priority date: 2007-11-29
Filing date: 2007-11-29
Publication date: 2008-06-18
Anticipated expiration: 2027-11-29
Also published as: CN101202634B

Abstract

The invention discloses a veneer used for improving the operating factor of a bandwidth. A veneer processor in the invention utilizes a port address to control words in a SPI4.2 packet to express a target veneer of the data to be transmitted. A bus interface converter confirms a target address of the data to be transmitted according to the port address to SPI4.2 control words in the SPI4.2 packet and adds the confirmed target address into a PCIe header of a PCIe packet and then transmits the PCIe packet through a PCIe bus interface. As invention only adds the data to be transmitted in SPI4.2 data message of the bus interface converter of the veneer and does not add a PCIe header, the operating factor of the bandwidth is improved, thereby improving the operating factor of the bandwidth. The invention also discloses a data transmission system and a method used for improving the operating factor of the bandwidth.

Description

Improve veneer and the data transmission system and the method for bandwidth availability ratio

Technical field

The present invention relates to based on bus interface data converted transmission technology, particularly a kind of veneer of bandwidth availability ratio, a kind of data transmission system and a kind of data transmission method that improves bandwidth availability ratio that improves bandwidth availability ratio of improving of changing based on bus interface.

Background technology

In order to adapt to increasing rapidly of data traffic in the Internet, (PCI Express, PCIe) bussing technique is alleviated the deficiency of system bandwidth can to adopt quick peripheral component interconnect standard usually.

Wherein, PCIe is a processor system bus of being advocated exploitation by Intel (Intel), based on a kind of serial interlinkage technology, accepted and become the successor of peripheral component interconnect standard (PCI), PCI-X at present by PCI-SIG international organization, target is to replace PCI and PCI-X fully.Every pair of circuit of PCIe provides 2.5Gbit/s bandwidth, can provide higher bandwidth to line bundle by many.

With the switching network is example, and the veneer processor of each veneer all is connected to the different PCIe bus interface of PCIe switch respectively in the switching network by the PCIe bus, and passes through the PCIe bus to PCIe switch transmission PCIe packet as shown in Figure 1.As shown in Figure 1, a complete PCIe packet is made up of processing layer, data link layer and physical layer; Processing layer comprises the PCIe packet header (Header) of 16 bytes and the data (Data) of 64 bytes at least, and high 8 bytes in the PCIe packet header are address field, have indicated the final goal address of this packet.Like this, the PCIe switch is realized the exchanges data between its each PCIe bus interface based on the address field in the PCIe packet header of PCIe packet, thereby has realized the transfer of data between the veneer processor of each veneer.

Wherein, according to different functions, veneer can be divided into master control borad and high-speed line plate; Transmitting control data between master control borad and the high-speed line plate is to realize the management of master control borad to each high-speed line plate; The high-speed line plate then is used to realize the miscellaneous service processing, transmission miscellaneous service data between each high-speed line plate; No matter be master control borad or high-speed line plate, its central processing unit (CPU) all can be referred to as the veneer processor, and the veneer processor can be single core processor, high performance polycaryon processor or the network processing unit of existing low performance.

Yet, some veneer processor, for example some polycaryon processor and network processing unit are only supported system's packet interface (SPI4.2) bus interface of the 4.2nd edition data rate, and can't be supported the PCIe bus interface.

Wherein, as shown in Figure 2, the SPI-4.2 bus interface is made of descending (Egress) interface and up (Ingress) interface usually, and Egress interface and Ingress interface are independent separately (in the practical application, these two interfaces can independently exist, and do not need paired appearance).Egress interface and Ingress interface have comprised data channel and push-up storage (FIFO) stator channel again respectively, and the transmission direction of two passages is opposite.Data channel is used for the transmission of data flow, and the fifo status passage then is totally independent of data channel, is used to send fifo status information, thereby realizes the data traffic control of bus.

For this situation, a bus interface transducer need be set on veneer, realize the conversion between SPI4.2 bus interface and the PCIe bus interface, thereby realize transmitting based on the bus interface data converted between each veneer.Generally, the bus interface transducer can be realized by field programmable gate array (FPGA).

As shown in Figure 3, comprise that with veneer master control borad and high-speed line plate are example, existing a kind ofly comprise based on bus interface data converted transmission system: 1 PCIe switch, 1 master control borad and m high-speed line plate of supporting the PCIe bus, wherein, m is the positive integer greater than 2.

The CPU of master control borad supports the PCIe bus interface, and is connected to a PCIe bus interface U of PCIe switch by the PCIe bus, is used for transmitting various control datas with each high-speed line plate, realizes the management to each high-speed line plate.

The CPU of each high-speed line plate supports the SPI4.2 bus interface, and therefore, each high-speed line plate also comprises a FPGA as the bus interface transducer.FPGA on each high-speed line plate links to each other with CPU on this high-speed line plate by the SPI4.2 bus interface, and links to each other with a PCIe bus interface D of PCIe switch with the PCIe bus by the PCIe bus interface, realizes that the bus interface of transmitting data changes.

With the data transfer path shown in the double-head arrow dotted line among Fig. 3 is example, supposes that high-speed line plate 1 need be to high-speed line plate m transmission data, and then the CPU of high-speed line plate 1 sends the SPI4.2 packet by the FPGA of SPI4.2 bus interface on this high-speed line plate.Wherein, the structure of SPI4.2 packet comprises SPI4.2 control word and SPI4.2 data message as shown in Figure 4.

Owing to need to comprise that the address field of 8 bytes is to identify the destination address of this PCIe packet in the PCIe packet header of PCIe packet, and do not comprise the address field of 8 bytes in the SPI4.2 packet, therefore, except being added into data waiting for transmission in the SPI4.2 data message, the CPU of high-speed line plate 1 also need add 16 PCIe packet header in the SPI4.2 data message, comprise the destination address of expression high-speed line plate m in the PCIe packet header of being added.That is to say, directly construct the PCIe packet, and the PCIe packet of its structure is sent to the FPGA of this plate (i.e. the veneer at this CPU place) as the SPI4.2 data message in the outer SPI4.2 packet of sending out by the CPU of high-speed line plate 1.

Like this, directly will be received from SPI4.2 data message in the SPI4.2 packet of this plate CPU, be that the PCIe packet is peeled off as the FPGA of bus converter in the high-speed line plate 1, and according to the destination address of wherein representing high-speed line plate m this PCIe packet is sent and to get final product, and need not other operations.The PCIe switch can by corresponding PCIe bus interface D, be sent to high-speed line plate m with this PCIe packet according to the destination address of expression high-speed line plate m in the PCIe packet that receives.

Though aforesaid way can be realized transmitting based on the bus interface data converted, but because the CPU of high-speed line plate 1 also needs to add extra PCIe packet header in it is transferred to the SPI4.2 packet of this plate FPGA, taken the part bandwidth, especially when transmitting less packet, the bandwidth ratio that takies is higher.

With the SPI4.2 packet that passes 64 bytes is example, in this SPI4.2 packet, also need additionally to add the expense of 16 bytes, like this, SPI4.2 bus for 10G bandwidth in the plate, because the expense of each SPI4.2 packet 16 byte, the actual bandwidth that is used to transmit data in the SPI4.2 bus is dropped to: 10G * 64 bytes/(64 bytes+16 bytes)=8G.In like manner, by the utilance of many PCIe bus bandwidths that circuit is constituted, be that bandwidth availability ratio also can descend thereupon between plate.

As seen, existing based in the bus interface data converted transmission means, the bus width utilance is not high.

Summary of the invention

In view of this, the invention provides a kind of veneer of bandwidth availability ratio, a kind of data transmission system and a kind of data transmission method that improves bandwidth availability ratio that improves bandwidth availability ratio of improving, can improve the bus bandwidth utilance of transfer of data.

A kind of veneer that improves bandwidth availability ratio provided by the invention comprises: by SPI4.2 bus interface continuous veneer processor and bus interface transducer,

Described veneer processor according to the corresponding relation of port address that sets in advance and veneer, is provided with the pairing port address of target single board of data to be sent in the control word of SPI packet, comprise described data to be sent in the described SPI packet; This SPI packet is sent to described bus interface transducer by described SPI4.2 bus interface;

Described bus interface transducer, corresponding relation according to the port address in the SPI packet that is received from described veneer processor and port address that sets in advance and veneer address, determine veneer address as described datum target to be sent address, determined veneer address is added in the PCIe packet header of described PCIe packet, comprises the data to be sent in the described SPI packet in this PCIe packet; Send described PCIe packet by its PCIe bus interface.

Described bus interface transducer further in the PCIe packet header of the PCIe packet that sends, adds the veneer sign of its place veneer correspondence.

Described bus interface transducer further by the PCIe packet of its PCIe bus interface reception from outside other veneers, comprises the pairing veneer sign of other veneers that sends this PCIe packet in the PCIe packet header of this PCIe packet; Send the SPI packet according to the PCIe packet that receives to described veneer processor; According to the corresponding relation of veneer sign that sets in advance and port address, other veneer corresponding port addresses, described outside are set in this SPI packet;

Described veneer processor identifies other veneers of described outside according to the port address in the SPI packet that receives; Take place when congested at its place veneer, send flow-control information, comprise other veneer corresponding port addresses, described outside in the described flow-control information to described bus interface transducer;

Described bus interface transducer sends PCIe Flow Control bag according to from described veneer processor and comprise the flow-control information of port address to the outside, comprises the pairing veneer of the port address address in the described flow-control information in this PCIe Flow Control bag.

Described bus interface transducer further receives the PCIe Flow Control bag from the outside; Veneer processor to its place veneer sends corresponding flow-control information, and the pairing port address of its place veneer is set in the flow-control information of the veneer processor that sends to its place veneer, need adjust with the flow of representing its place veneer.

Described bus interface transducer further links to each other with the outside switching equipment of its place veneer, the quick peripheral component interconnect Standard PC of described switching equipment support Ie bus;

Described bus interface transducer is further according to direct PCIe Flow Control bag from described switching equipment, veneer processor to this veneer sends corresponding flow-control information, and default universal port address is set in the flow-control information of the veneer processor that sends to this veneer, need adjust with the flow of representing this veneer.

The another kind of veneer that improves bandwidth availability ratio provided by the invention comprises: by SPI4.2 bus interface continuous veneer processor and bus interface transducer,

Described bus interface transducer by the PCIe packet of its PCIe bus interface reception from outside other veneers, comprises the pairing veneer sign of other veneers that sends this PCIe packet in the PCIe packet header of this PCIe packet; Send the SPI packet according to the PCIe packet that receives to described veneer processor; According to the corresponding relation of veneer sign that sets in advance and port address, other veneer corresponding port addresses, described outside are set in the control word of this SPI packet;

Described veneer processor identifies other veneers of described outside according to the port address in the SPI packet that receives.

Described veneer processor takes place when congested at its place veneer, further sends flow-control information to described bus interface transducer, comprises other veneer corresponding port addresses, described outside in the described flow-control information;

A kind of data transmission system that improves bandwidth availability ratio provided by the invention comprises: support switching equipment, source veneer and the target single board of quick peripheral component interconnect Standard PC Ie bus, wherein,

Described source veneer includes with target single board: the veneer processor and the bus interface transducer that link to each other by the SPI4.2 bus interface, and described bus interface transducer links to each other with described switching equipment by the PCIe bus interface;

The veneer processor of source veneer according to the corresponding relation of port address that sets in advance and veneer, is provided with the pairing port address of target single board of data to be sent in the control word of SPI packet, comprise described data to be sent in the described SPI packet; With this SPI packet by being sent to the bus interface transducer of described source veneer;

The bus interface transducer of source veneer, corresponding relation according to the port address in the SPI packet of the veneer processor that is received from described source veneer and port address that sets in advance and veneer address, determine veneer address as described datum target to be sent address, determined veneer address is added in the PCIe packet header of described PCIe packet, comprises the data to be sent in the described SPI packet in this PCIe packet; Send described PCIe packet by its PCIe bus interface to described switching equipment.

The bus interface transducer of source veneer further in the PCIe packet header of the PCIe packet that sends, adds the veneer sign of described source veneer correspondence;

The bus interface transducer of described target single board, send the SPI packet according to the PCIe packet that receives to the veneer processor of described target single board, and, veneer corresponding port address, source is set in the SPI packet of the veneer processor that sends to described target single board according to the corresponding relation of veneer sign that sets in advance and port address;

The veneer processor of described target single board identifies described source veneer according to the port address in the SPI packet that receives; Take place when congested at described target single board, send the flow-control information that comprises with veneer corresponding port address, source to the bus interface transducer of described target single board;

The bus interface transducer of described target single board is according to from the veneer processor of described target single board and comprise flow-control information with veneer corresponding port address, source, send PCIe Flow Control bag to described switching equipment, comprise the veneer address of described source veneer in this PCIe Flow Control bag.

Receive described PCIe Flow Control bag by described switching equipment after, the bus interface transducer of described source veneer further sends corresponding flow-control information to the veneer processor of described source veneer, and according to the corresponding relation of described port address and veneer address, veneer pairing port address in described source is set in the flow-control information of the veneer processor that sends to described source veneer, need adjusts with the flow of representing described source veneer.

After the portion's generation within it of described switching equipment is congested, to the bus interface transducer transmission PCIe of source veneer Flow Control bag;

The bus interface transducer of described source veneer is further according to direct PCIe Flow Control bag from described switching equipment, veneer processor to described source veneer sends corresponding flow-control information, and default universal port address is set in the flow-control information of the veneer processor that sends to described source veneer, need adjust with the flow of representing described source veneer.

A kind of data transmission method that improves bandwidth availability ratio provided by the invention comprises:

Veneer processor on the veneer is provided with the pairing port address of target single board of data to be sent according to the port address that sets in advance and the corresponding relation of veneer in the control word of SPI packet, comprise described data to be sent in the described SPI packet;

Described veneer processor is sent to described bus interface transducer with this SPI packet by described SPI4.2 bus interface;

Bus interface transducer on the described veneer is according to the port address in the SPI packet that is received from described veneer processor and the corresponding relation of port address that sets in advance and veneer address, determine veneer address as described datum target to be sent address, determined veneer address is added in the PCIe packet header of described PCIe packet, comprises the data to be sent in the described SPI packet in this PCIe packet;

Described bus interface transducer sends described PCIe packet by its PCIe bus interface.

Before sending described PCIe packet by its PCIe bus interface, this method further comprises:

This method further comprises:

Described bus interface transducer comprises the pairing veneer sign of other veneers that sends this PCIe packet by the PCIe packet of its PCIe bus interface reception from outside other veneers in the PCIe packet header of this PCIe packet;

Described bus interface transducer sends the SPI packet according to the PCIe packet that receives to described veneer processor, and, other veneer corresponding port addresses, described outside are set in this SPI packet according to the corresponding relation of veneer sign that sets in advance and port address;

Described veneer processor, identify other veneers of described outside according to the port address in the SPI packet that receives, and take place when congested at its place veneer, send flow-control information to described bus interface transducer, comprise other veneer corresponding port addresses, described outside in the described flow-control information;

This method further comprises:

Described bus interface transducer receives the PCIe Flow Control bag from the outside;

Described bus interface transducer sends corresponding flow-control information to the veneer processor of its place veneer, and the pairing port address of its place veneer is set in the flow-control information of the veneer processor that sends to its place veneer, need adjust with the flow of representing its place veneer.

Described veneer sign is the request identify label Request ID in the described PCIe packet header.

The another kind of data transmission method that improves bandwidth availability ratio provided by the invention is characterized in that this method comprises:

Bus interface transducer on the veneer comprises the pairing veneer sign of other veneers that sends this PCIe packet by the PCIe packet of its PCIe bus interface reception from outside other veneers in the PCIe packet header of this PCIe packet;

Described bus interface transducer sends the SPI packet according to the PCIe packet that receives to the veneer processor of its place veneer, and, other veneer corresponding port addresses, described outside are set in the control word of this SPI packet according to the corresponding relation of veneer sign that sets in advance and port address;

Identify after other veneers of described outside, this method further comprises:

Described veneer processor takes place when congested at its place veneer, sends flow-control information to described bus interface transducer, comprises other veneer corresponding port addresses, described outside in the described flow-control information;

The data transmission method of another raising bandwidth availability ratio provided by the invention comprises:

The veneer processor of source veneer is according to the port address that sets in advance and the corresponding relation of veneer, the pairing port address of target single board of data to be sent is set in the control word of SPI packet, comprise described data to be sent in the described SPI packet, and this SPI packet is sent to the bus interface transducer of described source veneer by the SPI4.2 bus interface;

The bus interface transducer of source veneer is according to the port address in the control word of the SPI packet of the veneer processor that is received from described source veneer and the corresponding relation of port address that sets in advance and veneer address, determine veneer address as described datum target to be sent address, determined veneer address is added in the PCIe packet header of described PCIe packet, comprised the data to be sent in the described SPI packet in this PCIe packet, sent described PCIe packet to described switching equipment by the PCIe bus interface;

Described switching equipment is forwarded to described target single board with the PCIe packet that receives.

Describedly send before the described PCIe packet by the PCIe interface, this method further comprises:

The bus interface transducer of source veneer adds described source veneer corresponding preset veneer sign in the PCIe packet header of PCIe packet;

The bus interface transducer of described target single board sends the SPI packet according to the PCIe packet that receives to the veneer processor of described target single board, and, veneer corresponding port address, source is set in the SPI packet of the veneer processor that sends to described target single board according to the corresponding relation of veneer sign that sets in advance and port address;

The veneer processor of described target single board identifies described source veneer according to the port address in the SPI packet that receives, and take place when congested at described target single board, send the flow-control information that comprises veneer corresponding port address, source to the bus interface transducer of described target single board;

The bus interface transducer of described target single board sends PCIe Flow Control bag according to from the veneer processor of described target single board and comprise the flow-control information of port address to described source veneer, comprises the veneer address of described source veneer in this PCIe Flow Control bag.

Described source veneer received described PCIe Flow Control bag by described switching equipment after, this method further comprised:

The bus interface transducer of described source veneer sends corresponding flow-control information to the veneer processor of described source veneer, and according to the corresponding relation of described port address and veneer address, veneer pairing port address in described source is set in the flow-control information of the veneer processor that sends to described source veneer, need adjusts with the flow of representing described source veneer.

As seen from the above technical solution, the veneer processor utilizes the port address of SPI4.2 control word in the SPI4.2 packet to represent the target single board of data to be sent; Behind the SPI4.2 packet that receives by the SPI4.2 bus interface from this plate veneer processor, the bus interface transducer is according to the port address of SPI4.2 control word in the SPI4.2 packet, and pre-assigned port address and destination address, promptly with the corresponding relation of target single board address, determine the destination address of data to be sent, and the destination address of determining is added in the PCIe packet header of PCIe packet, and the data of this PCIe packet are the data in the SPI4.2 data message of SPI4.2 packet, and then this PCIe packet is transferred to the PCIe switching equipment by the PCIe bus interface according to PCIe packet header, according to PCIe packet header this PCIe packet is forwarded to corresponding target single board by this equipment.Because the veneer processor only adds data to be sent in the SPI4.2 data message that sends to this plate bus interface transducer, and no longer adds PCIe packet header, thereby has improved the bandwidth availability ratio in the plate, thereby also can improve bandwidth availability ratio between plate.Especially when transmitting less packet, the effect that improves bandwidth availability ratio is more obvious.

Description of drawings

Fig. 1 is the structural representation of PCIe packet.

Fig. 2 is the model structure structure chart of SPI4.2 bus interface.

Fig. 3 is existing structural representation based on bus interface data converted transmission system.

Fig. 4 is the structural representation of SPI4.2 packet.

Fig. 5 is based on the structural representation of bus interface data converted transmission system in the embodiment of the invention.

Fig. 6 is a schematic diagram of realizing Flow Control between plate in the embodiment of the invention based on bus interface data converted transmission system.

Fig. 7 is based on the schematic flow sheet of bus interface data converted transmission method in the embodiment of the invention.

Embodiment

For making purpose of the present invention, technical scheme and advantage clearer, below with reference to the accompanying drawing embodiment that develops simultaneously, the present invention is described in more detail.

Among the present invention, carry out the veneer of interface bus conversion for need, its veneer processor utilizes the port address of SPI4.2 control word in the SPI4.2 packet to represent the target single board of data to be sent, only in the SPI4.2 data message that sends to this plate bus interface transducer, add data to be sent, and no longer add PCIe packet header, thereby improved the bandwidth availability ratio in the plate; Behind the SPI4.2 packet that receives by the SPI4.2 bus interface from this plate veneer processor, the bus interface transducer is according to the port address of SPI4.2 control word in the SPI4.2 packet, and the corresponding relation of pre-assigned port address and destination address (being the address of target single board), determine the destination address of data to be sent, and the destination address of determining is added in the PCIe packet header of PCIe packet, and the data of this PCIe packet are the data in the SPI4.2 data message of SPI4.2 packet, and then this PCIe packet is transferred to the PCIe switching equipment by the PCIe bus interface according to PCIe packet header, according to PCIe packet header this PCIe packet is forwarded to corresponding target single board by this switching equipment, owing to improved the interior bandwidth availability ratio of the plate of every veneer, thereby between plate, under the situation of bandwidth enough big (more than or equal to bandwidth in the plate), also improved bandwidth availability ratio between plate simultaneously.

Wherein, the veneer that above-mentioned need carry out the interface bus conversion can be master control borad, also can be the high-speed line plate.

Specifically,, comprised the port address field in the SPI4.2 control word of SPI4.2 packet, i.e. the position of [11:4] in the table 1 referring to table 1 as follows.

15	The control word type	1: payload control word (closelying follow a payload transmission after the expression control word); 0: idle (idle) code stream or training (training) sequence control word;
15	The control word type		14:13	The EOP state	00: non-EOP; 01: the special applications error situation; The 10:EOP normal termination, 2 bytes are effective; The 11:EOP normal termination, 1 byte is effective;
12	SOP	1: the start of message (SOM); 0:idle code stream or training sequence control word;	14:13	The EOP state
12	SOP		11:4	Port address	1～254: effectively, show port address immediately following the data of this control word; 0:idle code stream control word; 1:training sequence control word;
3:0	DIP-4	The DIP4 odd.	11:4	Port address

Table 1 SPI4.2 control word

The present invention is that every veneer in the system distributes fixing SPI4.2 port address, promptly sets up the corresponding relation of port address and each veneer, thereby can utilize the port address of SPI4.2 control word in the SPI4.2 packet to represent the target single board of data to be sent.

Fig. 5 is based on the structural representation of bus interface data converted transmission system in the embodiment of the invention.As shown in Figure 5, with the switching equipment of supporting the PCIe bus is that PCIe switch, veneer comprise that the CPU of master control borad and high-speed line plate, master control borad supports the CPU of PCIe bus interface, high-speed line plate to support that the SPI4.2 bus interface is an example, and this system comprises: 1 master control borad, 1 PCIe switch and high-speed line plate 1～6.

Because in the present embodiment, the CPU of master control borad supports the PCIe bus interface, therefore, is not described in detail in this.

High-speed line plate 1～6 includes: as the CPU of veneer processor and as the FPGA of bus interface transducer.Wherein, the CPU in each high-speed line plate links to each other by the SPI4.2 bus interface with FPGA, and FPGA links to each other with the PCIe switch by the PCIe bus interface.And the respectively corresponding pre-assigned port address of high-speed line plate 1～6, promptly high-speed line plate i respectively the corresponding port address be i, i is more than or equal to 1 and smaller or equal to 6 positive integer.

Below, the process that elder generation sends out packet outward based on the high-speed line plate describes the system in the present embodiment.

The CPU of each high-speed line plate is added into data to be sent in the data message of SPI4.2 packet; According to the corresponding relation of port address that sets in advance and veneer, in the control word of this SPI4.2 packet, add the pairing port address of target single board of data to be sent; This SPI4.2 packet is sent to the FPGA of this plate.

As the FPGA of bus interface transducer, receive SPI4.2 packet from the CPU of this plate; Data to be sent in the SPI4.2 packet that receives are added in the PCIe packet; Corresponding relation according to the port address in the control word of the SPI4.2 packet that receives and port address that sets in advance and veneer address, determine veneer address, determined veneer address is added in the PCIe packet header of PCIe packet as datum target to be sent address; Send the PCIe packet by the PCIe interface to the PCIe switch.

Wherein, in every veneer as the FPGA of bus interface transducer when the initialization, all can generate this plate address (for other veneers, this this plate address can be regarded the Data Receiving address of this plate as), and with this plate address reproduction give all the other each veneers in the system (this reproduction process can for: each high-speed line plate all gathers this plate address and master control borad, preserve and be handed down to each high-speed line plate again by master control borad), thereby make the address that all can know other veneers in the every veneer, and owing to distributed the fixed port address for every veneer in advance, thereby every veneer all can be set up the corresponding relation of port address and veneer address.

In the practical application, in every veneer as the FPGA of bus interface transducer when the initialization, also can generate the veneer sign of this plate, the for example request identify label (RequestID) in the packet header of PCIe packet, be added on PCIe packet header as shown in Figure 1 when being used for follow-up each transmission PCIe packet, and the Request ID of this plate also duplicated in advance to all the other each veneers in the system, all the other each veneers can be set up the corresponding relation of Request ID and the port address of corresponding different veneers.For other veneers, can regard Flow Control bag receiver address as the Request ID of this plate veneer sign, carry out Flow Control as for how based on Request ID and with the corresponding relation of port address, will be in the follow-up explanation of this paper.

The PCIe switch according to the destination address in the PCIe packet header of the PCIe packet that receives, is sent to this PCIe packet the target single board (master control borad or other high-speed line plates) of correspondence by the PCIe bus interface of correspondence.

With the data transfer path shown in the double-head arrow dotted line among Fig. 5 is example, suppose that high-speed line plate 1 need be to high-speed line plate 5 transmission data, then the CPU of high-speed line plate 1 sends the SPI4.2 packet by the FPGA of SPI4.2 bus interface on this high-speed line plate, and with the port address in the control word of this SPI4.2 packet, be set in advance for high-speed line plate 5 distribute as 5 of port address, be sent to the FPGA of this plate then.After the FPGA of high-speed line plate 1 receives SPI4.2 packet from this plate CPU, identify 5 in its control word, thereby the target single board of determining the data to be sent in this SPI4.2 packet is a high-speed line plate 5, and according to the port address of setting up in advance and the corresponding relation of veneer address, the veneer address of high-speed line plate 5 destination address as data to be sent is made an addition in the PCIe packet PCIe packet header of (having comprised data to be sent in this PCIe packet), be sent to the PCIe switch by the PCIe interface then.The PCIe switch can be forwarded to target single board with this PCIe packet according to the destination address in the PCIe packet header, and promptly the high-speed line plate 5.

As seen, the CPU of every block of high-speed line plate utilizes the port address of SPI4.2 control word in the SPI4.2 packet to represent the target single board of data to be sent in the said system; Behind the SPI4.2 packet that receives by the SPI4.2 bus interface from this plate CPU, in every veneer as the FPGA of bus interface transducer port address according to SPI4.2 control word in the SPI4.2 packet, and pre-assigned port address and destination address, promptly with the corresponding relation of target single board address, determine the destination address of data to be sent, and the destination address of determining is added in the PCIe packet header of PCIe packet, and the data of this PCIe packet are the data in the SPI4.2 data message of SPI4.2 packet, and then according to PCIe packet header this PCIe packet are transferred to the PCIe switch by the PCIe bus interface.Because the CPU of high-speed line plate only adds data to be sent in sending to the SPI4.2 data message of this plate FPGA, and no longer adds PCIe packet header, thereby has improved the bandwidth availability ratio in the plate, thereby also can improve bandwidth availability ratio between plate.

Below, the process based on high-speed line plate reception packet describes the system in the present embodiment again.

As previously mentioned, in every veneer as the FPGA of bus interface transducer when the initialization, also can generate the Request ID of this plate, and when sending the PCIe packet, be added in the PCIe packet header at every turn, and every veneer all can be set up the corresponding relation of Request ID and port address, therefore, receive in other PCIe packets, can comprise the Request ID of unique identification as the source veneer of this PCIe packet from veneer by the PCIe switch.

Like this, as the FPGA in the high-speed line plate of target single board, by the PCIe packet of PCIe switch reception from other veneers (master control borad or other high-speed line plates), according to the Request ID in the PCIe packet header of PCIe packet, identify the source veneer of this PCIe packet, and with the port address of the source veneer that correspondence identified, make an addition in the port address of control word of the SPI4.2 packet of giving this plate CPU to be sent, simultaneously, also the data in the PCIe packet that receives also are added into this SPI4.2 packet, by the SPI4.2 bus interface this SPI4.2 packet is sent to the CPU of this plate then, the CPU of this plate can be known the source veneer of this SPI4.2 packet according to the port address of the control word of SPI4.2 packet.

Be example still with the data transfer path shown in the double-head arrow dotted line among Fig. 5, suppose that high-speed line plate 1 is to high-speed line plate 5 transmission data, by the destination address of PCIe switch, this PCIe packet is forwarded to high-speed line plate 5 according to (FPGA of high-speed line plate 1 also is provided with the Request ID of its this plate correspondence in PCIe packet header) in the PCIe packet header.The FPGA of high-speed line plate 5 according in the PCIe packet header of the PCIe packet that receives corresponding to the Request ID of high-speed line plate 1, identify this PCIe packet from high-speed line plate 1, and high-speed line plate 1 corresponding port address 1 is arranged at port address in the control word of SPI4.2 packet, to comprise that then this SPI4.2 of data in the PCIe packet that receives is sent to the CPU of this plate, the CPU of this plate can identify data in this SPI4.2 packet from high-speed line plate 1 according to the port address in the control word of SPI4.2 packet 1.

Because target single board can identify the source veneer of the PCIe packet that receives, and therefore, can also carry out Flow Control to the source veneer.Below, the flow control procedure between veneer in the said system is elaborated.

Fig. 6 is a schematic diagram of realizing Flow Control between plate in the embodiment of the invention based on bus interface data converted transmission system.Shown in Figure 6 is identical with Fig. 5 based on bus interface data converted transmission system structure.

When as the CPU of the high-speed line plate of target single board handle near or when surpassing its load, cause this high-speed line plate congested.At this moment, the CPU of this high-speed line plate promptly can produce the FPGA that flow-control information (for example back-pressure signal) is sent to this plate to the FPGA of this plate by SPI4.2 bus interface fifo status passage as shown in Figure 2, because this CPU can be known the source veneer of the data that it receives, the port address that therefore, can also comprise the source veneer in the flow-control information.

The FPGA of high-speed line plate is behind the flow-control information that receives from this plate CPU, send the congested PCIe Flow Control bag of this plate of expression to the PCIe switch, and can comprise the address that causes congested source veneer (address of this source veneer is promptly as the destination address of PCIe Flow Control bag) in this PCIe Flow Control bag, this address can obtain according to default port address and veneer address lookup.

The PCIe switch is sent to corresponding target single board according to the destination address of PCIe Flow Control bag with this PCIe Flow Control bag, promptly causes congested source high-speed line plate.

After the FPGA of this source high-speed line plate receives PCIe Flow Control bag, can the flow-control information of correspondence be sent to the CPU of this plate by SPI4.2 bus interface fifo status passage as shown in Figure 2, and according to the corresponding relation of the destination address in the PCIe Flow Control bag (this moment destination address be this plate address of source high-speed line plate) and port address and veneer address, this plate corresponding port address is set in this flow-control information, need adjust with the flow of representing this plate, thereby realize that target high-speed line plate is to Flow Control between the plate between the high-speed line plate of source.

Like this, as shown in Figure 6, among the FIFO of the FPGA of each high-speed line plate, all stored the formation of two bags, one of them PCIe data packet queue that receives and store as target single board for this high-speed line plate (can regard the Data Receiving address as, be the fifo queue of foregoing target single board address correspondence), another PCIe Flow Control bag formation that receives and store as the source veneer for this high-speed line plate (can regard Flow Control bag receiver address as, be the fifo queue of foregoing Request ID correspondence).

With the data transfer path shown in the double-head arrow dotted line among Fig. 6 is example, supposes that High-Speed Data Line plate 1 sent out a large amount of PCIe packets to high-speed line plate 5, causes high-speed line plate 5 congested.At this moment, the CPU of high-speed line plate veneer 5 is by the port address in its SPI4.2 packet that receives, identifying the source veneer that causes blocking is high-speed line plate 1, therefore the fifo status passage by the SPI4.2 bus interface sends flow-control information to the FPGA of this plate, can comprise high-speed line plate 1 corresponding port address in this flow-control information.The FPGA of high-speed line plate 5 is after receiving flow-control information, send PCIe Flow Control bag (address that comprises high-speed line plate 1 in the PCIe packet header of this PCIe Flow Control bag) by the PCIe switch to high-speed line plate 1, destination address in this PCIe Flow Control bag is the address of high-speed line plate 1, is to be searched according to the corresponding relation of the port address of its maintenance and veneer address by the FPGA of high-speed line plate 5 to get.

The FPGA of high-speed line plate 1 is after receiving this PCIe Flow Control bag, be stored in earlier in the Flow Control bag formation as shown in Figure 6, by the stator channel of SPI4.2 bus interface the Flow Control message of correspondence is sent to the CPU of this plate then, need adjust with the flow of representing this plate, thereby finish the Flow Control of 5 pairs of high-speed line plates 1 of high-speed line plate.

Above-mentioned Flow Control mode can be regarded a kind of SPI4.2 Flow Control based on the PCIe bussing technique as.

As seen, the system in the present embodiment can reduce congested probability has taken place in the veneer based on the SPI4.2 Flow Control between PCIe bus realization veneer, thereby has improved the reliability of this system.

In the practical application, PCIe switch inside also may take place congested.For example, high-

speed line plate

1,2,3,4 all sends the PCIe packet by the PCIe switch to high-speed line plate 5, thereby causes the congested of PCIe switch inside.In this case, flow-control mechanism is different from the Flow Control between foregoing veneer.

If the inner generation of PCIe switch congested (sending the PCIe packet to same target high-speed line plate such as polylith source high-speed line plate), then the PCIe exchange opportunity sends PCIe Flow Control bag to source high-speed line plate.

At this moment, directly (can be if the high-speed line plate receives according to existing mode from the PCIe Flow Control bag of its upstream PCIe switch, or other the default signs in the PCIe Flow Control bag are distinguished the PCIe Flow Control bag that receives whether for directly from the PCIe switch), then the FPGA of this high-speed line plate still can send corresponding flow-control information to the CPU of this plate by the fifo status passage of SPI4.2 bus interface, but the port address in this Flow Control message is that (promptly another except that the every pairing port address of veneer arranged port address in a universal port address, in order to represent this plate, for example 0).The CPU of this plate is according to the universal port address in the flow-control information, and it is congested to know that this plate has caused, the flow of this plate need be adjusted.

As seen, the system in the present embodiment can realize the SPI4.2 Flow Control of PCIe switch to veneer based on the PCIe bus, has reduced the congested probability of the inner generation of PCIe switch, thereby has improved the reliability of this system.

Present embodiment all is to be that PCIe switch, veneer comprise that the CPU of master control borad and high-speed line plate, master control borad supports the CPU of PCIe bus interface, high-speed line plate to support that the SPI4.2 bus interface is an example with the switching equipment of supporting the PCIe bus.In the practical application, support the switching equipment of PCIe bus also can be router, veneer also can comprise the wiring board of other types, if and the CPU of master control borad do not support the PCIe bus interface, then also can realize transmitting according to the mode identical with high-speed line plate in the present embodiment based on the bus interface data converted; And the bus interface transducer also can be realized by other programmable logical devices except realizing by FPGA.

More than, be in the embodiment of the invention based on the detailed description of bus interface data converted transmission system and veneer, below, again to describing based on bus interface data converted transmission method in the embodiment of the invention.

Fig. 7 is based on the schematic flow sheet of bus interface data converted transmission method in the embodiment of the invention.As shown in Figure 7, based on foregoing system, high-speed line plate and master control borad are referred to as veneer, may further comprise the steps based on bus interface data converted transmission method in the present embodiment:

Step 701, the veneer processor of source veneer is according to the port address that sets in advance and the corresponding relation of veneer, to comprise the port address in the control word of SPI packet of data to be sent, be set to the pairing port address of target single board of data to be sent, and this SPI packet be sent to the bus interface transducer of this plate.

In this step, before sending the PCIe packet by the PCIe interface, the bus interface transducer of source veneer is also in the PCIe packet header of PCIe packet, add the default Flow Control bag receiver address of its this plate, Request ID in for example foregoing PCIe packet header, can identify the source veneer in order to the target single board that receives this PCIe packet, and the source veneer is carried out Flow Control between plate.

In the practical application,, then need not to carry out this processing, also need not to carry out follow-up step 703～step 706 if need not to carry out Flow Control between veneer, can direct process ends after step 702.

Step 702, the data to be sent that the bus interface transducer of source veneer will be received from the SPI packet of veneer processor of this plate are added in the PCIe packet, according to the port address in the control word of the SPI packet that receives, and the corresponding relation of port address that sets in advance and veneer address, determine veneer address as datum target to be sent address, determined veneer address is added in the PCIe packet header of PCIe packet, and in PCIe packet header, also add the Flow Control bag receiver address of this plate correspondence, send the PCIe packet by the PCIe bus interface to the switching equipment of supporting the PCIe bus then.

Above-mentioned steps 701～702 has realized sending out outward based on the bus interface data converted, and because the veneer processor utilizes the port address of SPI4.2 control word in the SPI4.2 packet to represent the target single board of data to be sent, and only in the SPI4.2 data message that sends to this plate bus interface transducer, add data to be sent, and no longer add PCIe packet header, thereby improved the bandwidth availability ratio in the plate.

Step 703, the bus interface transducer of target single board is according to its PCIe packet that receives by the switching equipment of supporting the PCIe bus, veneer processor to this plate sends the SPI packet, and, veneer corresponding port address, source is set in the SPI packet of the veneer processor that sends to this plate according to Flow Control bag receiver address that sets in advance and corresponding relation corresponding to the port address of veneer.

Step 704, the veneer processor of target single board identifies the source veneer according to the port address in the SPI packet that receives, and takes place when congested at this plate, sends the flow-control information of the port address that comprises corresponding source veneer to the bus interface transducer of this plate.

Step 705, the bus interface transducer of target single board sends PCIe Flow Control bag according to from the veneer processor of this plate and comprised the flow-control information of veneer corresponding port address, source to the source veneer, comprises the veneer address of source veneer in this PCIe Flow Control bag.

In this step, the veneer address of the source veneer that comprises in the PCIe Flow Control bag is to determine according to the corresponding relation of port address and veneer address.

Step 706, after the bus interface transducer of source veneer receives PCIe Flow Control bag by the switching equipment of supporting the PCIe bus, veneer processor to this plate sends corresponding flow-control information, and according to the corresponding relation of port address and veneer address, the pairing port address of this plate is set in the flow-control information of the veneer processor that sends to this plate, need adjusts with the flow of representing this plate.

Above-mentioned steps 703～step 706 has realized that promptly target single board is to Flow Control between the plate of source veneer.

So far, this flow process finishes.

After the step 702 of above-mentioned flow process, if after supporting that switching equipment portion's generation within it of PCIe bus is congested, then can send PCIe Flow Control bag to the bus interface transducer of source veneer.Like this, the bus interface transducer of source veneer is according to direct PCIe Flow Control bag from switching equipment, veneer processor to this plate sends corresponding flow-control information, and default universal port address is set in the flow-control information of the veneer processor that sends to this plate, need adjust with the flow of representing this plate, thereby realize the Flow Control of switching equipment veneer.

By above-mentioned flow process as seen, not only can improve bandwidth availability ratio based on bus interface data converted transmission method in the present embodiment, can also realize Flow Control between veneer and switching equipment Flow Control to veneer, promptly when having improved bandwidth availability ratio, also reduce the probability of happening of system congestion, further improved reliability of data transmission.

Be example all in the above embodiment of the present invention with the SPI4.2 bus interface, in the practical application, if comprise port address in the control word of the SPI packet of other versions, then the technical scheme in the foregoing description also goes for the spi bus interface of other versions, and principle is same as the previously described embodiments.

The above is preferred embodiment of the present invention only, is not to be used to limit protection scope of the present invention.Within the spirit and principles in the present invention all, any modification of being done, be equal to and replace and improvement etc., all should be included within protection scope of the present invention.

Claims

1. veneer that improves bandwidth availability ratio comprises: veneer processor and bus interface transducer by the SPI4.2 bus interface links to each other, it is characterized in that,

2. veneer as claimed in claim 1 is characterized in that, described bus interface transducer further in the PCIe packet header of the PCIe packet that sends, adds the veneer sign of its place veneer correspondence.

3. veneer as claimed in claim 1 is characterized in that,

4. veneer as claimed in claim 1 is characterized in that,

5. as any described veneer in the claim 3 to 4, it is characterized in that described bus interface transducer further links to each other with the outside switching equipment of its place veneer, the quick peripheral component interconnect Standard PC of described switching equipment support Ie bus;

6. veneer that improves bandwidth availability ratio comprises: veneer processor and bus interface transducer by the SPI4.2 bus interface links to each other, it is characterized in that,

7. veneer as claimed in claim 6 is characterized in that,

8. data transmission system that improves bandwidth availability ratio comprises: support switching equipment, source veneer and the target single board of quick peripheral component interconnect Standard PC Ie bus, wherein,

It is characterized in that,

9. system as claimed in claim 8 is characterized in that, the bus interface transducer of source veneer further in the PCIe packet header of the PCIe packet that sends, adds the veneer sign of described source veneer correspondence;

10. system as claimed in claim 9, it is characterized in that, receive described PCIe Flow Control bag by described switching equipment after, the bus interface transducer of described source veneer further sends corresponding flow-control information to the veneer processor of described source veneer, and according to the corresponding relation of described port address and veneer address, veneer pairing port address in described source is set in the flow-control information of the veneer processor that sends to described source veneer, need adjusts with the flow of representing described source veneer.

11. as any described system in the claim 8 to 10, it is characterized in that, after the portion's generation within it of described switching equipment is congested, to the bus interface transducer transmission PCIe of source veneer Flow Control bag;

12. a data transmission method that improves bandwidth availability ratio is characterized in that, this method comprises:

13. method as claimed in claim 12 is characterized in that, before sending described PCIe packet by its PCIe bus interface, this method further comprises:

14. method as claimed in claim 12 is characterized in that, this method further comprises:

15. method as claimed in claim 12 is characterized in that, this method further comprises:

16., it is characterized in that described veneer sign is the request identify label Request ID in the described PCIe packet header as any described method in the claim 13 to 15.

17. a data transmission method that improves bandwidth availability ratio is characterized in that, this method comprises:

18. method as claimed in claim 17 is characterized in that, identifies after other veneers of described outside, this method further comprises:

19. a data transmission method that improves bandwidth availability ratio is characterized in that, this method comprises:

20. method as claimed in claim 19 is characterized in that, describedly sends before the described PCIe packet by the PCIe interface, this method further comprises: