CN101202226B - Integrated method for improving metal former medium PMD filling characteristic - Google Patents

Integrated method for improving metal former medium PMD filling characteristic Download PDF

Info

Publication number
CN101202226B
CN101202226B CN200610119408A CN200610119408A CN101202226B CN 101202226 B CN101202226 B CN 101202226B CN 200610119408 A CN200610119408 A CN 200610119408A CN 200610119408 A CN200610119408 A CN 200610119408A CN 101202226 B CN101202226 B CN 101202226B
Authority
CN
China
Prior art keywords
side wall
etching
bpsg
deposit
polysilicon
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Active
Application number
CN200610119408A
Other languages
Chinese (zh)
Other versions
CN101202226A (en
Inventor
陈昊瑜
龚顺强
缪炳有
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Shanghai IC R&D Center Co Ltd
Shanghai Huahong Grace Semiconductor Manufacturing Corp
Original Assignee
Shanghai Hua Hong NEC Electronics Co Ltd
Shanghai Integrated Circuit Research and Development Center Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Shanghai Hua Hong NEC Electronics Co Ltd, Shanghai Integrated Circuit Research and Development Center Co Ltd filed Critical Shanghai Hua Hong NEC Electronics Co Ltd
Priority to CN200610119408A priority Critical patent/CN101202226B/en
Publication of CN101202226A publication Critical patent/CN101202226A/en
Application granted granted Critical
Publication of CN101202226B publication Critical patent/CN101202226B/en
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Images

Abstract

The invention discloses an integration method for enhancing the filling characteristic of a metal antemedium PMD. The method of the invention includes: firstly a layer of a heated oxidation film is generated on a silicon basic board; a layer of polysilicon (1) is settled for etching; silicon nitride or silicon oxide is settled to form a side wall after etching; after the forming of the side wall,SiN is settled as a liner (5); finally BPSG is settled; however, the appearance of the side wall formed by the invention is inclined; the inclined appearance of the side wall can lead the polysiliconbottom to be provided with an inclined appearance of about 80 degrees angle through changing the etching conditions of the polysilicon or lead the shoulder of the side wall to fall down to form the inclined appearance of the side wall through increasing the ratios of anisotropic etching in the side wall etching process. The invention can compensate the defects or limits of the filling capability of BPSG process, so as to avoid the emergence of PMD void. The invention can be applied to the integration process of semiconductors which is of 0.18 microns or less than 0.18 microns.

Description

A kind of integrated approach that improves metal former medium PMD filling characteristic
Technical field
The present invention relates to a kind of semiconductor fabrication process, relate in particular to a kind of integrated approach that improves metal former medium PMD filling characteristic.
Background technology
Before-metal medium layer PMD generally is made up of three layers of medium, as liner SiN (silicon nitride) or SiON (silicon oxynitride)+BPSG (Borophosphosilicate glass, boron phosphor silicon oxide)+SiO 2(silicon dioxide) or SiON.The main effect of liner SiN or SiON is to stop B (boron) and P (phosphorus) to be diffused into silicon substrate, thereby influences device performance; The effect of BPSG is a gettering---absorb or catch from the metal ion/hydrogen ion of postchannel process and other impurity, prevent to be diffused into silicon substrate; Surface SiO 2The main effect of (silicon dioxide) or SiON is that protection BPSG acidifying/boron phosphorus is separated out.Usually industrial quarters adopts SA (inferior normal pressure) BPSG.
Along with reducing of device size, the filling a vacancy property of BPSG becomes one of focus of industry concern before the metal.In 0.18um and following technology, special in containing the storage component part technology of double level polysilicon, the aspect ratio logical device height of polysilicon, and the spacing between the polysilicon is dwindled, both ratio is bigger.The filling a vacancy property of original SA BPSG is subjected to challenge (having the cavity to occur), maybe can not satisfy technological requirement; Because should the cavity if appear at the sidewall of interconnected pores, barrier layer Ti/TiN can not cover the cavity, in the deposition process of tungsten plug, can etching sidewall BPSG from the F ion of gas WF6, thus may cause interconnect failure and device performance reduction etc.Because the requirement of filling a vacancy property, people also adopt HDP PSG (high-density plasma is mixed phosphor silicon oxide), and this filling a vacancy property of technology is good; But its shortcoming is a technology cost height.So unless have no alternative but, people always select the lower-cost SA BPSG of technology.In order to prolong the technology life-span of SA BPSG, people always try every means and improve the filling a vacancy property of PMD integral body.In general, PMD the cavity occurs and has following five reasons at least: the ability of filling a vacancy of SA BPSG technology itself has much room for improvement or optimizes; BPSG's covers type sexual needs optimization; Liner SiN or SiON technology have to be optimized; Annealing process needs to optimize; Silicide process needs to optimize.
Summary of the invention
The technical problem to be solved in the present invention provides a kind of integrated approach that improves metal former medium PMD filling characteristic, remedies the deficiency or the finiteness of the filling capacity of BPSG technology own, thereby avoids the generation in PMD cavity.
For solving the problems of the technologies described above, the present invention improves the integrated approach of the preceding medium filling characteristic of metal, and described before-metal medium layer is made up of three layers of medium, and described three layers of medium are respectively liner, BPSG, SiO 2Or SiON, described integrated approach comprises: one deck heat oxide film of at first growing on silicon substrate; Deposit one deck polysilicon and carry out etching again; Deposit silicon nitride or silica form side wall after the etching; Form behind the side wall deposit SiN or SiON as liner, last deposit BPSG; But it is what tilt that the present invention forms the pattern of side wall; The pattern that forms side wall can be by changing the etching condition of polysilicon for what tilt, and making the polysilicon bottom have angle is inclination pattern about 80 degree; Also by increasing the ratio of anisotropic etching in the side wall etching, the pattern that makes the decline of side wall shoulder position form side wall tilts.The inventive method can be applicable to 0.18 micron and following semiconductor integrated technique.
The inventive method has improved the type that covers of BPSG owing to change two kinds of etching technics menus, can improve the rate of finished products and the reliability of corresponding product.
Description of drawings
Fig. 1 is the formation step of PMD under the traditional handicraft method;
Fig. 2 is the formation step of PMD under the inventive method;
Reference numeral: 1, polysilicon, 2, heat oxide film, 3, silicon substrate, 4, side wall, 5, liner, 6, BPSG.
Embodiment
The present invention is further detailed explanation below in conjunction with the drawings and specific embodiments.
At first tell about principle of the present invention.The filling step of BPSG is as follows in traditional semiconductor technology: 1, on liner SiN or SiON at first deposit cover the type film; 2, deposit is filled to intermediate gaps from film on every side; 3, make BPSG reflow through thermal annealing, further fill the gap.In 0.18 micron technology, in order to reduce the influence of thermal process to device, thermal annealing after the BPSG deposit from before stove annealing (general 700-800 degree, about 30 minutes time) change rapid thermal anneal process (general~700 degree /~30 seconds) into, rapid thermal anneal process RTP does not almost have too big improvement to the filling a vacancy property of BPSG technology under this kind situation; In addition, by adjusting the B/P ratio in the BPSG technology, can optimize the porefilling capability of BPSG itself; But because BPSG grows up and its to cover type relevant, isolate in the mortise at the polycrystalline of high depth-width ratio, if the pattern of side wall itself is steep, can make BPSG in filling process, form a sealing cavity, the above-mentioned BPSG of improvement process conditions and annealing conditions all can't thoroughly be eliminated the cavity, at this situation, we have proposed novel integrated approach at the optimization that BPSG covers type.Promptly the side wall pattern of Qing Xieing can reduce to form the probability in sealing cavity, provides a kind of new PMD integrated approach as starting point, to satisfy 0.18 micron and following technological requirement.And the side wall pattern that will obtain tilting can be realized from following two kinds of methods: 1, directly optimize the side wall etching condition, and form the pattern of inclination as far as possible.This can make it that side wall shoulder position is descended and obtain by increasing the ratio of anisotropic etching in the side wall etching; 2, change the etching polysilicon condition, make it form the pattern (as figure) that tilts, also helpful to obtaining the side wall pattern.This polycrystalline silicon etching process can be used for reference the lithographic method that the short groove of ditch is isolated (STI), makes it form the preceding dielectric isolation mortise of the metal that tilts.Comprise: change the pattern of polycrystal etching and the pattern of side wall etching.
Fig. 1 is the formation step of PMD under the traditional handicraft method; As shown in the figure, long one deck heat oxide film 2 on silicon substrate 3 at first; Deposit one deck polysilicon 1 again; Be the etching of polysilicon then; Deposit side wall nitride silicon and silica form side wall 4 after the etching; Side wall forms back deposit SiN as liner 5, last deposit BPSG 6.The pattern of side wall is steep among Fig. 1, forms the sealing cavity easily.
Fig. 2 then is the formation step of PMD under the inventive method.Be that with the difference of traditional approach among Fig. 1 the change of polycrystal etching and side wall etching to form the pattern of inclination, helps the filling of BPSG.The present invention selects the etching polysilicon at 80 degree angles of inclination for use; Can use for reference the lithographic method of ripe shallow trench isolation (STI); Reduced technology difficulty.
Tell about the present invention below in conjunction with embodiment.
Embodiment one: what adopt this method in the present embodiment is that a kind of double-layered polycrystal thickness is the storage component part of 3500A (dust) altogether.Be spaced apart 0.54um between its polycrystalline, the structure of side wall (Spacer) is the SiO of 100A 2Add the SiN of 1000A.Under traditional PMD formation method, be easy to occur cavity (Void).Adopt SiN among the EMAX base station etching Spacer in an embodiment, increase anisotropic etching gas, thereby can realize the spacer pattern that tilts.And type is covered in the BPSG that the spacer pattern that tilts improves filling, thereby has solved the Void problem.
Embodiment two: if the design rule of device further reduces, in order further to improve the filling characteristic of PMD, can increase the etching angle of polysilicon (Poly), consider the control problem of CD after the Poly etching, the etching angle of Po1y is decided to be about 80 degree, similar with the etching angle of short trench isolations (STI). use for reference the etching condition of STI, promptly in the poly etching, increase etching polymer, increasing the O2 content in the etching gas, can realize the pattern of poly etching rear-inclined. its result also is the filling capacity that equally helps improving BPSG.
The inventive method can be applicable to 0.18 micron and following semiconductor integrated technique.

Claims (2)

1. integrated approach that improves medium filling characteristic before the metal, described before-metal medium layer is made up of three layers of medium, and described three layers of medium are respectively liner, BPSG, SiO 2Or SiON, described integrated approach comprises: one deck heat oxide film of at first growing on silicon substrate; Deposit one deck polysilicon and carry out etching again; Deposit silicon nitride or silica form side wall after the etching; Form behind the side wall deposit SiN or SiON as liner, last deposit BPSG; It is characterized in that described deposit one deck polysilicon also carries out changing the etching condition of described polysilicon in the process of etching, make the polysilicon bottom have the inclination pattern that angle is 80 degree;
Described deposit silicon nitride or silica also form after etching in the process of side wall, and by increasing the ratio of anisotropic etching in the side wall etching, the pattern that makes the decline of side wall shoulder position form side wall tilts.
2. the integrated approach that improves the preceding medium filling characteristic of metal according to claim 1 is characterized in that this method is applied to 0.18 micron and following semiconductor integrated technique.
CN200610119408A 2006-12-11 2006-12-11 Integrated method for improving metal former medium PMD filling characteristic Active CN101202226B (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
CN200610119408A CN101202226B (en) 2006-12-11 2006-12-11 Integrated method for improving metal former medium PMD filling characteristic

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN200610119408A CN101202226B (en) 2006-12-11 2006-12-11 Integrated method for improving metal former medium PMD filling characteristic

Publications (2)

Publication Number Publication Date
CN101202226A CN101202226A (en) 2008-06-18
CN101202226B true CN101202226B (en) 2010-05-12

Family

ID=39517295

Family Applications (1)

Application Number Title Priority Date Filing Date
CN200610119408A Active CN101202226B (en) 2006-12-11 2006-12-11 Integrated method for improving metal former medium PMD filling characteristic

Country Status (1)

Country Link
CN (1) CN101202226B (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN110718533A (en) * 2019-10-08 2020-01-21 上海集成电路研发中心有限公司 Sunken structure convenient for online monitoring and preparation method thereof

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN102446740B (en) * 2011-08-29 2013-09-11 上海华力微电子有限公司 Integrated process for improving gap fill property of PMD (pre-metal dielectric)
CN104377130B (en) * 2013-08-16 2017-12-05 上海华虹宏力半导体制造有限公司 The method of growth high reliability IGBT metal connections
CN110828307A (en) * 2019-10-16 2020-02-21 中芯集成电路制造(绍兴)有限公司 Method for forming material layer with inclined side wall and semiconductor device

Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1039151A (en) * 1988-06-29 1990-01-24 菲利浦光灯制造公司 Method, semi-conductor device manufacturing method
CN1154570A (en) * 1995-07-28 1997-07-16 日本电气株式会社 MOS field effect transistor with improved pocket regions for suppressing any short channel effects and method for fabricating the same
US6740549B1 (en) * 2001-08-10 2004-05-25 Integrated Device Technology, Inc. Gate structures having sidewall spacers using selective deposition and method of forming the same
CN1553968A (en) * 2001-07-20 2004-12-08 应用材料有限公司 Method and apparatus for deposition of boron-phosphorus silicate glass
CN1767156A (en) * 2004-10-29 2006-05-03 海力士半导体有限公司 Method for fabricating semiconductor device with gate spacer
CN1832125A (en) * 2005-02-24 2006-09-13 台湾积体电路制造股份有限公司 Hdp-cvd methodology for forming pmd layer

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1039151A (en) * 1988-06-29 1990-01-24 菲利浦光灯制造公司 Method, semi-conductor device manufacturing method
CN1154570A (en) * 1995-07-28 1997-07-16 日本电气株式会社 MOS field effect transistor with improved pocket regions for suppressing any short channel effects and method for fabricating the same
CN1553968A (en) * 2001-07-20 2004-12-08 应用材料有限公司 Method and apparatus for deposition of boron-phosphorus silicate glass
US6740549B1 (en) * 2001-08-10 2004-05-25 Integrated Device Technology, Inc. Gate structures having sidewall spacers using selective deposition and method of forming the same
CN1767156A (en) * 2004-10-29 2006-05-03 海力士半导体有限公司 Method for fabricating semiconductor device with gate spacer
CN1832125A (en) * 2005-02-24 2006-09-13 台湾积体电路制造股份有限公司 Hdp-cvd methodology for forming pmd layer

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
JP特开平7-94718A 1995.04.07

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN110718533A (en) * 2019-10-08 2020-01-21 上海集成电路研发中心有限公司 Sunken structure convenient for online monitoring and preparation method thereof
CN110718533B (en) * 2019-10-08 2021-01-29 上海集成电路研发中心有限公司 Sunken structure convenient for online monitoring and preparation method thereof

Also Published As

Publication number Publication date
CN101202226A (en) 2008-06-18

Similar Documents

Publication Publication Date Title
US4952524A (en) Semiconductor device manufacture including trench formation
KR101426483B1 (en) Method for fabricating semiconductor device
US6677247B2 (en) Method of increasing the etch selectivity of a contact sidewall to a preclean etchant
US6602748B2 (en) Method for fabricating a semiconductor device
US5661334A (en) Inter-metal dielectric structure which combines fluorine-doped glass and barrier layers
US6277730B1 (en) Method of fabricating interconnects utilizing fluorine doped insulators and barrier layers
CN101202226B (en) Integrated method for improving metal former medium PMD filling characteristic
US6911394B2 (en) Semiconductor devices and methods of manufacturing such semiconductor devices
KR100703968B1 (en) Method for fabricating interconnection line in a semiconductor device
US6358785B1 (en) Method for forming shallow trench isolation structures
KR100815952B1 (en) Method for forming intermetal dielectric in semiconductor device
JP2003124144A (en) Processing method for semiconductor chip
US7052970B2 (en) Method for producing insulator structures including a main layer and a barrier layer
JP3771048B2 (en) Method for planarizing semiconductor structure and method for filling gap between adjacent gate electrodes of semiconductor structure
EP0875929A2 (en) Planarisation of an interconnect structure
KR20010051285A (en) Hdp capping layer or polish layre over hsq/peteos ild stack to enhance planarity and gap-fill
WO1997012393A1 (en) Capped interlayer dielectric for chemical mechanical polishing
US6489253B1 (en) Method of forming a void-free interlayer dielectric (ILD0) for 0.18-μm flash memory technology and semiconductor device thereby formed
KR100596277B1 (en) Semiconductor device and method of manufacturing dielectric layer thereof
KR100314275B1 (en) Manufacturing method of semiconductor device
US7939855B2 (en) Semiconductor device
US7834427B2 (en) Integrated circuit having a semiconductor arrangement
KR100855285B1 (en) Method of manufacturing semiconductor device
US7528063B2 (en) Semiconductor device having a reductant layer and manufacturing method thereof
Bakli et al. Materials and processing for 0.25 μm multilevel interconnect

Legal Events

Date Code Title Description
C06 Publication
PB01 Publication
C10 Entry into substantive examination
SE01 Entry into force of request for substantive examination
C14 Grant of patent or utility model
GR01 Patent grant
ASS Succession or assignment of patent right

Owner name: SHANGHAI HUAHONG GRACE SEMICONDUCTOR MANUFACTURING

Free format text: FORMER OWNER: HUAHONG NEC ELECTRONICS CO LTD, SHANGHAI

Effective date: 20140121

C41 Transfer of patent application or patent right or utility model
COR Change of bibliographic data

Free format text: CORRECT: ADDRESS; FROM: 201206 PUDONG NEW AREA, SHANGHAI TO: 201203 PUDONG NEW AREA, SHANGHAI

TR01 Transfer of patent right

Effective date of registration: 20140121

Address after: 201203 Shanghai city Zuchongzhi road Pudong New Area Zhangjiang hi tech Park No. 1399

Patentee after: Shanghai Huahong Grace Semiconductor Manufacturing Corporation

Patentee after: Shanghai integrated circuit research and Development Center Co., Ltd.

Address before: 201206, Shanghai, Pudong New Area, Sichuan Road, No. 1188 Bridge

Patentee before: Shanghai Huahong NEC Electronics Co., Ltd.

Patentee before: Shanghai integrated circuit research and Development Center Co., Ltd.