CN101201852A - SPICE model method for proportional contraction technique - Google Patents

Abstract

The invention discloses a SPICE model method used for equal-ratio scaling down technique, which includes the following steps: step 1, the measurement of the model data is carried out; step 2, the extraction of the model parameter is carried out; step 3, the model is emulated; in the step 2, better model extracting result can be achieved by setting the physical parameter of a special SPICE model, transforming the designed values of the width and length of the transistor in practical technique into practical values according to a certain computational method, simultaneously transforming junction capacitance and gate capacitance into practical values according to proportion and reflecting the physical dimension sinking in the model parameter. The invention simplifies operation and reduces the error probability thereof, which is extremely convenient for both the model extraction and the model user.

Description

The SPICE model method that is used for scaled down technology

Technical field

The present invention relates to a kind of integrated circuit semiconductor apparatus model generating method, relate in particular to a kind of SPICE model generating method that is used for scaled down technology (Shrink technology).

Background technology

In order to improve the technology competitive power, dwindle chip area, often take on the basis of existing maturation process, by a certain percentage design rule and size to be dwindled (shrink), form a new semiconductor technology platform; The deviser of this platform uses the design load before dwindling to carry out circuit design and emulation, and in the physical size that forms on the silicon chip after dwindling, if use conventional model extraction method, its model is difficult to extract.As shown in Figure 1, existing SPICE model method mainly may further comprise the steps: step 1, and model data is measured; Step 2, model parameter extraction; Step 3 model emulation.At scaled technology, existing SPICE modelling technique generally takes to be provided with option scale (selecting ratio)=" shrink value " (dwindling value) in emulation (Simulation) net table (Netlist), promptly in the net table, add the Scale coefficient, allow emulation tool on the basis of design load, calculate the actual physical size of device automatically according to shrinkvalue, and before model parameter extraction, when being the measurement of step 1 model data, must be designs value (channel length, channel width etc.) be converted to actual value, be input to model data and measure in the file, carry out step 2 model parameter extraction then.

This model method is fairly simple, and is directly perceived, can satisfy a few thing of simple conventional device model, but two shortcomings are arranged:

1, when step 1 model data is tested, must be converted to actual value to the relevant design load of all size of devices, in the model parameter extraction flow process, occur mistake easily;

2, under the shrink situation of relative complex, models treated is difficulty relatively, for example, and the scaled one-tenth 0.9 of certain technology, but 0.1um (micron) can be amplified in long (gate length) the every limit of transistor gate; Secondly also have some special transistor device on common BSIM model based, to carry out modelling (for example high-pressure process) by more plug-in electronic circuits (SUBCKT circuit), use the shrink coefficient to carry out modelling and can bring unfavorable factor.

Summary of the invention

The technical problem to be solved in the present invention provides a kind of SPICE model method that is used for scaled down technology, this method has realized that the SPICE model that carries out Shrink technology with conventional BSIM model extracts, and this method is all very convenient to model extraction and model user both sides.

For solving the problems of the technologies described above, the invention provides a kind of SPICE model method that is used for scaled down technology, comprise the steps: step 1, model data is measured; Step 2, model parameter extraction; Step 3 model emulation; In step 2, the SPICE model parameter is set, and the design load in the actual process is converted to actual value, the reduction volume of physical size is reflected in the model parameter.

Described in the step 2 the SPICE model parameter is set,, comprises parameter and the relevant parameter of electric capacity that DC characteristic is relevant by in conventional BSIM model, choosing following physical parameter.

Design load as follows that transistor is wide and long in step 2 is converted to actual value: following four parameter l ln=-1 are set, wwn=-1, ll=0.5* (1-ratio), ww=0.5* (1-ratio) is a fixed value, (1) as follows～(4) are converted to actual value with design load:

Wherein, ratio is the technology scale down, Leff is that transistorized effective raceway groove is long, Weff is that transistorized effective raceway groove is wide, L is the design load of crystal pipe range, W is the wide design load of transistor, and DL, Lint, lw, lwn, lwl, lln, lwn, DW, Wint, wl, wln, wwl, wln, wwn, ll and ww are the relevant parameter of DC characteristic.

In step 2, as follows the design load of junction capacity and gate capacitance is converted to actual value: junction capacity, by choosing Cj, Cjsw, the Cjswg parameter multiply by coefficient ratio; Gate capacitance by choosing electric capacity correlation model parameter, is provided with llc=ll=0.5* (1-ratio), wwc=ww=0.5* (1-ratio), (a) as follows～(d) design load is converted to actual value:

Wherein, ratio is the technology scale down, Leffc is that transistorized effective raceway groove is long, Weffc is that transistorized effective raceway groove is wide, L is the design load of crystal pipe range, W is the wide design load of transistor, and DL, DLC, lwc, lwn, lwlc, lln, lwn, DW, DWC, wlc, wln, wwlc, wln, wwn, llc and wwc are electric capacity correlation model parameter.

Compare with prior art, the present invention has following beneficial effect: the present invention utilizes the setting of conventional BSIM model parameter value, realize the conversion that all sizes are relevant and the modelling of characteristic, by in conventional BSIM model, choosing following physical parameter, comprise the relevant parameter of DC characteristic, parameter that electric capacity is relevant etc., according to the variation of design load in the actual process to actual value, the Shrink of physical size amount is reflected in the model parameter, realize the model parameter extraction of scaled down technology.By the setting to specific SPICE model physical parameter, the wide and long design load of transistor is converted to actual value according to certain calculation method, simultaneously junction capacity and gate capacitance also is converted to actual value in proportion, extracts the result thereby reach good model.This method has been simplified operation, and has reduced the wrong probability of operation, and is all very convenient to model extraction and model user both sides.

Description of drawings

Fig. 1 is existing SPICE model method process flow diagram;

Fig. 2 is the process flow diagram that the present invention is used for the SPICE model method of Shrink technology.

Embodiment

The present invention is further detailed explanation below in conjunction with drawings and Examples.

As shown in Figure 2, a kind of SPICE model method that is used for Shrink technology of the present invention comprises the steps: step 1, and model data is measured; Step 2, model parameter extraction; Step 3 model emulation.The starting point of this method is in the inner conversion that all sizes are relevant and the modelling of characteristic of realizing of BSIM model, therefore, only uses design load in step 1 model data is measured; In step 2 model parameter extraction,, comprise the parameter L int that DC characteristic is relevant by in conventional BSIM model, choosing following physical parameter, Wint, Dlc, Dwc, ll, lln, ww, wwn, llc, wwc, Hdif etc., and electric capacity correlation parameter CGDO, CGSO, CGDL, CGSL, CJ, CJSW, CJSWG etc. will be according to the variation of design load in the actual process to actual value, the Shrink of physical size amount is reflected in the model parameter, makes that the user need not be concerned about the Scale coefficient when step 3 model emulation.

1. DC characteristic model parameter:

In general BSIM model, ll, lln, ww, wwn generally are used for Short/narrow (short/narrow) transistor model parameter IV curve fitting (fitting) and use, be traditionally arranged to be lln=1, wwn=1, with ll and the transistorized effective raceway groove of ww parameter regulation Short/narrow long (Leff) and effective raceway groove wide (Weff), two parameters can be ignored to large (greatly) transistors influence, but very big to the Short/narrow transistors influence, its computing formula is as follows:

Leff＝L-2*DL. -------(2)

Weff＝W-2*DW. ------(4)

In the present invention, by flexible Application to parameter, give the BSIM model parameter new meaning, the Shrink value of transistor L (length) and W (wide) by the model parameter setting, generally speaking, the long Lwafer=Ldesign*ratio of actual raceway groove of Shrink technology, the wide Wwafer=Wdesign*ratio of actual raceway groove, (Ldesign: the long design load of raceway groove, Wdesign: the wide design load of raceway groove, Ratio: the technology scale down), can realize of the conversion of L/W design load by the following method to actual value:

Following four parameter l ln=-1 are set, wwn=-1, ll=0.5* (1-ratio), ww=0.5* (1-ratio) is a fixed value, formula (1)～(4) can be write as follows:

Wherein, ratio is the technology scale down, Leff is that transistorized effective raceway groove is long, Weff is that transistorized effective raceway groove is wide, L is the design load of crystal pipe range, W is the wide design load of transistor, and DL, Lint, lw, lwn, lwl, lln, lwn, DW, Wint, wl, wln, wwl, wln, wwn, ll and ww are the relevant parameter of DC characteristic.

Reduction volume is counted according to design load among Leff and the Weff as can be known by (6) and (8) formula.

2. capacitor model parameter:

Junction capacity: can be by choosing Cj, Cjsw, the Cjswg parameter multiply by coefficient ratio.

Gate capacitance: choose electric capacity correlation model parameter, llc=ll=0.5* (1-ratio), wwc=ww=0.5* (1-ratio) according to above-mentioned same principle, can realize the correct description of electric capacity.

Wherein, ratio is the technology scale down, Leffc is that transistorized effective raceway groove is long, Weffc is that transistorized effective raceway groove is wide, L is the design load of crystal pipe range, W is the wide design load of transistor, and DL, DLC, lwc, lwn, lwlc, lln, lwn, DW, DWC, wlc, wln, wwlc, wln, wwn, llc and wwc are electric capacity correlation model parameter.

Reduction volume is counted according to design load among Leffc and the Weffc as can be known by (10) and (12) formula.

Claims (4)

1. a SPICE model method that is used for scaled down technology comprises the steps: step 1, and model data is measured; Step 2, model parameter extraction; Step 3 model emulation; It is characterized in that, in step 2, the SPICE model parameter is set, and the design load in the actual process is converted to actual value, the reduction volume of physical size is reflected in the model parameter.

2. the SPICE model method that is used for scaled down technology as claimed in claim 1, it is characterized in that, described in the step 2 the SPICE model parameter is set,, comprises parameter and the relevant parameter of electric capacity that DC characteristic is relevant by in conventional BSIM model, choosing following physical parameter.

3. the SPICE model method that is used for scaled down technology as claimed in claim 1 or 2, it is characterized in that, design load as follows that transistor is wide and long in step 2 is converted to actual value: following four parameter l ln=-1 are set, wwn=-1, ll=0.5* (1-ratio), ww=0.5* (1-ratio) is a fixed value, and (1) as follows～(4) are converted to actual value with design load:

Wherein, ratio is the technology scale down, Leff is that transistorized effective raceway groove is long, Weff is that transistorized effective raceway groove is wide, L is the design load of crystal pipe range, W is the wide design load of transistor, and DL, Lint, lw, lwn, lwl, lln, lwn, DW, Wint, wl, wln, wwl, wln, wwn, ll and ww are the relevant parameter of DC characteristic.

4. the SPICE model method that is used for scaled down technology as claimed in claim 1 or 2, it is characterized in that, in step 2, as follows the design load of junction capacity and gate capacitance is converted to actual value: junction capacity, by choosing Cj, Cjsw, the Cjswg parameter multiply by coefficient ratio; Gate capacitance by choosing electric capacity correlation model parameter, is provided with llc=ll=0.5* (1-ratio), wwc=ww=0.5* (1-ratio), (a) as follows～(d) design load is converted to actual value:

Wherein, ratio is the technology scale down, Leffc is that transistorized effective raceway groove is long, Weffc is that transistorized effective raceway groove is wide, L is the design load of crystal pipe range, W is the wide design load of transistor, and DL, DLC, lwc, lwn, lwlc, lln, lwn, DW, DWC, wlc, wln, wwlc, wln, wwn, llc and wwc are electric capacity correlation model parameter.

Images