CN101201756A - Method for detecting fault due to abnormal electrifying and shutting down - Google Patents
Method for detecting fault due to abnormal electrifying and shutting down Download PDFInfo
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- CN101201756A CN101201756A CNA200610157455XA CN200610157455A CN101201756A CN 101201756 A CN101201756 A CN 101201756A CN A200610157455X A CNA200610157455X A CN A200610157455XA CN 200610157455 A CN200610157455 A CN 200610157455A CN 101201756 A CN101201756 A CN 101201756A
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Abstract
The invention discloses a detection method of abnormal computer power-on and power-off faults and comprises the following steps: step 1, an embedded controller detects signal of the computer hardware system in real time, and decides whether an abnormal phenomenon happens, and if an exception signal is detected, step 2 is executed; else step 1 is executed sequentially; step 2, the embedded controller writes the exception signal into an electrically-erasable storage; step 3, a reader device reads information of the exception signal stored in the electrically-erasable storage through a battery interface, consequently, testers can read fault information through the battery interface without electrifying or detaching computers.
Description
Technical field
The present invention is about a kind of due to abnormal electrifying and shutdown method for detecting fault, and particularly do not need computing machine re-powered or dismantle and read the due to abnormal electrifying and the shutdown method for detecting fault of failure message.
Background technology
When due to abnormal electrifying or abnormal shutdown appearred in computing machine, the tester need be by obtaining to cause the abnormal signal of computing machine non-normal working to be fixed a breakdown.The method that traditional abnormal signal obtains is with the various power supplys of some apparatus measures computer-internal and the sequential of marking signal, and contrasts with the sequential specification that defines before, finds out underproof sequential and analyzes.This way needs experiment repeatedly just can find out problem, even if the abnormal problem of probability of occurrence, because much information is lost after power down restarts, so be difficult to extract accurately abnormal information.
Summary of the invention
Therefore the object of the present invention is to provide a kind of due to abnormal electrifying and shutdown method for detecting fault, it is by electrically connecting an electricity erasable memorizer with real-time being recorded in the electricity erasable memorizer of abnormal signal on the I2C bus that electrically connects at computer-internal circuit and battery interface, do not need computing machine is re-powered or dismantles, can utilize the battery interface on the computing machine to read failure message.
According to above-mentioned purpose of the present invention, a kind of due to abnormal electrifying and shutdown method for detecting fault are proposed, may further comprise the steps:
Step 1, the signal of embedded controller detecting real-time computer hardware system sees if there is abnormal occurrence and takes place,
The signal that notes abnormalities, execution in step 2;
The signal that do not note abnormalities continues execution in step 1;
Step 2, embedded controller writes electricity erasable memorizer with this abnormal signal;
Step 3, reading device are read in the information of the abnormal signal that stores in the electricity erasable memorizer by battery interface.
Due to abnormal electrifying of the present invention and shutdown method for detecting fault are by electrically connecting an electricity erasable memorizer on the I2C bus of computer-internal circuit and battery interface electric connection, pass through the internal circuit of the real-time monitoring computer of embedded controller of computer-internal again, and, so just make the tester in that do not power on or do not tear open can read failure information by battery interface under the situation of machine with real-time being recorded in the electricity erasable memorizer of abnormal signal.
Description of drawings
Below in conjunction with accompanying drawing,, will make technical scheme of the present invention and other beneficial effects apparent by the specific embodiment of the present invention is described in detail.
In the accompanying drawing,
Fig. 1 is for realizing theory diagram of the present invention;
Fig. 2 is the process flow diagram of due to abnormal electrifying of the present invention and shutdown method for detecting fault.
Embodiment
Fig. 1 is for realizing theory diagram of the present invention, as shown in the figure, embedded controller 10 electrically connects computer hardware system 20, the computer-internal Circuits System is monitored in real time, and the abnormal signal that monitors stored in the electricity erasable memorizer 30 by the I2C bus, last reading device 40 reads information in the electricity erasable memorizer 30 by battery interface 50.
Fig. 2 is the process flow diagram of due to abnormal electrifying of the present invention and shutdown method for detecting fault.
Step 1, the signal of embedded controller 10 detecting real-time computer hardware systems 20 sees if there is abnormal occurrence and takes place,
The signal that notes abnormalities, execution in step 2;
The signal that do not note abnormalities continues execution in step 1;
Step 2, embedded controller 10 writes electricity erasable memorizer 30 with this abnormal signal;
Step 3, reading device 40 are read in the information of the abnormal signal that stores in the electricity erasable memorizer 30 by battery interface 50.
Also comprise embedded controller 10 electric connection I2C bus and computer hardware systems 20 in step 1.Also comprise electricity erasable memorizer 30 electric connection I2C buses in step 2, after embedded controller 10 notes abnormalities signal, by the I2C bus abnormal information is write electricity erasable memorizer 30 by embedded controller 10.This electricity erasable memorizer 30 is an Electrically Erasable Read Only Memory.
In step 3, comprise battery interface 50 is electrically connected at the I2C bus, reading device 40 is connected in battery interface 50, and reading device 40 reads the abnormal signal that is stored in the electricity erasable memorizer 30 by the I2C bus.
When the tester finds that computing machine has due to abnormal electrifying or shutdown phenomenon, reading device 40 is connected on the battery interface 50 of computing machine, utilization is electrically connected to the abnormal signal that the I2C bus on the battery interface will be stored in the electricity erasable memorizer 30 and is read in the reading device 40, solves failure problems pointedly so that the tester records according to the information of these abnormal signals.
Therefore, due to abnormal electrifying of the present invention and shutdown method for detecting fault are by electrically connecting an electricity erasable memorizer on the I2C bus of computer-internal circuit and battery interface electric connection, pass through the internal circuit of the real-time monitoring computer of embedded controller of computer-internal again, and, so just make the tester in that do not power on or do not tear open can read failure information by battery interface under the situation of machine with real-time being recorded in the electricity erasable memorizer of abnormal signal.
The above for the person of ordinary skill of the art, can make other various corresponding changes and distortion according to technical scheme of the present invention and technical conceive, and all these changes and distortion all should belong to the scope that the present invention protects.
Claims (6)
1. a due to abnormal electrifying and the method for detecting fault that shuts down is characterized in that, may further comprise the steps:
Step 1, the signal in the embedded controller detecting real-time computer hardware system sees if there is abnormal occurrence and takes place,
The signal that notes abnormalities, execution in step 2;
The signal that do not note abnormalities continues execution in step 1;
Step 2, embedded controller writes electricity erasable memorizer with this abnormal signal;
Step 3, reading device read the information of the abnormal signal that stores in the electricity erasable memorizer by battery interface.
2. due to abnormal electrifying as claimed in claim 1 and shutdown method for detecting fault is characterized in that, in step 1, comprise embedded controller is electrically connected at I2C bus and computer hardware system.
3. due to abnormal electrifying as claimed in claim 1 and shutdown method for detecting fault is characterized in that, in step 2, comprise electricity erasable memorizer is electrically connected at the I2C bus.
4. due to abnormal electrifying as claimed in claim 1 and shutdown method for detecting fault is characterized in that in step 2, embedded controller writes electricity erasable memorizer by the I2C bus with abnormal information.
5. due to abnormal electrifying as claimed in claim 1 and shutdown method for detecting fault, it is characterized in that, in step 3, comprise battery interface is electrically connected at the I2C bus, reading device is connected in battery interface, and reading device reads the abnormal signal that is stored in the electricity erasable memorizer by the I2C bus.
6. due to abnormal electrifying as claimed in claim 1 and shutdown method for detecting fault is characterized in that electricity erasable memorizer is an Electrically Erasable Read Only Memory.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNA200610157455XA CN101201756A (en) | 2006-12-11 | 2006-12-11 | Method for detecting fault due to abnormal electrifying and shutting down |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNA200610157455XA CN101201756A (en) | 2006-12-11 | 2006-12-11 | Method for detecting fault due to abnormal electrifying and shutting down |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN101201756A true CN101201756A (en) | 2008-06-18 |
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Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CNA200610157455XA Pending CN101201756A (en) | 2006-12-11 | 2006-12-11 | Method for detecting fault due to abnormal electrifying and shutting down |
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| CN (1) | CN101201756A (en) |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101853196A (en) * | 2010-04-21 | 2010-10-06 | 中兴通讯股份有限公司 | Method and device recording exceptional data |
| CN102194521A (en) * | 2010-03-16 | 2011-09-21 | 精拓科技股份有限公司 | System and method for burning data for flash memory of notebook computer via battery interface |
| CN117395544A (en) * | 2023-12-12 | 2024-01-12 | 西安荣耀终端有限公司 | Battery state data reporting method, terminal equipment and storage medium |
-
2006
- 2006-12-11 CN CNA200610157455XA patent/CN101201756A/en active Pending
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102194521A (en) * | 2010-03-16 | 2011-09-21 | 精拓科技股份有限公司 | System and method for burning data for flash memory of notebook computer via battery interface |
| CN101853196A (en) * | 2010-04-21 | 2010-10-06 | 中兴通讯股份有限公司 | Method and device recording exceptional data |
| CN117395544A (en) * | 2023-12-12 | 2024-01-12 | 西安荣耀终端有限公司 | Battery state data reporting method, terminal equipment and storage medium |
| CN117395544B (en) * | 2023-12-12 | 2024-05-07 | 西安荣耀终端有限公司 | Battery state data reporting method, terminal equipment and storage medium |
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Application publication date: 20080618 |