CN101197260A - Semiconductor underlay and production method and its application on silicon and extension of insulator - Google Patents
Semiconductor underlay and production method and its application on silicon and extension of insulator Download PDFInfo
- Publication number
- CN101197260A CN101197260A CNA2007101737091A CN200710173709A CN101197260A CN 101197260 A CN101197260 A CN 101197260A CN A2007101737091 A CNA2007101737091 A CN A2007101737091A CN 200710173709 A CN200710173709 A CN 200710173709A CN 101197260 A CN101197260 A CN 101197260A
- Authority
- CN
- China
- Prior art keywords
- substrate
- semiconductor substrate
- layer
- silicon
- epitaxial
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Images
Abstract
The invention relates to a semi-conductor substrate, which comprises a covering layer which is positioned on the top layer and a cave layer which is positioned below the covering layer and a supporting layer which is positioned below the cave layer. The semi-conductor substrate with a special structure is prepared by two methods, that is, an ion injection and an anode oxidization. At the same time, the invention further discloses a method for preparing a silicon material on a generalized bonded thin insulator by the semi-conductor substrate, and a method for using the semi-conductor substrate for material extension as an extending substrate. Compared with the prior art, the invention has the advantage that the cave layer in the semi-conductor substrate can help release interlayer stress, thus acquiring perfect single crystal material.
Description
Technical field
The invention belongs to the manufacturing field of microelectronics and solid electronics, silica-based integrated opto-electronic device material.
Background technology
Silicon on the insulator (being SOI-silicon on insulator) has advantages such as high speed, low-power, anti-irradiation, has important application prospects at aspects such as Aero-Space, military project electronics, portable communications, automotive electronics, the silicon integrated circuit technology that is considered to 21st century, people's attention (J.P.Colinge extremely, Silicon onInsulator Technology, Material to VLSI, Kulwer Academic Publication 1991).Development along with automotive electronics integrated circuit, frequency power amplifying IC, illumination etc., to the demand of power device more and more widely, the SOI substrate has the good insulation performance performance because of it, make its application prospect (F.Urea that especially receives much attention in the power device field, D.Garner, K.Sheng, A.Popescu, H.T.Lim and W.I.Milne, SOI Power Device, Electronics and Communication Engineering Joumal, Feb.2000, Volume 12, p27).
The main bonding and wafer thinning technology of manufacturing technology of thick film SOI material and the smart peeling that the bonding and wafer thinning technology is derived are Smart-cut at present
Technology (G.K.Celler, Sorin Cristoloveanu, Frontiers ofsilicon-on-insulator, Journal of Applied Physics, vol.93, pp.4955,2003).
Traditional bonding and wafer thinning technology is exactly silicon chip and a slice mating plate bonding that a slice surface is had thermal oxide layer, under 1100 ℃ of high temperature, reinforces then, and with the thickness of silicon chip thinning back side to needs.Because the difference of thermal coefficient of expansion between silicon dioxide and the silicon, the processing step that high temperature is reinforced in bonding and wafer thinning SOI manufacture craft, to in soi layer, introduce a large amount of residual thermal stresses, and the existence of thermal stress will produce injurious effects even weaken bonding force (T.Iida between the bonding pad the performance of device, T.Itoh, D.Noguchi andY.Takano, Residual lattice strain in thin silicon-on-insulator bonded wafers:Thermalbehavior and formation mechanisms, Journal of Applied Physics, vol.87, pp.675-681,2000).Furukawa etc. studies show that, depend on different bonding temperatures, when interfacial stress surpasses 5-12MPa, soi layer will break away from support chip (F.Furukawa, Y.Udo and T.Kawakami, Mechanical propertiesfor directly bonded silicon wafers, in EEP Proc.Joint ASME/JSME Conf.ElectronicPackaging, pp.627-631,1992).In addition, thermal stress between soi layer and interfacial dielectric layer will cause generation of defects, such as dislocation, and these defectives will cause the distribution again of impurity and change device performance (A.E.Widmer and W.Rehwald, Thermoplastic deformation of silicon wafers, J.Electrochem.Soc., vol.133, pp.2403-2409,1986).
Summary of the invention
Processing step at the reinforcing of prior art high temperature, there is a large amount of residual thermal stress of introducing in the top silicon layer, and the existence of thermal stress will produce the problem of injurious effects to the performance of device, and in semi-conducting material heteroepitaxy process, how to discharge lattice and lose the stress that mismatch causes, the object of the invention is: a kind of Semiconductor substrate that embeds the hole layer that has is provided, adopt this Semiconductor substrate to be used for gallium nitride as epitaxial substrate, material epitaxies such as SiGe, and be used for the making of the silicon materials on the broad sense bonding and wafer thinning insulator as support substrates, have little residual thermal stress in the top layer silicon of the silicon materials on this broad sense insulator.Specifically, it is a kind of way that adopts anodic oxidation or ion to inject, at the support chip top or inner one deck hole layer that forms, and utilize this Semiconductor substrate as the epitaxial substrate of materials such as gallium nitride, SiGe or as the silicon materials on the support substrates making broad sense bonding and wafer thinning insulator with hole layer, can reduce residual thermal stress in the top layer silicon.
The invention provides the hole layer can be the surface or inner formation of initial substrate, the way that adopts ion to inject will form the hole layer in initial substrate inside, anode oxidation method directly forms the hole layer on the initial substrate surface, and the epitaxial semiconductor cover layer then forms the hole layer in this substrate interior on this hole layer.
Optionally, the material of described hole layer is porous silicon or the monocrystalline silicon that contains bubble.
Optionally, the material of described hole layer is a porous silicon.
Optionally, the material of described initial substrate is a monocrystalline silicon.
A kind of method for preparing above-mentioned Semiconductor substrate comprises the steps: to provide initial substrate; In initial substrate, carry out ion and inject, the modification ion is injected support substrates, in initial substrate, form and bury the hole layer.
Optionally, described modification ion is hydrogen, helium or its combination.
A kind of method for preparing above-mentioned Semiconductor substrate comprises the steps: to provide initial substrate; Make the hole layer on the initial substrate surface; Make cover layer at the hole laminar surface, then at the inner hole layer that forms of initial substrate.
Optionally, the material of described initial substrate is a monocrystalline silicon.
Optionally, the method for described making hole layer is an anode oxidation method.
Optionally, the corrosive liquid of described anodic oxidation employing is HF and C
2H
5The mixed solution of COOH, the current density of employing are 1mA/cm
2To 20mA/cm
2, the anodised time is 1min to 30min.
It is optionally, described that to make tectal method at the hole laminar surface be the chemical gaseous phase epitaxy.
Optionally, described tectal material is a monocrystalline silicon.
A kind of method that adopts above-mentioned Semiconductor substrate to make the silicon materials on the broad sense bonding and wafer thinning insulator comprises the following steps: to provide the Semiconductor substrate of a described structure as support substrates; A device substrate is provided; The surface of one or two substrates in support substrates and device substrate makes insulating barrier; This support substrates and device substrate are carried out bonding, and annealing; The attenuate device substrate; Polishing is carried out on device substrate surface behind the attenuate.
Optionally, described device substrate is a monocrystalline substrate.
Optionally, the material of described hole layer is porous silicon or the monocrystalline silicon that contains bubble.
Optionally, described finishing method is chemico-mechanical polishing.
Optionally, the thining method of described device substrate is mechanical lapping, chemical corrosion or its combination.
Compared with prior art, the invention has the advantages that to adopt in the top layer silicon of above-mentioned Semiconductor substrate as the silicon materials on the broad sense bonding and wafer thinning insulator of support substrates made to have little residual thermal stress.
A kind of method that adopts above-mentioned Semiconductor substrate to be used for epitaxial growth of semiconductor material may further comprise the steps: the Semiconductor substrate that a described structure is provided is as epitaxial substrate; On epitaxial substrate, make epitaxial buffer layer; The needed semi-conducting material of extension on epitaxial buffer layer.
Optionally, described cushioning layer material is an aluminium nitride.
Optionally, described epitaxial material is gallium nitride or SiGe.
Specifically: a kind of Semiconductor substrate has comprised cover layer that is positioned at top layer and the hole layer that is positioned at the cover layer below and the supporting layer that is positioned at hole layer below.
Aforesaid Semiconductor substrate, described hole layer material are porous silicon, perhaps contain monocrystalline silicon, indium phosphide or the GaAs of bubble.
Aforesaid Semiconductor substrate, the material of described supporting layer are monocrystalline silicon or indium phosphide or GaAs.
Aforesaid Semiconductor substrate, described tectal material comprise monocrystalline silicon or indium phosphide or GaAs or gallium nitride or aluminium nitride or SiGe.
A kind of method for preparing above-mentioned Semiconductor substrate comprises the steps:
Substrate is provided;
Initial substrate is provided;
In initial substrate, carry out ion and inject, the modification ion is injected initial substrate, at the inner hole layer that forms of initial substrate.
Aforesaid Semiconductor substrate, described modification ion are hydrogen, helium or its combination.
Aforesaid Semiconductor substrate, described initial substrate materials are monocrystalline silicon or indium phosphide or GaAs.
A kind of method for preparing above-mentioned Semiconductor substrate comprises the steps:
Initial substrate is provided;
Make the hole layer on the initial substrate surface;
Make cover layer at the hole laminar surface, then at the inner hole layer that forms of initial substrate;
Aforesaid Semiconductor substrate, the material of described initial substrate are monocrystalline silicon or indium phosphide or GaAs.
Aforesaid Semiconductor substrate, the method for described making hole layer is an anode oxidation method.
Aforesaid Semiconductor substrate, the corrosive liquid that described anodic oxidation is adopted is HF and C
2H
5The mixed solution of COOH, the current density of employing are 1mA/cm
2To 20mA/cm
2, the anodised time is 1min to 30min.
Aforesaid Semiconductor substrate, described to make tectal method at the hole laminar surface be the chemical gaseous phase epitaxy.
Aforesaid Semiconductor substrate, described tectal material is monocrystalline silicon, gallium nitride, aluminium nitride or SiGe.
A kind of method that adopts aforesaid Semiconductor substrate to make the silicon materials on the broad sense bonding and wafer thinning insulator comprises the following steps:
Provide a Semiconductor substrate as support substrates with said structure;
A device substrate is provided;
The surface of one or two substrates in support substrates and device substrate makes insulating barrier;
This Semiconductor substrate and device substrate are carried out bonding, and annealing;
The attenuate device substrate;
Polishing is carried out on device substrate surface behind the attenuate.
According to the method for the silicon materials on the above-mentioned making broad sense bonding and wafer thinning insulator, the material of described device substrate is monocrystalline silicon, indium phosphide or GaAs.
According to the method for the silicon materials on the above-mentioned making broad sense bonding and wafer thinning insulator, the material of described insulating barrier is silicon dioxide, silicon nitride, aluminium oxide or aluminium nitride.
According to the method for the silicon materials on the above-mentioned making broad sense bonding and wafer thinning insulator, insulating barrier be made as thermal oxidation or chemical vapour deposition (CVD).
According to the method for the silicon materials on the above-mentioned making broad sense bonding and wafer thinning insulator, the thining method of described device substrate is mechanical lapping, chemical corrosion or its combination.
According to the method for the silicon materials on the above-mentioned making broad sense bonding and wafer thinning insulator, described polishing is chemico-mechanical polishing.
A kind of method that adopts above-mentioned Semiconductor substrate to be used for epitaxial growth of semiconductor material may further comprise the steps:
Provide a Semiconductor substrate as epitaxial substrate with structure as mentioned above;
On epitaxial substrate, make resilient coating;
The needed semi-conducting material of extension on epitaxial buffer layer;
Aforesaid Semiconductor substrate, described method at extension substrate surface making resilient coating is chemical gaseous phase epitaxy, molecular beam epitaxy.
Aforesaid Semiconductor substrate, described material at resilient coating is monocrystalline silicon, gallium nitride, aluminium nitride or SiGe.
The method for preparing above-mentioned epitaxial semiconductor material, described on resilient coating the method for the required semi-conducting material of extension be chemical gaseous phase epitaxy, molecular beam epitaxy, described epitaxial material is monocrystalline silicon, gallium nitride, aluminium nitride or SiGe.
Compared with prior art, the invention has the advantages that SiGe, gallium nitride material delay time outward, the hole layer can help to discharge stress, obtains perfect monocrystal material.
Description of drawings
Figure 1 shows that first embodiment schematic diagram of Semiconductor substrate;
Figure 2 shows that second embodiment schematic diagram of Semiconductor substrate;
Figure 3 shows that the preparation method's of Semiconductor substrate the implementation step schematic diagram of first embodiment;
Fig. 4 to Fig. 5 is the preparation method's of Semiconductor substrate the process schematic representation of first embodiment;
Figure 6 shows that the preparation method's of Semiconductor substrate the implementation step schematic diagram of second embodiment;
Fig. 7 to Fig. 8 is the preparation method's of Semiconductor substrate the process schematic representation of first embodiment;
Fig. 9 is for making the implementation step schematic diagram of the silicon materials embodiment on the broad sense bonding and wafer thinning insulator;
Figure 10 to Figure 14 is for making the process schematic representation of the silicon materials embodiment on the broad sense bonding and wafer thinning insulator;
Figure 15 adopts the implementation step schematic diagram of this Semiconductor substrate as the embodiment of epitaxial substrate extension gallium nitride material;
Figure 16 to 18 is for adopting the process schematic representation of this Semiconductor substrate as the embodiment of epitaxial substrate extension gallium nitride material.
Embodiment
Below in conjunction with accompanying drawing to the preparation method of Semiconductor substrate of the present invention, Semiconductor substrate and adopt this Semiconductor substrate as the silicon materials on the broad sense bonding and wafer thinning insulator of support substrates with adopt this Semiconductor substrate to be described in detail as the embodiment of epitaxial substrate extension gallium nitride material.
At first introduce the embodiment of Semiconductor substrate of the present invention.Be illustrated in figure 1 as first embodiment schematic diagram of Semiconductor substrate, comprise cover layer 101, be positioned at the hole layer 102 of cover layer below, be positioned at the supporting layer 103 of hole layer below.
The material of described hole layer 102 is porous silicon or the monocrystalline silicon that contains bubble, and the material of cover layer 101 is a monocrystalline silicon, and the material of supporting layer 103 is a monocrystalline silicon,
Be illustrated in figure 2 as second embodiment schematic diagram of Semiconductor substrate, comprise hole layer 201, be positioned at the supporting layer 202 of hole layer below.
The material of described hole layer 201 is a porous silicon, and the material of supporting layer 202 is a monocrystalline silicon,
Provide first embodiment of the preparation method of Semiconductor substrate of the present invention below.Be illustrated in figure 3 as the preparation method's of Semiconductor substrate the implementation step schematic diagram of first embodiment.Step S301 provides initial substrate; Step S302 carries out ion and injects in initial substrate, the modification ion is injected support substrates, forms the hole layer in an initial substrate.
Fig. 4 is the process schematic representation of this embodiment to Fig. 5.
Refer step S301 as shown in Figure 4, provides initial substrate 301.Described initial substrate 301 is a modal monocrystalline substrate in the semiconductor technology.
Refer step S302 as shown in Figure 5, carries out ion and injects in support substrates 301, the modification ion is injected initial substrate 301, forms hole layer 304 in initial substrate 301, and all the other are cover layer 302, supporting layer 303.
Described modification ion can be a hydrogen ion, and the basic principle of selecting ion is that the modification ion that is injected can produce the hole layer at silicon, changes the performance of the material of ion injection phase, forms the monocrystalline silicon that contains bubble.When the modification ion that injects was hydrogen ion, implantation dosage was 1 * 10
14/ cm
2To 1 * 10
18/ cm
2, injecting energy is that 20KeV is to 2000KeV.
Introduce second embodiment of the preparation method of Semiconductor substrate of the present invention below in conjunction with accompanying drawing.Be illustrated in figure 6 as the preparation method's of Semiconductor substrate the implementation step schematic diagram of second embodiment.Step S401 provides initial substrate; Step S402 makes the hole layer on the initial substrate surface.
Fig. 7 to Fig. 8 is the process schematic representation of this embodiment.
Refer step S401 as shown in Figure 7, provides initial substrate 401.Described initial substrate is a modal monocrystalline substrate in the semiconductor technology.
Refer step S402 as shown in Figure 8, makes hole layer 403 on support substrates 401 surfaces, and then 402 is supporting layer.
The method of above-mentioned making hole layer is an anode oxidation method.Anode oxidation method is the method for preparing porous silicon common in the semiconductor technology.The corrosive liquid that anodic oxidation condition adopts is HF and C
2H
5The mixed solution of COOH, the volume ratio that both mix is 100: 1 to 1: 100, preferred mixed proportion is 1: 1; Anodised current density is 1mA/cm
2To 20mA/cm
2Between; Anodizing time is that 1min is between the 30min.
Also can be according to the needs of subsequent applications, the surface that is chosen in hole layer 403 also makes one deck cover layer, the process of preparation is chemical gaseous phase epitaxy (CVD), also can be molecular beam epitaxy (MBE), low pressure chemical vapour phase epitaxy (LPCVD), high vacuum chemical vapour phase epitaxy (UHVCVD) or ultra vacuum electron beam evaporation etc.Adopting pre-oxidation process, the temperature of pre-oxidation process before the extension is 100 ℃ to 1000 ℃, and preoxidation time is 5 minutes to 10 hours, and the monocrystalline silicon layer thickness of extension is that 30nm is to 100 μ m.To obtain aforementioned structure shown in Figure 1 after making cover layer, hole layer 403 surface do not make cover layer, will obtain aforementioned structure shown in Figure 2.
Introduce silicon materials embodiment on the making broad sense bonding and wafer thinning insulator of the present invention below in conjunction with accompanying drawing.As shown in Figure 9, be the implementation step schematic diagram of the silicon materials embodiment on the making broad sense bonding and wafer thinning insulator of the present invention.Step S501 provides a Semiconductor substrate with described structure as support substrates; Step S502 provides a device substrate; Step S503, the surface of one or two substrates in support substrates and device substrate makes insulating barrier; Step S504 carries out bonding with this support substrates and device substrate, and annealing; Step S505, the attenuate device substrate; Step S506 carries out polishing to the device substrate surface behind the attenuate.
Figure 10 to Figure 14 is the process schematic representation of this embodiment.
Refer step S501 as shown in figure 10, provides a Semiconductor substrate with described structure as support substrates 501, comprises cover layer 502, hole layer 503, supporting layer 504.
Refer step S502 as shown in figure 11, provides a device substrate 505, and described device substrate 505 is a modal monocrystalline substrate in the semiconductor technology.
Refer step S503, the surface of one or two substrates in support substrates 501 and device substrate 505 makes insulating barrier.
Because in following step, the surface of support substrates 501 and device substrate 505 will adhere to by bonding and be integral, therefore can make insulating barrier on one of them surface of support substrates 501 or device substrate 505, also can all make insulating barrier, not influence subsequent technique on the surface of support substrates 501 and device substrate 505.
As shown in figure 12, for only making the schematic diagram of insulating barrier 506 on support substrates 501 surfaces.Insulating barrier 506 manufacture crafts can adopt oxidation preparation technology ripe in the integrated circuit, as dry-oxygen oxidation technology or " dried oxygen+wet oxygen+dried oxygen " technology.Oxidation technology is carried out under the atmosphere of oxygen, and oxidizing temperature 600-1400 ℃, oxidization time 0.5 hour to 10 hours, the material of the insulating barrier that obtains is a silica, thickness 10nm to 500 nanometer.Insulating barrier 303 also can strengthen additive methods making such as chemical vapour deposition (CVD) (PECVD), physical vapor deposition (PVD), magnetron sputtering or electron beam evaporation by using plasma, and the material of insulating barrier 506 can be silicon nitride, silicon oxynitride, carborundum, aluminium nitride or aluminium oxide etc.
Refer step S503, as shown in figure 13, with device substrate 505 and support substrates 501 bondings.
Described bonding can adopt high temperature bonding or electrostatic bonding the most common in the present semiconductor technology, also can be before bonding the auxiliary plasma activating process.Described annealing is carried out in oxygen-containing atmosphere, and temperature is 300 ℃ to 1400 ℃, and the time is 0.5 hour to 15 hours.
Refer step S504, as shown in figure 14, attenuate device substrate 505, residue top layer silicon 507, silicon layer thickness is that 1 μ m is to 100 μ m.
Described thining method is mechanical lapping attenuate, chemical corrosion attenuate or its combination.
Refer step S505 carries out polishing to the device substrate surface behind the attenuate.
The way of described polishing is chemico-mechanical polishing (CMP).
Introduce the embodiment of this Semiconductor substrate of employing of the present invention below in conjunction with accompanying drawing as epitaxial substrate extension gallium nitride material.Adopt the implementation step schematic diagram of this Semiconductor substrate for the present invention as shown in figure 15 as the embodiment of epitaxial substrate extension gallium nitride material.Step S601 provides a Semiconductor substrate with described structure as epitaxial substrate; Step S602, epitaxial buffer layer 605 on this epitaxial substrate; Step S603, extension gallium nitride layer 606 on this resilient coating.
Figure 16 to Figure 18 is the process schematic representation of this embodiment.
Refer step S601 as shown in figure 16, provides a Semiconductor substrate with described structure as epitaxial substrate 601, comprises cover layer 602, hole layer 603, supporting layer 604.
Refer step S602, as shown in figure 17, epitaxial buffer layer 605 on this epitaxial substrate.As shown in figure 18, extension gallium nitride layer 606 on this resilient coating.
Described epitaxial growth equipment is MOCVD, epitaxial substrate 601 before epitaxial buffer layer at H
2In the atmosphere, between 1000 ℃-1150 ℃, preceding baking 10 minutes to 1 hour.The MOCVD growth source is trimethyl gallium, trimethyl and ammonia.Growth 45nmAlN resilient coating under 1100 ℃, 50mbar condition, this layer resilient coating of also can not growing.Growing GaN under 1070 ℃ then, 100mbar, growth thickness 1 μ m.
Claims (23)
1. a Semiconductor substrate is characterized in that, has comprised cover layer that is positioned at top layer and the hole layer that is positioned at the cover layer below and the supporting layer that is positioned at hole layer below.
2. Semiconductor substrate according to claim 1 is characterized in that, the described hole layer material is a porous silicon, perhaps contains monocrystalline silicon, indium phosphide or the GaAs of bubble.
3. Semiconductor substrate according to claim 1 and 2 is characterized in that, the material of described supporting layer is monocrystalline silicon or indium phosphide or GaAs.
4. Semiconductor substrate according to claim 1 and 2 is characterized in that, described tectal material comprises monocrystalline silicon or indium phosphide or GaAs or gallium nitride or aluminium nitride or SiGe.
5. a method for preparing the described Semiconductor substrate of claim 1 is characterized in that, comprises the steps:
Substrate is provided;
Initial substrate is provided;
In initial substrate, carry out ion and inject, the modification ion is injected initial substrate, at the inner hole layer that forms of initial substrate.
6. the method for preparing Semiconductor substrate according to claim 4 is characterized in that, described modification ion is hydrogen, helium or its combination.
7. the method for preparing Semiconductor substrate according to claim 4 is characterized in that, described initial substrate materials is monocrystalline silicon or indium phosphide or GaAs.
8. a method for preparing the described Semiconductor substrate of claim 1 is characterized in that, comprises the steps:
Initial substrate is provided;
Make the hole layer on the initial substrate surface;
Make cover layer at the hole laminar surface, then at the inner hole layer that forms of initial substrate;
9. the method for preparing Semiconductor substrate according to claim 7 is characterized in that, the material of described initial substrate is monocrystalline silicon or indium phosphide or GaAs.
10. the method for preparing Semiconductor substrate according to claim 7 is characterized in that, the method for described making hole layer is an anode oxidation method.
11. the method for preparing Semiconductor substrate according to claim 7 is characterized in that, the corrosive liquid that described anodic oxidation is adopted is HF and C
2H
5The mixed solution of COOH, the current density of employing are 1mA/cm
2To 20mA/cm
2, the anodised time is 1min to 30min.
12. the method for preparing Semiconductor substrate according to claim 7 is characterized in that, described to make tectal method at the hole laminar surface be the chemical gaseous phase epitaxy.
13. the method for preparing Semiconductor substrate according to claim 7 is characterized in that, described tectal material is monocrystalline silicon, gallium nitride, aluminium nitride or SiGe.
14. a method that adopts Semiconductor substrate described in the claim 1 to make the silicon materials on the broad sense bonding and wafer thinning insulator is characterized in that, comprises the following steps:
Provide a Semiconductor substrate as support substrates with structure described in the claim 1;
A device substrate is provided;
The surface of one or two substrates in support substrates and device substrate makes insulating barrier;
This Semiconductor substrate and device substrate are carried out bonding, and annealing;
The attenuate device substrate;
Polishing is carried out on device substrate surface behind the attenuate.
15. the method according to the silicon materials on the described making broad sense of the claim 13 bonding and wafer thinning insulator is characterized in that the material of described device substrate is monocrystalline silicon, indium phosphide or GaAs.
16. the method according to the silicon materials on the described making broad sense of the claim 13 bonding and wafer thinning insulator is characterized in that the material of described insulating barrier is silicon dioxide, silicon nitride, aluminium oxide or aluminium nitride.
17. the method for the silicon materials on the making broad sense bonding and wafer thinning insulator according to claim 13 is characterized in that, insulating barrier be made as thermal oxidation or chemical vapour deposition (CVD).
18. the method according to the silicon materials on the described making broad sense of the claim 13 bonding and wafer thinning insulator is characterized in that the thining method of described device substrate is mechanical lapping, chemical corrosion or its combination.
19. the method for the silicon materials on the making broad sense bonding and wafer thinning insulator according to claim 13 is characterized in that described polishing is chemico-mechanical polishing.
20. a method that adopts Semiconductor substrate described in the claim 1 to be used for epitaxial growth of semiconductor material is characterized in that, may further comprise the steps:
Provide a Semiconductor substrate as epitaxial substrate with structure described in the claim 1;
On epitaxial substrate, make resilient coating;
The needed semi-conducting material of extension on epitaxial buffer layer;
21. the method for epitaxial semiconductor material according to claim 19 is characterized in that, described method at extension substrate surface making resilient coating is chemical gaseous phase epitaxy, molecular beam epitaxy.
22. the method for epitaxial semiconductor material according to claim 19 is characterized in that, described material at resilient coating is monocrystalline silicon, gallium nitride, aluminium nitride or SiGe.
23. the method for epitaxial semiconductor material according to claim 19, it is characterized in that, described on resilient coating the method for the required semi-conducting material of extension be chemical gaseous phase epitaxy, molecular beam epitaxy, described epitaxial material is monocrystalline silicon, gallium nitride, aluminium nitride or SiGe.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN2007101737091A CN101197260B (en) | 2007-12-28 | 2007-12-28 | Semiconductor underlay production method and extension method |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN2007101737091A CN101197260B (en) | 2007-12-28 | 2007-12-28 | Semiconductor underlay production method and extension method |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN101197260A true CN101197260A (en) | 2008-06-11 |
| CN101197260B CN101197260B (en) | 2010-04-14 |
Family
ID=39547561
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN2007101737091A Active CN101197260B (en) | 2007-12-28 | 2007-12-28 | Semiconductor underlay production method and extension method |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN101197260B (en) |
Cited By (13)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101901753A (en) * | 2010-06-25 | 2010-12-01 | 上海新傲科技股份有限公司 | Method for preparing thick-film material with insulating embedded layer |
| CN101958271A (en) * | 2010-07-09 | 2011-01-26 | 中国科学院上海微系统与信息技术研究所 | Method for preparing hanging strained silicon film by utilizing silicon on insulator |
| CN102184940A (en) * | 2011-03-30 | 2011-09-14 | 清华大学 | Semiconductor structure and forming method thereof |
| CN102201362A (en) * | 2011-05-13 | 2011-09-28 | 上海新傲科技股份有限公司 | Method for preparing the substrate with insulating buried layer and arbitrary thickness |
| CN102569353A (en) * | 2011-01-04 | 2012-07-11 | 中国科学院微电子研究所 | Semiconductor structure and preparation method thereof |
| CN102683178A (en) * | 2012-05-31 | 2012-09-19 | 中国科学院上海微系统与信息技术研究所 | Semiconductor-on-insulator and preparation method thereof |
| CN103035585A (en) * | 2012-12-12 | 2013-04-10 | 武汉铂岩科技有限公司 | Metal aluminum base aluminum nitride package substrate and preparation method thereof |
| CN103311172A (en) * | 2012-03-16 | 2013-09-18 | 中芯国际集成电路制造(上海)有限公司 | SOI (Silicon On Insulator) substrate formation method |
| CN103646961A (en) * | 2013-11-19 | 2014-03-19 | 中国电子科技集团公司第五十五研究所 | Silicon-based Group III nitride thin film containing high resistance parasitic conductive layer and growth method |
| CN104538282A (en) * | 2014-12-17 | 2015-04-22 | 江苏能华微电子科技发展有限公司 | Growing method of vertical structure power device epitaxial layer and power device |
| CN105097732A (en) * | 2014-05-22 | 2015-11-25 | 上海北京大学微电子研究院 | SOI high-voltage structure for reducing self-heating effect |
| CN105789026A (en) * | 2014-12-25 | 2016-07-20 | 中国科学院微电子研究所 | Substrate structure and manufacturing method therefor |
| CN111180334A (en) * | 2020-01-15 | 2020-05-19 | 长江存储科技有限责任公司 | Semiconductor substrate thinning method |
Family Cites Families (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1153283C (en) * | 2001-07-20 | 2004-06-09 | 中国科学院上海冶金研究所 | Substrate of silicon structure on insulating layer using alumina as buried layer and its preparing process |
-
2007
- 2007-12-28 CN CN2007101737091A patent/CN101197260B/en active Active
Cited By (19)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101901753A (en) * | 2010-06-25 | 2010-12-01 | 上海新傲科技股份有限公司 | Method for preparing thick-film material with insulating embedded layer |
| CN101958271A (en) * | 2010-07-09 | 2011-01-26 | 中国科学院上海微系统与信息技术研究所 | Method for preparing hanging strained silicon film by utilizing silicon on insulator |
| CN101958271B (en) * | 2010-07-09 | 2012-09-26 | 中国科学院上海微系统与信息技术研究所 | Method for preparing hanging strained silicon film by utilizing silicon on insulator |
| CN102569353A (en) * | 2011-01-04 | 2012-07-11 | 中国科学院微电子研究所 | Semiconductor structure and preparation method thereof |
| CN102184940A (en) * | 2011-03-30 | 2011-09-14 | 清华大学 | Semiconductor structure and forming method thereof |
| CN102184940B (en) * | 2011-03-30 | 2014-01-08 | 清华大学 | Semiconductor structure and forming method thereof |
| CN102201362A (en) * | 2011-05-13 | 2011-09-28 | 上海新傲科技股份有限公司 | Method for preparing the substrate with insulating buried layer and arbitrary thickness |
| CN102201362B (en) * | 2011-05-13 | 2014-05-14 | 上海新傲科技股份有限公司 | Method for preparing substrate with insulating buried layer and arbitrary thickness |
| CN103311172A (en) * | 2012-03-16 | 2013-09-18 | 中芯国际集成电路制造(上海)有限公司 | SOI (Silicon On Insulator) substrate formation method |
| US8980729B2 (en) | 2012-03-16 | 2015-03-17 | Semiconductor Manufacturing International Corp. | Silicon-on-insulator substrate and fabrication method |
| CN102683178A (en) * | 2012-05-31 | 2012-09-19 | 中国科学院上海微系统与信息技术研究所 | Semiconductor-on-insulator and preparation method thereof |
| CN103035585A (en) * | 2012-12-12 | 2013-04-10 | 武汉铂岩科技有限公司 | Metal aluminum base aluminum nitride package substrate and preparation method thereof |
| CN103035585B (en) * | 2012-12-12 | 2015-07-15 | 武汉铂岩科技有限公司 | Metal aluminum base aluminum nitride package substrate and preparation method thereof |
| CN103646961A (en) * | 2013-11-19 | 2014-03-19 | 中国电子科技集团公司第五十五研究所 | Silicon-based Group III nitride thin film containing high resistance parasitic conductive layer and growth method |
| CN103646961B (en) * | 2013-11-19 | 2017-02-22 | 中国电子科技集团公司第五十五研究所 | Silicon-based Group III nitride thin film containing high resistance parasitic conductive layer and growth method |
| CN105097732A (en) * | 2014-05-22 | 2015-11-25 | 上海北京大学微电子研究院 | SOI high-voltage structure for reducing self-heating effect |
| CN104538282A (en) * | 2014-12-17 | 2015-04-22 | 江苏能华微电子科技发展有限公司 | Growing method of vertical structure power device epitaxial layer and power device |
| CN105789026A (en) * | 2014-12-25 | 2016-07-20 | 中国科学院微电子研究所 | Substrate structure and manufacturing method therefor |
| CN111180334A (en) * | 2020-01-15 | 2020-05-19 | 长江存储科技有限责任公司 | Semiconductor substrate thinning method |
Also Published As
| Publication number | Publication date |
|---|---|
| CN101197260B (en) | 2010-04-14 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN101197260B (en) | Semiconductor underlay production method and extension method | |
| US6100165A (en) | Method of manufacturing semiconductor article | |
| US6054363A (en) | Method of manufacturing semiconductor article | |
| US6350702B2 (en) | Fabrication process of semiconductor substrate | |
| Taraschi et al. | Strained Si, SiGe, and Ge on-insulator: review of wafer bonding fabrication techniques | |
| US11183420B2 (en) | High resistivity silicon-on-insulator wafer manufacturing method for reducing substrate loss | |
| US10290533B2 (en) | Thermally stable charge trapping layer for use in manufacture of semiconductor-on-insulator structures | |
| US11699615B2 (en) | High resistivity semiconductor-on-insulator wafer and a method of manufacture | |
| EP3189544B1 (en) | Method of manufacturing high resistivity silicon-on-insulator substrate | |
| US6573126B2 (en) | Process for producing semiconductor article using graded epitaxial growth | |
| US7887936B2 (en) | Substrate with determinate thermal expansion coefficient | |
| CN100487885C (en) | Method for manufacturing silicon of insulator | |
| US20070278574A1 (en) | Compound semiconductor-on-silicon wafer with a thermally soft insulator | |
| US7498229B1 (en) | Transistor and in-situ fabrication process | |
| CA2220600C (en) | Method of manufacturing semiconductor article | |
| US7749863B1 (en) | Thermal management substrates | |
| KR19980042471A (en) | Manufacturing method of semiconductor article | |
| KR20190095322A (en) | High resistivity silicon-on-insulator structure and its manufacturing method | |
| CN114175212A (en) | Method for producing a composite structure comprising a thin layer of monocrystalline SIC on a polycrystalline SIC carrier substrate | |
| FAURE et al. | INNOVATIVE SUBSTRATE SOLUTIONS FOR WIDE BAND GAP MATERIALS: THE SMART CUT™ APPROACH F. LETERTRE', N. DAVAL', F. TEMPLIER², L. DI CIOCCIO 2, C. RICHTARCH', B. |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant |