CN101197186A

CN101197186A - Ferroelectric memory device and electronic equipment

Info

Publication number: CN101197186A
Application number: CNA200710187566XA
Authority: CN
Inventors: 小出泰纪
Original assignee: Seiko Epson Corp
Current assignee: Seiko Epson Corp
Priority date: 2006-12-04
Filing date: 2007-12-03
Publication date: 2008-06-11
Anticipated expiration: 2027-12-03
Also published as: JP4264758B2; CN101197186B; JP2008140493A

Abstract

The invention provides a ferroelectric memory device and an electronic device which can increase the read capability of the ferroelectric memory device and also increase the read performance of the ferroelectric memory device, wherein, the ferroelectric memory device includes a first p charge-transfer MISFET (P1-L) connected between a first node (Vmn-L)and a third node (Vc-L), wherein, the grid of the first p charge-transfer MISFET is connected with the second node (Vmn-R); a second p charge-transfer MISFET (P1-R) connected between a second node and a fourth node (Vc-R), wherein, the grid of the second p charge-transfer MISFET is connected with the first node; a first charge-transfer MISFET (T2-L) connected between the first bit line (BL-L) and the first node (Vmn-L); a second charge-transfer MISFET (T2-R) connected between the second bit line (BL-R) and the second node (Vmn-R); a first capacitance (C5-L)connected to the first node; and a second capacitance (C5-R)connected to the second node.

Description

Ferroelectric memory and electronic equipment

Technical field

The present invention relates to ferroelectric memory and electronic equipment, relate in particular to the sensing circuit of ferroelectric memory.

Background technology

Known have a kind of method (for example, with reference to following patent documentation 1): use the sense amplifier circuit of latch-type to carry out reading of ferroelectric memory (FeRAM:FerroelectricRandom Access Memory).

But in this case, the voltage that is added on the printed line is the voltage of ferroelectric condenser electric capacity (Cs) and the voltage of bit line capacitance (Cbl) by dividing potential drop.Therefore, because bit line capacitance (Cbl) can't add enough current potentials to ferroelectric condenser.And, since by sensor amplifier carry out bit-line voltage difference amplification and read, so bit line capacitance (Cbl) increases greatly more, bit-line voltage is more little, diminishes thereby cause reading tolerance limit.

In addition, also study the sensing circuit (for example, with reference to following patent documentation 2) that a kind of hypothesis is fixed on bit line earthing potential

Patent documentation 1: TOHKEMY 2000-187990 communique

Patent documentation 2: TOHKEMY 2000-133857 communique

But, even the circuit that uses above-mentioned patent documentation 2 grades to record and narrate, describe in detail as following, when the ferroelectric condenser electric capacity of (1) storage unit and initial setting produce bigger skew, (2) during the ratio marked change of the ferroelectric condenser electric capacity of storage unit and tank capacitance, cause reading tolerance limit and reduce.

And, (3) importantly: improve and wrongly to judge, simultaneously, improve and read tolerance limit.Especially have following situation when the reading of ferroelectric storage cell: earlier that the original quantity of electric charge is little " 0 " data send bit line to, and current potential that temporarily will " 0 " data and the current potential of " 1 " data reverse.Under such inverted status,, then be easy to produce wrong judgement if enlarge current potential of " 0 " data and the potential difference (PD) of " 1 " data.

Summary of the invention

In view of the above problems, the object of the present invention is to provide a kind of ferroelectric memory and electronic equipment, it can improve the tolerance limit of reading of ferroelectric memory, and, can improve the characteristic of reading of ferroelectric memory.

(1) ferroelectric memory that the present invention relates to comprises: first electric charge transmits MISFET (first electric charge transmits and uses MISFET), is connected between first bit line and the first node; Second electric charge transmits MISFET (second electric charge transmits and uses MISFET), is connected between second bit line and the Section Point; First electric capacity is connected in above-mentioned first node; Second electric capacity is connected in above-mentioned Section Point; The one p channel-type MISFET is connected above-mentioned first electric charge and transmits between MISFET and the above-mentioned first node, and the grid of an above-mentioned p channel-type MISFET is connected in above-mentioned Section Point; And the 2nd p channel-type MISFET, being connected above-mentioned second electric charge and transmitting between MISFET and the above-mentioned Section Point, the grid of above-mentioned the 2nd p channel-type MISFET is connected in above-mentioned first node.

According to such structure,, rise owing to can suppress the current potential of the side among first node Vmn-L and the Section Point Vmn-R, so can guarantee their potential difference (PD) significantly even under the big situation of the ferroelectric condenser electric capacity change of storage unit.

(2) preferred above-mentioned first electric charge transmission MISFET and above-mentioned second electric charge transmission MISFET are respectively p channel-type MISFET.

(3) be preferably: above-mentioned ferroelectric memory also comprises first phase inverter and second phase inverter, this first phase inverter is connected first bit line and above-mentioned first electric charge transmits between the grid of MISFET, the input part of above-mentioned first phase inverter is connected with above-mentioned first bit line by the 3rd electric capacity, the efferent of above-mentioned first phase inverter is connected with the grid that above-mentioned first electric charge transmits MISFET by the 4th electric capacity, this second phase inverter is connected second bit line and above-mentioned second electric charge transmits between the grid of MISFET, the input part of above-mentioned second phase inverter is connected with above-mentioned second bit line by the 5th electric capacity, and the efferent of above-mentioned second phase inverter is connected with the grid that above-mentioned second electric charge transmits MISFET by the 6th electric capacity.According to such structure, feed back to first electric charge by current potential and transmit the grid that MISFET, second electric charge transmit MISFET first bit line, second bit line, be earthing potential thereby bit line more firmly fixed.

(4) for example, above-mentioned ferroelectric memory also comprises: the 3rd p channel-type MISFET is connected as above-mentioned first electric charge and transmits between the 3rd node and earthing potential of connected node of a MISFET and an above-mentioned p channel-type MISFET; And the 4th p channel-type MISFET, be connected as above-mentioned second electric charge and transmit between the 4th node and earthing potential of connected node of MISFET and above-mentioned the 2nd p channel-type MISFET.

According to such structure, even under the situation that the ferroelectric condenser electric capacity of storage unit diminishes, owing to also can promote the current potential of the side in first node, the Section Point, so can guarantee their potential difference (PD) significantly by the 3rd p channel-type MISFET, the 4th p channel-type MISFET.

(5) the 3rd p channel-type MISFET and above-mentioned the 4th p channel-type MISFET Be Controlled so that after reading of above-mentioned ferroelectric memory moved beginning, and after during certain, become conducting state.

(6) for example, above-mentioned ferroelectric memory also comprises: a n channel-type MISFET is connected between the efferent and earthing potential of above-mentioned first phase inverter; And the 2nd n channel-type MISFET, be connected between the efferent and earthing potential of above-mentioned second phase inverter.

According to such structure, even under the situation that the ferroelectric condenser electric capacity of storage unit diminishes, owing to also can promote the current potential of the side in first node, the Section Point, so can guarantee their potential difference (PD) significantly by a n channel-type MISFET, the 2nd n channel-type MISFET.

(7) an above-mentioned n channel-type MISFET and above-mentioned the 2nd n channel-type MISFET Be Controlled so that after reading of above-mentioned ferroelectric memory moved beginning, and after during certain, become conducting state.

(8) for example, above-mentioned ferroelectric memory also comprises: the 5th p channel-type MISFET is connected between the input part and power supply potential of above-mentioned first phase inverter; And the 6th p channel-type MISFET, be connected between the efferent and power supply potential of above-mentioned second phase inverter.

According to such structure, even under the situation that the ferroelectric condenser electric capacity of storage unit diminishes, owing to also can promote the current potential of the side in first node, the Section Point, so can guarantee their potential difference (PD) significantly by the 5th p channel-type MISFET, the 6th p channel-type MISFET.

(9) above-mentioned the 5th p channel-type MISFET and above-mentioned the 6th p channel-type MISFET Be Controlled so that after reading of above-mentioned ferroelectric memory moved beginning, and after during certain, become conducting state.

(10) for example, above-mentioned first electric capacity, above-mentioned second electric capacity are ferroelectric capacitors.According to such structure, can guarantee big electric capacity with small size.

(11) for example, above-mentioned first electric capacity, above-mentioned second electric capacity are gate capacitance.According to such structure, can controlledly form electric capacity well.

(12) for example, on above-mentioned first bit line and above-mentioned second bit line, be connected with ferroelectric memory respectively.According to such structure, the present invention can be applicable to the ferroelectric storage cell of so-called 2T2C.

(13) for example, on above-mentioned first bit line, be connected with ferroelectric memory, be added with reference potential outside on above-mentioned second bit line.According to such structure, the present invention can be applicable to the ferroelectric storage cell of so-called 1T1C.

(14) electronic equipment that the present invention relates to has above-mentioned ferroelectric memory.According to such structure, can improve the characteristic of electronic equipment.At this, so-called electronic equipment is meant to have general device ferroelectric memory, the certain function of performance that the present invention relates to, there is no particular limitation for its structure, for example comprises all devices general computer installation with above-mentioned ferroelectric memory, portable phone, PHS, PDA, electronic memo, IC-card etc., that need memory storage.

(15) ferroelectric memory that the present invention relates to comprises: a p channel-type MISFET, be connected between first node and above-mentioned the 3rd node, and the grid of an above-mentioned p channel-type MISFET is connected in Section Point; The 2nd p channel-type MISFET is connected between above-mentioned Section Point and the 4th node, and the grid of above-mentioned the 2nd p channel-type MISFET is connected in above-mentioned first node; First electric charge transmits MISFET, is connected between first bit line and the 3rd node; Second electric charge transmits MISFET, is connected between second bit line and the 4th node; First control circuit is connected above-mentioned first bit line and above-mentioned first electric charge and transmits between the first grid of MISFET, according to the current potential of above-mentioned first bit line, and the current potential that control adds to above-mentioned first grid; Second control circuit is connected above-mentioned second bit line and above-mentioned second electric charge and transmits between the second grid of MISFET, according to the current potential of above-mentioned second bit line, and the current potential that control adds to above-mentioned second grid; First electric capacity is connected in above-mentioned first node; Second electric capacity is connected in above-mentioned Section Point; The first negative potential generation circuit is connected in above-mentioned first bit line; And the second negative potential generation circuit, be connected in above-mentioned second bit line.

According to such structure, owing to also can promote the current potential of the side in first node, the Section Point by a p channel-type MISFET, the 2nd p channel-type MISFET, thus can guarantee their potential difference (PD) significantly, and can realize reading the raising of tolerance limit.And, owing to first bit line and second bit line are changed to negative potential by the first negative potential generation circuit and the second negative potential generation circuit, thereby can limit the action of a p channel-type MISFET and the 2nd p channel-type MISFET at the initial stage of reading, and can improve wrong judgement.

(16) preferred above-mentioned first electric charge transmission MISFET and above-mentioned second electric charge transmission MISFET are respectively p channel-type MISFET.

(17) be preferably: above-mentioned first control circuit comprises first phase inverter, above-mentioned first phase inverter is connected first bit line and above-mentioned first electric charge transmits between the grid of MISFET, the input part of above-mentioned first phase inverter is connected with above-mentioned first bit line by the 3rd electric capacity, the efferent of above-mentioned first phase inverter is connected with the grid that above-mentioned first electric charge transmits MISFET by the 4th electric capacity, above-mentioned second control circuit comprises second phase inverter, above-mentioned second phase inverter is connected second bit line and above-mentioned second electric charge transmits between the grid of MISFET, the input part of above-mentioned second phase inverter is connected with above-mentioned second bit line by the 5th electric capacity, and the efferent of above-mentioned second phase inverter is connected with the grid that above-mentioned second electric charge transmits MISFET by the 6th electric capacity.According to such structure, the current potential of first bit line, second bit line can be fed back to the grid that first electric charge transmits MISFET, second electric charge transmission MISFET.

(18) be preferably: the above-mentioned first negative potential generation circuit comprises the 7th electric capacity, above-mentioned the 7th electric capacity is connected between above-mentioned first bit line and above-mentioned first signal wire, the above-mentioned second negative potential generation circuit comprises the 8th electric capacity, and above-mentioned the 8th electric capacity is connected between above-mentioned second bit line and above-mentioned first signal wire.According to such structure, can relatively easily produce negative potential by simple structure.

(19) for example, above-mentioned the 7th electric capacity, above-mentioned the 8th electric capacity are ferroelectric capacitors.As mentioned above, can use ferroelectric capacitor as electric capacity.

(20) be preferably: be connected with ferroelectric memory respectively on above-mentioned first bit line or above-mentioned second bit line, above-mentioned the 7th electric capacity and above-mentioned the 8th electric capacity are and the roughly the same electric capacity of ferroelectric capacitor that constitutes above-mentioned ferroelectric memory.According to such structure, eliminate the electric charge of (cancel) " 0 " data volume, and when bit line rises to positive potential, the counter-rotating of current potential of correction " 0 " data and the current potential of " 1 " data.

(21) for example, above-mentioned ferroelectric memory also comprises: a n channel-type MISFET is connected between the efferent and earthing potential of above-mentioned first phase inverter; And the 2nd n channel-type MISFET, be connected between the efferent and earthing potential of above-mentioned second phase inverter.

According to such structure, can promote the current potential of the side in first node, the Section Point by a n channel-type MISFET, the 2nd n channel-type MISFET.

(22) for example, above-mentioned ferroelectric memory also comprises: the 3rd n channel-type MISFET, be connected between the efferent and an above-mentioned n channel-type MISFET of above-mentioned first phase inverter, and grid is connected in the input part of above-mentioned first phase inverter; And the 4th n channel-type MISFET, being connected between the efferent and above-mentioned the 2nd n channel-type MISFET of above-mentioned second phase inverter, grid is connected in the input part of above-mentioned second phase inverter.

According to such structure, can reflect the potential difference (PD) of first bit line, second bit line by the 3rd n channel-type MISFET, the 4th n channel-type MISFET, simultaneously, can improve the current potential of the side in first node, the Section Point.

(23) an above-mentioned n channel-type MISFET and above-mentioned the 2nd n channel-type MISFET Be Controlled so that after the action of above-mentioned first negative potential generation circuit and the above-mentioned second negative potential generation circuit begins, and after during certain, become conducting state respectively.

According to such structure, by the above-mentioned first negative potential generation circuit and the second negative potential generation circuit, can limit a p channel-type MISFET at the initial stage of reading, the action of the 2nd p channel-type MISFET, and and then during certain in, the counter-rotating of current potential of correction " 0 " data and the current potential of " 1 " data, and can promote the current potential of the side in first node, the Section Point according to the suitable potential difference (PD) after correcting.Therefore, wrong judgement can be prevented, and the raising of tolerance limit can be realized reading.

(24) for example, above-mentioned ferroelectric memory also comprises: tricharged transmits MISFET, transmits MISFET with above-mentioned first electric charge and is connected in parallel, and grid is connected in the secondary signal line; And the 4th electric charge transmit MISFET, transmit MISFET with above-mentioned second electric charge and be connected in parallel, grid is connected in the secondary signal line.

According to such structure, can transmit the current potential that MISFET, the 4th electric charge transmission MISFET promote the side in first node, the Section Point by tricharged.

(25) for example, above-mentioned ferroelectric memory also comprises: the 3rd p channel-type MISFET, be connected between above-mentioned the 3rd node and the earthing potential, and grid is connected in the secondary signal line; And the 4th p channel-type MISFET, being connected between above-mentioned the 4th node and the earthing potential, grid is connected in the secondary signal line.

According to such structure, can promote the current potential of the side in first node, the Section Point by the 3rd p channel-type MISFET, the 4th p channel-type MISFET.

(26) for example, above-mentioned ferroelectric memory also comprises: the 5th p channel-type MISFET, be connected between the input part and power supply potential of above-mentioned first phase inverter, and grid is connected in the secondary signal line; And the 6th p channel-type MISFET, being connected between the input part and power supply potential of above-mentioned second phase inverter, grid is connected in the secondary signal line.

According to such structure, can promote the current potential of the side in first node, the Section Point by the 5th p channel-type MISFET, the 6th p channel-type MISFET.

(27) the current potential Be Controlled of preferred above-mentioned secondary signal line so that after the action of above-mentioned first negative potential generation circuit and the above-mentioned second negative potential generation circuit begins, and after during certain, changes.

According to such structure, can limit a p channel-type MISFET at the initial stage of reading, the action of the 2nd p channel-type MISFET, and and then during certain in, the counter-rotating of current potential of correction " 0 " data and the current potential of " 1 " data, and can promote the current potential of the side in first node, the Section Point according to the suitable potential difference (PD) after correcting.Therefore, wrong judgement can be prevented, and the raising of tolerance limit can be realized reading.

(28) for example, be connected with ferroelectric memory respectively on described first bit line and described second bit line.According to such structure, the present invention can be applicable to the ferroelectric storage cell of so-called 2T2C.

(29) for example, on above-mentioned first bit line, be connected with ferroelectric memory, be added with reference potential outside on above-mentioned second bit line.According to such structure, the present invention can be applicable to the ferroelectric storage cell of so-called 1T1C.

(30) electronic equipment that the present invention relates to has above-mentioned ferroelectric memory.According to such structure, can improve the characteristic of electronic equipment.

Description of drawings

Fig. 1 is the block diagram of expression ferroelectric memory;

Fig. 2 is the circuit diagram of formation of the sense amplifier circuit (sensing circuit) of expression first embodiment;

The synoptic diagram of the time diagram when Fig. 3 is reading of ferroelectric memory (sequential chart);

The synoptic diagram of the time diagram when Fig. 4 is reading of ferroelectric memory;

Fig. 5 is the pie graph of the sense amplifier circuit when not using cross-coupled p channel-type MISFETP1-L, P1-R;

Fig. 6 is in comparator circuit as shown in Figure 5, the synoptic diagram of the analog result when the ferroelectric condenser electric capacity of storage unit is big;

Fig. 7 is the circuit diagram of formation of the sense amplifier circuit (sensing circuit) of second embodiment;

The synoptic diagram of the time diagram when Fig. 8 is reading of ferroelectric memory;

The synoptic diagram of the time diagram when Fig. 9 is reading of ferroelectric memory;

Figure 10 in comparator circuit as shown in Figure 5, the synoptic diagram of the analog result of the ferroelectric condenser electric capacity of storage unit hour;

Figure 11 is in the circuit of Fig. 7, the synoptic diagram of the analog result when the ferroelectric condenser electric capacity of storage unit is big;

Figure 12 is the circuit diagram of formation of the sense amplifier circuit (sensing circuit) of the 3rd embodiment;

Figure 13 is the circuit diagram of formation of the sense amplifier circuit (sensing circuit) of the 4th embodiment;

Figure 14 is the circuit diagram of formation of the sense amplifier circuit (sensing circuit) of the 5th embodiment;

Time diagram when Figure 15 is the reading of ferroelectric memory of the 5th embodiment;

Time diagram when Figure 16 is the reading of ferroelectric memory of the 5th embodiment;

Figure 17 is in comparator circuit as shown in Figure 5, the time diagram the when output of electric charge is reversed in proper order;

Figure 18 is in circuit as shown in figure 12, the time diagram the when output of electric charge is reversed in proper order;

Figure 19 is in circuit as shown in figure 14, the time diagram the when output of electric charge is reversed in proper order;

Figure 20 is in the circuit of deletion behind the pull-up circuit from circuit as shown in figure 14, the time diagram the when current potential of bit line is changed to negative potential excessively;

Figure 21 is in circuit as shown in figure 14, the time diagram the when current potential of bit line is changed to negative potential too much;

Figure 22 is the circuit diagram of formation of the sense amplifier circuit (sensing circuit) of the 6th embodiment;

Figure 23 is the circuit diagram of formation of the sense amplifier circuit (sensing circuit) of the 7th embodiment;

Figure 24 is the circuit diagram of formation of the sense amplifier circuit (sensing circuit) of the 7th embodiment; And

Figure 25 is the circuit diagram of formation of the sense amplifier circuit (sensing circuit) of the 7th embodiment.

Embodiment

Below, with reference to accompanying drawing embodiments of the invention are described in detail.In addition, the parts with identical function have been marked identical or related symbol, and omitted repeat specification it.

(first embodiment)

Fig. 1 is the block diagram of the structure of expression ferroelectric memory.As shown in Figure 1, ferroelectric memory 100 comprises memory cell array 110, peripheral circuit portion (120,130,140 etc.).Memory cell array 110 comprises a plurality of storage unit that are configured to array-like, and each memory cell arrangements is on the intersection point of word line WL and bit line BL-L, BL-R.In addition, at this, be that example describes with the 2T2C unit.Therefore, store data by two transistors and two ferroelectric condensers of being connected to bit line BL-L and BL-R.And, constitute the word line control part 120 of peripheral circuit and the voltage of printed line control part 130 many word line WL of control and many printed line PL.By these control, the data that are stored among the storage unit MC are read (reading out to a plurality of bit lines) from a plurality of bit line BL, and, the data write storage unit MC that will provide from the outside by bit line BL.Carry out such reading, write in the line traffic control on the throne portion 140.

Fig. 2 is the circuit diagram of structure of the sense amplifier circuit (sensing circuit) of expression present embodiment.

As shown in Figure 2, (electric charge transmits MI SFET:Metal Insulator Semiconductor Field EffectTransistor: conductor insulator semiconductor fet) T2-L and T2-R are connected in first node Vmn-L and Section Point Vmn-R by p channel-type MISFET respectively for bit line BL-L and BL-R.

On the other hand, between first node Vmn-L and Section Point Vmn-R and earthing potential (reference potential, GND, Vss), be connected with tank capacitance C5-L and C5-R respectively.And, on first node Vmn-L and Section Point Vmn-R, be connected with negative potential generation circuit 17-L, 17-R by switching transistor VswmL, VswmR respectively.In addition, at this,, also can use para-electric (paraelectric) electric capacity though use ferroelectric capacitor as tank capacitance C5-L and C5-R.But,, then can obtain big electric capacity by small size if use ferroelectric capacitor.

By top structure, even transmit current potential to bit line BL-L, BL-R from storage unit, and the negative charge that first tank capacitance, second tank capacitance are stored transmits by p channel-type MISFETT2-L and T2-R, thereby can suppose bit line is fixed as earthing potential.Therefore, the major part that is applied to the read-out voltage of printed line can be applied to the ferroelectric condenser of storage unit, read tolerance limit (read-out margin) thereby can improve.And, can improve reading speed.In addition, owing to can reduce the influence of bit line capacitance, even, also can keep above-mentioned good characteristic because the electric capacity of storage unit becomes the length increase that causes bit line greatly.

Below, the circuit of Fig. 2 is described in further detail.

On the grid (node Vthg-L, Vthg-R) of above-mentioned p channel-type MISFETT2-L, T2-R,, be connected with threshold potential (Vth) circuit 15-L, 15-R take place respectively by switching transistor VswL, VswR.

And, between the grid of bit line BL-L, BL-R and p channel-type MISFETT2-L, T2-R, be connected with see-saw circuit 13-L, 13-R respectively.See-saw circuit 13-L, 13-R comprise phase inverter (inverter) INVL, INVR, capacitor C 1-L, C1-R, C2-L, C2-R and resistance R L, RR.

Particularly, the input part of bit line BL-L and phase inverter INVL is connected by capacitor C 1-L, and the grid of p channel-type MISFETT2-L is connected by capacitor C 2-R with the efferent of phase inverter INVL.And the input part of phase inverter INVL is connected by resistance R L with efferent.

Similarly, the input part of bit line BL-R and phase inverter INVR is connected by capacitor C 1-R, and the grid of p channel-type MISFETT2-R is connected by capacitor C 2-R with the efferent of phase inverter INVR.And the input part of phase inverter INVR is connected by resistance R R with efferent.

In addition, though above-mentioned see-saw circuit 13-L, 13-R use paraelectric capacitance as capacitor C 1-L, C1-R, C2-L, C2-R, also can use ferroelectric capacitor.This see-saw circuit 13-L, 13-R bring into play following effect: feed back to the grid of p channel-type MISFET by the current potential with bit line, be earthing potential thereby bit line more firmly fixed.

And, on first node Vmn-L and Section Point Vmn-R, be connected with positive potential translation circuit (L/S) 19-L, 19-R, by latch cicuit 20 potential difference (PD) of their output (signal) Vsf-L, Vsf-R is judged and read.

At this, in the present embodiment, between p channel-type MISFETT2-L, T2-R and first node Vmn-L, Section Point Vmn-R, be connected with p channel-type MISFETP1-L, P1-R respectively.And the grid of p channel-type MISFETP1-L is connected with Section Point Vmn-R, and the grid of p channel-type MISFETP1-R is connected with first node Vmn-L.Should cross-coupled p channel-type MISFETP1-L and P1-R as circuit 30.As described later, this circuit 30 is called as the big countermeasure circuit of electric charge.

Below, the action of reading of ferroelectric memory with above-mentioned sense amplifier circuit is described.Time diagram (simulation of current potential) when the reading of ferroelectric memory has been shown in Fig. 3 and Fig. 4.

Shown in Fig. 3 (A), with the control signal Vthgen of threshold potential generation circuit 15-L, 15-R as H level (noble potential level), and from the threshold potential of threshold potential generation circuit 15-L, 15-R output p channel-type MISFETT2-L, T2-R.At this moment, the common control signal Vsw of switching transistor VswL, VswR is the H level, and switching transistor VswL, VswR are conducting (ON) state (with reference to Fig. 3 (B)).Therefore, supply with threshold potential to the grid of p channel-type MISFETT2-L, T2-R.Then, with the current potential of word line WL as H level (with reference to the WL of Fig. 4).

And, control signal Vsw as L level (electronegative potential level), and is set at switching transistor VswL, VswR by (OFF) state.Thus, node Vthg-L, Vthg-R are (floating) state that suspends.

Then, the control signal Vmngen of negative potential generation circuit 17-L, 17-R as the H level, and is exported negative potential from negative potential generation circuit 17-L, 17-R.At this moment, the common control signal Vswm of switching transistor VswmR, VswmL is the H level, and switching transistor VswmR, VswmL are conducting state (with reference to Fig. 3 (D)).Therefore, first node Vmn-L and Section Point Vmn-R become negative potential.In other words, to tank capacitance C5-L, C5-R charging negative charge.

Next, control signal Vswm as the L level, and is set at cut-off state with switching transistor VswmL, VswmR.Thus, first node Vmn-L and Section Point Vmn-R are suspended state.

Then, with printed line PL as H level (with reference to the PL of Fig. 4).Consequently, charge storing unit is read out.In other words, charge storing unit is transferred into bit line BL-L, BL-R.

By the transmission of above-mentioned electric charge, the current potential of bit line BL-L, BL-R rises.The rising of amplifying this current potential in the mode of antiphase by see-saw circuit 13-L, 13-R reduces the current potential of node Vthg-L, Vthg-R.The variable quantity of this current potential (range of decrease) depends on the variable quantity (ascending amount) of the current potential of above-mentioned bit line.That is the quantity of electric charge poor of, depending on " 0 " data of storage unit and " 1 " data.

At this, if the current potential of node Vthg-L, Vthg-R descends then p channel-type MISFETT2-L, T2-R conducting.That is, transmit electric charge to the tank capacitance C5-L that is charged to negative potential, C5-R from bit line BL-L, BL-R.That is, the current potential of first node Vmn-L and Section Point Vmn-R rises.If all send charge storing unit to tank capacitance C5-L, C5-R, then the current potential of bit line BL-L, BL-R descends, and the current potential of node Vthg-L, Vthg-R rises, p channel-type MISFETT2-L, T2-R conducting.Therefore, the rising of the current potential of first node Vmn-L and Section Point Vmn-R stops.At this moment, owing to " 0 " data of storage unit and the quantity of electric charge of " 1 " data cause the potential change of first node Vthg-L and Section Point Vthg-R different, corresponding, the ascensional range difference of the current potential of first node Vmn-L and Section Point Vmn-R.That is,, between first node Vmn-L and Section Point Vmn-R, produce potential difference (PD) because the quantity of electric charge of " 0 " data and " 1 " data is poor.

At this, in the present embodiment, as mentioned above, owing in sense amplifier circuit, comprise cross-coupled p channel-type MISFETP1-L, P1-R (30), so can carry out following action.

That is, in first node Vmn-L and Section Point Vmn-R, be in more that a side of noble potential at first reaches the threshold potential (Vth) of p channel-type MISFETP1-L, P1-R, and the p channel-type MISFET of the opposing party's side is ended.In Fig. 4 and since Section Point Vmn-R at first reach threshold potential (this for-0.7V), so p channel-type MISFETP1-L ends.Consequently, the current potential of first node Vmn-L rises and stops (with reference to Vmn-R, the Vmn-L of Fig. 4).

As mentioned above, in the present embodiment, the current potential that suppresses the side among first node Vmn-L and the Section Point Vmn-R owing to the current potential of not scrupling node Vthg-L, Vthg-R rises, so can guarantee their potential difference (PD) significantly.Therefore, can improve and read tolerance limit.

Below, with reference to comparator circuit (Fig. 5), the effect of present embodiment is described in further detail.

Fig. 5 is the pie graph of the sense amplifier circuit when not using cross-coupled p channel-type MISFETP1-L, P1-R.In addition, the place identical with Fig. 2 marked identical symbol, and omitted detailed description thereof.In circuit as shown in Figure 5, p channel-type MISFETT2-L and T2-R are directly connected in first node Vmn-L and Section Point Vmn-R respectively.

In such circuit, when the ferroelectric condenser electric capacity of (1) storage unit and initial setting produce bigger skew, during the ratio marked change of ferroelectric condenser electric capacity of (2) storage unit and tank capacitance, read the tolerance limit reduction.

Analog result when for example, the ferroelectric condenser electric capacity of storage unit (quantities of electric charge of " 0 " data) is big as shown in Figure 6.In addition, this situation is called as following this situation: the ferroelectric condenser electric capacity of storage unit is compared with tank capacitance, and is relatively large.

In this case, as shown in Figure 6, corresponding first node Vmn-L rises significantly with " 0 " data.On the other hand, owing to only rise to regulation current potential (being 0.7V this moment) with the corresponding Section Point Vmn-R of " 1 " data, so cause the potential difference (PD) of first node Vmn-L and Section Point Vmn-R to diminish.Therefore, corresponding, cause the output Vsf-L of positive potential translation circuit 19-L, 19-R and the potential difference (PD) of Vsf-R also to diminish.In the positive potential conversion, owing to produce common conversion loss (loss), and then potential difference (PD) diminishes.

Relative therewith, in the present embodiment, as mentioned above, owing to suppress the rising of the current potential (being Vmn-L) of the side among first node Vmn-L and the Section Point Vmn-R in Fig. 4, so can guarantee their potential difference (PD) significantly.In other words, the potential difference (PD) of first node Vmn-L and Section Point Vmn-R can be set at more than the Vth.Therefore, can increase the output Vsf-L of positive potential translation circuit 19-L, 19-R and the potential difference (PD) of Vsf-R.That is, the current potential of first node Vmn-L and Section Point Vmn-R is owing to be converted to positive potential from negative potential, need latch that this is poor.Therefore, the potential difference (PD) of the output Vsf-L of positive potential translation circuit 19-L, 19-R and Vsf-R become big rule constantly between after, conducting latch cicuit 20, and read output signal exported as digital signal (H or L).

As mentioned above, can increase the output Vsf-L of positive potential translation circuit 19-L, 19-R and the potential difference (PD) of Vsf-R.And, owing to can guarantee the potential difference (PD) that Vth is above at least, can not scruple the potential difference (PD) that the setting (setting) of positive potential translation circuit increases output Vsf-L and Vsf-R (conversion loss).

What as above described in detail is the same, according to present embodiment, can improve and read tolerance limit.And, can improve and read characteristic.In addition, in Fig. 4 and Fig. 6, also show the potential change of node Vthg-L, Vthg-R.

(second embodiment)

In first embodiment, though the countermeasure to the ferroelectric condenser electric capacity (quantities of electric charge of " 0 " data) of storage unit when big is illustrated, but will the countermeasure of ferroelectric condenser electric capacity (quantities of electric charge of " 1 " data) hour be described in the present embodiment.In addition, this situation is also referred to as following this situation: the ferroelectric condenser electric capacity of storage unit is compared with tank capacitance, and is less relatively.The place identical with first embodiment marked identical symbol, and omitted detailed description thereof.

Fig. 7 is the circuit diagram of structure of the sense amplifier circuit (sensing circuit) of expression present embodiment.In circuit as shown in Figure 7, circuit 40 is installed as the little countermeasure circuit of electric charge.

That is, on the 3rd node Vc-L, the 4th node Vc-R, be connected with p channel-type MISFETP3-L, P3-R as the connected node between p channel-type MISFETT2-L, T2-R and p channel-type MISFETP1-L, the P1-R.

Particularly, between the 3rd node Vc-L and earthing potential, be connected with p channel-type MISFETP3-L, between the 4th node Vc-R and earthing potential, be connected with p channel-type MISFETP3-R.The grid of p channel-type MISFETP3-L and P3-R is connected in signal wire Vupb by capacitor C 7.And the back of the body grid of p channel-type MISFETP3-L and P3-R (back gate) are connected in earthing potential.By connecting in this wise, can reduce leakage current to substrate.In addition, represent signal wire and signal by identical symbol.And, at this,, also can use ferroelectric capacitor though use paraelectric capacitance as capacitor C 7.

Next, the action of reading to ferroelectric memory with above-mentioned sensor amplifier describes.Time diagram when the reading of ferroelectric memory has been shown in Fig. 8 and Fig. 9.In addition, to the action identical with first embodiment, detailed description thereof will be omitted, and only 40 related actions are elaborated to circuit.In addition, Fig. 8 (A)～Fig. 8 (D) is identical waveform with Fig. 3 (A)～Fig. 3 (D).

As among first embodiment with reference to Fig. 3 etc. illustrated, control signal Vthgen as H level (with reference to Fig. 3 (A), Fig. 8 (A)), and is supplied with threshold potential to p channel-type MISFETT2-L, T2-R.Then, with the current potential of word line WL as H level (with reference to the WL of Fig. 9).And, control signal Vsw as L level (with reference to Fig. 3 (B), Fig. 8 (B)), is set at suspended state with node Vthg-L, Vthg-R.Then, control signal Vmngen is set at H level (with reference to Fig. 3 (C), Fig. 8 (C)), to tank capacitance C5-L, C5-R charging negative charge.Next, control signal Vswm as L level (with reference to Fig. 3 (D), Fig. 8 (D)), and is set at suspended state with first node Vmn-L and Section Point Vmn-R.

Then, printed line PL is set at H level (with reference to the PL of Fig. 9).Consequently, as illustrated among first embodiment, charge storing unit is sent to bit line BL-L, BL-R.And the current potential of first node Vmn-L and Section Point Vmn-R rises.

At this, in the present embodiment, as mentioned above, owing to comprise p channel-type MISFETP3-L and P3-R (40), so can carry out following action.

That is, shown in Fig. 8 (E), during certain (for example, from printed line PL rise begin through during behind the t1), control signal Vup is set at the H level.That is, will be set at the L level as the Vupb of the reverse signal of Vup.Therefore, transmit signal by capacitor C 7, p channel-type MISFETP3-L and P3-R become conducting state.Therefore, be connected with earthing potential, rise as the first node Vmn-L and the Section Point Vmn-R of negative potential as the 3rd node Vc-L and the 4th node Vc-R of negative potential.

After this, with in first embodiment, describe in detail the same, in first node Vmn-L and Section Point Vmn-R, be in the threshold potential (Vth) that a side of noble potential at first reaches p channel-type MISFETP1-L, P1-R, and by the p channel-type MISFET of the opposing party's side.In Fig. 9 and since Section Point Vmn-R at first reach threshold potential (this for-0.7V), so p channel-type MISFET ends.Consequently, the current potential of first node Vmn-L rises and stops (with reference to Vmn-R, the Vmn-L of Fig. 9).

As mentioned above, in the present embodiment, because the ferroelectric condenser electric capacity of storage unit is little, so the time from storage unit transmission electric charge, even under the few situation of the current potential rising of first node Vmn-L and Section Point Vmn-R, also can guarantee their potential difference (PD) significantly.Therefore, can improve and read tolerance limit.

Below, with reference to above-mentioned comparator circuit (Fig. 5), the effect of present embodiment is described in further detail.

In comparator circuit as shown in Figure 5, the analog result of the ferroelectric condenser electric capacity of storage unit (quantities of electric charge of " 1 " data) hour as shown in figure 10.

In this case, as shown in figure 10, finish earlier to transmit (extraction) current potential, thereby cause rising with the current potential of the corresponding Section Point Vmn-R of " 1 " data from storage unit.Therefore, the potential difference (PD) of first node Vmn-L and Section Point Vmn-R diminishes, and is relative therewith, causes the output Vsf-L of positive potential translation circuit 19-L, 19-R and the potential difference (PD) of Vsf-R also to diminish.In the positive potential conversion, owing to produce common conversion loss (loss), and then potential difference (PD) diminishes.

Relative therewith, in the present embodiment, as mentioned above,, the current potential of first node Vmn-L and Section Point Vmn-R can be risen to the current potential of circuit 30 actions by p channel-type MISFETP3-L, P3-R (40).And, the potential difference (PD) of first node Vmn-L and Section Point Vmn-R can be set at more than the Vth.

Therefore, can increase the output Vsf-L of positive potential translation circuit 19-L, 19-R and the potential difference (PD) of Vsf-R.And, owing to can guarantee the potential difference (PD) that Vth is above at least, can not scruple the potential difference (PD) that the setting of positive potential translation circuit increases output Vsf-L and Vsf-R (conversion loss).Consequently, can improve and read tolerance limit.Can improve and read characteristic.In addition, in Fig. 9 and Figure 10, also show the potential change (Figure 11 is also identical) of node Vthg-L, Vthg-R.

Certainly in the present embodiment owing to possess circuit 30, so even to as in first embodiment big situation of ferroelectric condenser electric capacity that described in detail, storage unit (quantities of electric charge of " 0 " data), also can be in addition corresponding.

Figure 11 illustrates in the circuit of Fig. 7 the analog result when the ferroelectric condenser electric capacity of storage unit (quantities of electric charge of " 0 " data) is big.In this case, before control signal Vup was set at the moment of H level, circuit 30 moved, thereby can guarantee the potential difference (PD) of first node Vmn-L and Section Point Vmn-R.The explanation of the action of circuit 30 sees first embodiment for details.Therefore, the result of Figure 11 and Fig. 4's comes to the same thing.

Above-mentioned described, according to present embodiment, no matter can be in addition corresponding under the big situation of the ferroelectric condenser electric capacity of storage unit still is little situation.

And, can constitute tank capacitance C5-L, C5-R by for example gate capacitance.So-called gate capacitance is meant the electric capacity that the conducting film by the dielectric film on substrate and the substrate and this top constitutes, and this conducting film can be formed by the grid identical materials (operation) with MISFET.

That is, when forming tank capacitance, because the piezoelectric property of their electric capacity is different with temperature characterisitic, so under user mode, be difficult to control so that become the electric capacity of regulation by the material different with the ferroelectric capacitor that constitutes storage unit.But,,, as mentioned above, also can be compensated by circuit 30 and circuit 40 even their capacity ratio changes according to present embodiment.Therefore, can constitute tank capacitance by gate capacitance.If constitute tank capacitance by gate capacitance, then compare with ferroelectric capacitor, can reduce the operation error.Can certainly use conducting film beyond the gate capacitance (for example, distribution etc.) to constitute tank capacitance.

(the 3rd embodiment)

In the present embodiment, other configuration examples to the little countermeasure circuit of electric charge (40) describe.In addition, to having marked identical symbol, and omit detailed description thereof with first embodiment, place that second embodiment is identical.

Figure 12 is the circuit diagram of structure of the sense amplifier circuit (sensing circuit) of expression present embodiment.In circuit as shown in figure 12, circuit 40A-L, 40A-R are installed as the little countermeasure circuit of electric charge.

That is, between the efferent of phase inverter INVL and earthing potential, be connected with n channel-type MISFETN1-L, between the efferent of phase inverter INVR and earthing potential, be connected with n channel-type MISFETN1-R.The grid of these n channel-types MISFETN1-L, N1-R is connected with signal wire Vup.

Next, the action of reading to ferroelectric memory with above-mentioned sensor amplifier describes.The action of various signals etc. is identical with second embodiment (Fig. 8, Fig. 9).Therefore, at this, only control signal Vup is described to the later circuit 40A-L of H level variation, the action of 40A-R.

Shown in Fig. 8 (E), begin through back during certain (for example, beginning through behind the t1) from reading action from the rising of printed line PL, if control signal Vup is set at the H level, then n channel-type MISFETN1-L, N1-R become conducting state.Therefore, the current potential of the efferent of phase inverter INBL, INBR reduces, and is corresponding, and the current potential of node Vthg-L, Vthg-R reduces.Therefore, p channel-type MISFETT2-L, T2-R become conducting state, and bit line BL-L, BL-R are connected with first node Vmn-L and Section Point Vmn-R as the negative potential node.Consequently, the current potential of first node Vmn-L and Section Point Vmn-R rises.That is, if finish to transmit (extractions) electric charge from storage unit, and the potential change of node Vthg-L, Vthg-R do not exist, and then ends p channel-type MISFETT2-L, T2-R.But, at this, force conducting p channel-type MISFETT2-L, T2-R, and the current potential of first node Vmn-L and Section Point Vmn-R risen by n channel-type MISFETN1-L, N1-R.

After this, as illustrated in a second embodiment, in first node Vmn-L and Section Point Vmn-R, be in the threshold potential that a side of noble potential at first reaches p channel-type MISFETP1-L, P1-R, and by the p channel-type MISFET of the opposing party's side.In Fig. 9 and since Section Point Vmn-R at first reach threshold potential (this for-0.7V), so p channel-type MISFETP1-L ends.Consequently, the current potential of first node Vmn-L rises and stops (with reference to Vmn-R, the Vmn-L of Fig. 9).

As mentioned above, also the same in the present embodiment with second embodiment, even under the little situation of the big ferroelectric condenser electric capacity of storage unit, also can guarantee the potential difference (PD) of first node Vmn-L and Section Point Vmn-R significantly.Therefore, can improve and read tolerance limit.Certainly in the present embodiment owing to possess circuit 30, so even as the situation that ferroelectric condenser electric capacity that described in detail, storage unit is big in first embodiment under, also can be in addition corresponding.

(the 4th embodiment)

In the present embodiment, further other configuration examples of the little countermeasure circuit of electric charge (40) are described.In addition, the place identical with first embodiment, second embodiment and the 3rd embodiment marked identical symbol, and omitted detailed description thereof.

Figure 13 is the circuit diagram of structure of the sense amplifier circuit (sensing circuit) of expression present embodiment.In circuit as shown in figure 13, circuit 40B-L, 40B-R are installed as the little countermeasure circuit of electric charge.

That is, between the input part of phase inverter INVL and power supply potential (driving current potential, Vcc, Vdd), be connected with p channel-type MISFETP2-L, between the input part of phase inverter INVR and power supply potential, be connected with p channel-type MISFETP2-R.The grid of these p channel-types MISFETP2-L, P2-R is connected with signal wire Vupb.

Next, the action of reading to ferroelectric memory with above-mentioned sensor amplifier describes.The action of various signals etc. is identical with second embodiment (Fig. 8, Fig. 9).Therefore, at this, only control signal Vupb is described to the later circuit 40B-L of L level variation, the action of 40B-R.

Shown in Fig. 8 (E), (for example begin from reading action through back during certain, begin through behind the t1 from the rising of printed line PL), if control signal Vup is set at the H level, then will be set at the L level, and p channel-type MISFETP2-L, P2-R will be become conducting state as the Vupb of the reverse signal of Vup.Therefore, the current potential of the input part of phase inverter INBL, INBR rises, and the current potential of the efferent of phase inverter INBL, INBR descends.Corresponding, the current potential of node Vthg-L, Vthg-R reduces.Therefore, p channel-type MISFETT2-L, T2-R become conducting state, and bit line BL-L, BL-R are connected with first node Vmn-L and Section Point Vmn-R as the negative potential node.Consequently, the current potential of first node Vmn-L and Section Point Vmn-R rises.That is, if finish to transmit (extraction) electric charge from storage unit, and the potential change of node Vthg-L, Vthg-R do not exist, and then p channel-type MISFETT2-L, T2-R end.But,,, and the current potential of first node Vmn-L and Section Point Vmn-R is risen by p channel-type MISFETP2-L, P2-R conducting p channel-type MISFETT2-L, T2-R forcibly at this.

After this, as illustrated in a second embodiment, in first node Vmn-L and Section Point Vmn-R, be in the threshold potential that a side of noble potential at first reaches p channel-type MISFETP1-L, P1-R, and the p channel-type MISFET that surveys by the opposing party.In Fig. 9 and since Section Point Vmn-R at first reach threshold potential (this for-0.7V), so p channel-type MISFETP1-L ends.Consequently, the current potential of first node Vmn-L rises and stops (with reference to Vmn-R, the Vmn-L of Fig. 9).

As mentioned above, also the same in the present embodiment with second embodiment, even under the little situation of the ferroelectric condenser electric capacity of storage unit, also can guarantee the potential difference (PD) of first node Vmn-L and Section Point Vmn-R significantly.Therefore, can improve and read tolerance limit.Certainly in the present embodiment owing to possess circuit 30, so even as the situation that ferroelectric condenser electric capacity that described in detail, storage unit is big in first embodiment under, also can be in addition corresponding.

Next, the effect to the little countermeasure circuit of the illustrated electric charge of second embodiment～the 4th embodiment (40,40A-L/R, 40B-L/R) is described further.

In the little countermeasure circuit 40 of electric charge of second embodiment,, draw (pull up) first node Vmn-L and Section Point Vmn-R on can be positively by control signal Vupb.And, owing to separately control bit line BL-L, BL-R, so be difficult to give noise to bit line BL-L, BL-R.

In the little countermeasure circuit of electric charge 40A-L/R, the 40B-L/R of the 3rd embodiment and the 4th embodiment, need not to be formed for controlling the capacitor C 7 of MISFET at positive potential, so can realize dwindling circuit area.

And, in the little countermeasure circuit of the electric charge 40B-L/R of the 4th embodiment, because the current potential of the input side of control phase inverter INVL, INVR, thus the input and output current potential of phase inverter INVL, INVR can be fixed on H level and L level, thus can reduce perforation electric current.

In addition, in the above-described embodiments, though the ferroelectric memory with 2T2C is that example is illustrated, the present invention also goes for adding to a side bit line the ferroelectric memory of reference potential 1T1C (for example, the 1T1C of open stance line style (open bit tape)).

(the 5th embodiment)

Figure 14 is the circuit diagram of structure of the sense amplifier circuit (sensing circuit) of expression present embodiment.In circuit as shown in figure 14, negative potential generation circuit 50-L, 50-R and pull-up circuit (the little countermeasure circuit of electric charge) circuit 41A-L, 41A-R are installed.In addition, in the following description, to having marked symbol identical or that be associated, and omit explanation to its repetition with place that first embodiment～the 4th embodiment is identical.And, in the following description, represent signal wire and signal (current potential) by identical symbol.

That is, negative potential generation circuit 50-L, 50-R have capacitor C 8-R, C8-L respectively, and capacitor C 8-R is connected between bit line BL-R and the signal wire Vblm, and capacitor C 8-L is connected between bit line BL-L and the signal wire Vblm.In addition, at this,, also can use paraelectric capacitance though use ferroelectric capacitor as capacitor C 8-R, C8-L.

And pull-up circuit 41A-L, 41A-R have two n channel-type MISFET (N2-L and N1-L, N2-R and N1-R) respectively.Promptly, between the efferent of phase inverter INVL and earthing potential (reference potential, GND, Vss), be connected in series with n channel-type MISFETN2-L and N1-L, the grid of n channel-type MISFETN2-L is connected with the input part of phase inverter INVL, and the grid of n channel-type MISFETN1-L is connected with signal wire Vup.And, between the efferent of phase inverter INVL and earthing potential, be connected in series with n channel-type MISFETN2-R and N1-R, the grid of n channel-type MISFETN2-R is connected with the input part of phase inverter INVR, and the grid of n channel-type MISFETN1-R is connected with signal wire Vup.

It is identical that other structures and first are implemented (Fig. 2).Explanation simply, bit line BL-L and BL-R by two p channel-type MISFETT2-L and P1-L, T2-R and P1-R, are connected in first node Vmn-L and Section Point Vmn-R respectively.The connected node of this p channel-type MISFETT2-L and P1-L is set at Vc-L, the connected node of p channel-type MISFETT2-R and P1-R is set at Vc-R.

On the other hand, be connected with tank capacitance C5-L and C5-R respectively between first node Vmn-L and Section Point Vmn-R and the earthing potential.

And, on first node Vmn-L and Section Point Vmn-R, by switching transistor VswmL, VswmR, be connected with negative potential generation circuit 17-L, 17-R respectively.

And, on first node Vmn-L and Section Point Vmn-R, be connected with positive potential translation circuit (L/S) 19-L, 19-R, by latch cicuit 20 potential difference (PD) of these outputs (signal) Vsf-L, Vsf-R is judged and read.

And, on the grid (node Vthg-L, Vthg-R) of above-mentioned p channel-type MISFETT2-L, T2-R,, be connected with threshold potential (Vth) circuit 15-L, 15-R take place respectively by switching transistor VswL, VswR.

And, between the grid of bit line BL-L, BL-R and p channel-type MISFETT2-L, T2-R, be connected with see-saw circuit (control circuit, feedback circuit) 13-L, 13-R respectively.See-saw circuit 13-L, 13-R constitute and comprise phase inverter INVL, INVR, capacitor C 1-L, C1-R, C2-L, C2-R and resistance R L, RR.These resistance R L, RR also can be switching transistor.

Particularly, the input part of bit line BL-L and phase inverter INVL is connected by capacitor C 1-L, and the grid of p channel-type MISFETT2-L is connected by capacitor C 2-L with the efferent of phase inverter INVL.And the input part of phase inverter INVL is connected by resistance R L with efferent.

And the grid of p channel-type MISFETP1-L is connected with Section Point Vmn-R, and the grid of p channel-type MISFETP1-R is connected with first node Vmn-L.Should cross-coupled p channel-type MISFETP1-L and P1-R be called circuit 30 (the big countermeasure circuit of electric charge).

Next, the action of reading to ferroelectric memory with above-mentioned sense amplifier circuit describes.Time diagram when the reading of ferroelectric memory of present embodiment has been shown in Figure 15 and Figure 16.Transverse axis express time [ns], the longitudinal axis are represented current potential [V].

Shown in Figure 15 (A), with the control signal Vthgen of threshold potential generation circuit 15-L, 15-R as H level (noble potential level), and from the threshold potential of threshold potential generation circuit 15-L, 15-R output p channel-type MISFETT2-L, T2-R.At this moment, the common control signal Vsw of switching transistor VswL, VswR is the H level, and switching transistor VswL, VswR are conducting (ON) state (with reference to Figure 15 (B)).Therefore, supply with threshold potential to the grid of p channel-type MISFETT2-L, T2-R.

Then, control signal Vsw as L level (electronegative potential level), and is set at switching transistor VswL, VswR by (OFF) state.Thus, node Vthg-L, Vthg-R are suspended state.

Then, with the current potential of word line WL as H level (with reference to the WL of Figure 16).And then, with the control signal Vmngen of negative potential generation circuit 17-L, 17-R as the H level, and from negative potential generation circuit 17-L, 17-R output negative potential (with reference to Figure 15 (C)).At this moment, the common control signal Vswm of switching transistor VswmR, VswmL is the H level, and switching transistor VswmR, VswmL are conducting state (with reference to Figure 15 (D)).Therefore, first node Vmn-L and Section Point Vmn-R are negative potential.In other words, to tank capacitance C5-L, C5-R charging negative charge.

Next, signal Vblm is changed (with reference to Figure 15 (E)) from the H level to the L level, and the current potential of bit line BL-L, BL-R is descended.That is, the current potential with bit line BL-L, BL-R is changed to negative potential from earthing potential.For example, before and after the 15ns of Figure 16, can confirm: the current potential of bit line BL-L, BL-R is near some negative potentials that the drop to 0V.In addition, the decline of signal Vblm (from the variation of H level to the L level) also can be not limited in this moment for the front and back of the rising (reading) of printed line PL.

To potential change that should bit line BL-L, BL-R, the current potential of node Vthg-L and Vthg-R rises.That is, the current potential of corresponding bit line BL-L, BL-R descends, and the current potential of the input part of phase inverter INVL, INVR descends, and the current potential of efferent rises.Therefore, the current potential of node Vthg-L and Vthg-R rises.

Next, control signal Vswm is set at the L level, and switching transistor VswmR, VswmL are set at cut-off state (with reference to Figure 15 (D)).Thus, first node Vmn-L and Section Point Vmn-R are suspended state.

Then, with printed line PL as H level (with reference to the PL of Figure 16).Consequently, charge storing unit is read out.In other words, charge storing unit is transferred into bit line BL-L, BL-R.

At this, if the current potential of node Vthg-L, Vthg-R descends then p channel-type MISFETT2-L, T2-R conducting.That is, transmit electric charge to the tank capacitance C5-L that is charged to negative potential, C5-R from bit line BL-L, BL-R.That is, the current potential of first node Vmn-L and Section Point Vmn-R rises.If charge storing unit all is sent to tank capacitance C5-L, C5-R, then the current potential of bit line BL-L, BL-R descends, and the current potential of node Vthg-L, Vthg-R rises, and p channel-type MISFETT2-L, T2-R end.Therefore, the rising of the current potential of first node Vmn-L and Section Point Vmn-R stops.At this moment, owing to " 0 " data of storage unit and the quantity of electric charge of " 1 " data cause the potential change of node Vthg-L, Vthg-R different, corresponding, the ascensional range difference of the current potential of first node Vmn-L and Section Point Vmn-R.That is,, between first node Vmn-L and Section Point Vmn-R, produce potential difference (PD) because the quantity of electric charge of " 0 " data and " 1 " data is poor.

The effect of the big countermeasure circuit of electric charge

At this, in the present embodiment, as describing in detail among first embodiment, owing in sense amplifier circuit, comprise cross-coupled p channel-type MISFETP1-L, P1-R (30), so can carry out following action.

That is, in first node Vmn-L and Section Point Vmn-R, be in the threshold potential (Vth) that a side of noble potential at first reaches p channel-type MISFETP1-L, P1-R, and by the p channel-type MISFET of the opposing party's side.In Figure 16 and since Section Point Vmn-R at first reach threshold potential (this for-0.7V), so p channel-type MISFET ends.Consequently, the current potential of first node Vmn-L rises and stops (with reference to Vmn-R, the Vmn-L of Figure 16).

As mentioned above, the current potential that suppresses the side among first node Vmn-L and the Section Point Vmn-R owing to the current potential of not scrupling node Vthg-L, Vthg-R rises, so can guarantee their potential difference (PD) significantly.Therefore, can improve and read tolerance limit.

First effect of pull-up circuit

Next, shown in Figure 15 (E), during certain (for example, from the decline of signal Vblm begin through during behind the t2) after, control signal Vup is set at the H level.Therefore, n channel-type MISFETN1-L, N1-R are conducting state.At this, the grid of n channel-type MISFETN2-L or N2-R is added and prima facies ratio, the voltage about 1/2Vcc.This is owing to be connected caused by resistance R R with the input and output portion of phase inverter (INVL, INVR).Therefore, n channel-type MISFETN2-L or N2-R are the state from initial some conductings, the rising of the current potential of corresponding bit line BL-L, BL-R (current potential of the input part of phase inverter INVL, INVR), and the degree of conducting (conducting electric current) rises.

Because when the rising of above-mentioned control signal Vup, so n channel-type MISFETN1-L, N1-R conducting are the decline of the current potential of node Vthg-L, Vthg-R.The potential difference (PD) of the degree that this current potential descends corresponding BL-L, BL-R and changing.Therefore, can make p channel-type MISFETT2-L, T2-R become conducting state, and the current potential of first node Vmn-L and Section Point Vmn-R is risen.

Then, as mentioned above, in first node Vmn-L and Section Point Vmn-R, be in the threshold potential that a side of noble potential at first reaches p channel-type MISFETP1-L, P1-R, and by the p channel-type MISFET of the opposing party's side.

As mentioned above, can make the current potential of first node Vmn-L and Section Point Vmn-R rise to the current potential (with reference to second embodiment～the 4th embodiment) of circuit 30 actions by pull-up circuit 41A-L, 41A-R.

And, in the present embodiment, the current potential of corresponding bit line BL-L, BL-R, the conducting degree of n channel-type MISFETN2-L or N2-R (conducting electric current) difference.Therefore, the potential difference (PD) of bit line BL-L, BL-R can be reflected, simultaneously, near the current potential (17～30ns with reference to Figure 16) of node Vthg-L, Vthg-R can be reduced.That is, the potential difference (PD) of bit line BL-L, BL-R can be reflected, simultaneously, the current potential of first node Vmn-L and Section Point Vmn-R can be improved.Therefore, can realize further improving reading tolerance limit.

Then, by 20 pairs of latch cicuits be connected to output (signal) Vsf-L of positive potential translation circuit (L/S) 19-L, 19-R on first node Vmn-L and the Section Point Vmn-R, the potential difference (PD) of Vsf-R is judged, thereby is read.

The effect of negative potential generation circuit

And, in the present embodiment,, can realize improving reading accuracy (reducing wrong judgement) because negative potential generation circuit 50-L, 50-R are installed.

For example, when the reading of storage unit, in " 0 " data and " 1 " data, " 1 " data to read the quantity of electric charge more.But, when when ferroelectric properties is produced special deterioration or by foozle, causing producing the area discrepancy of ferroelectric capacitor, have following situation: the current potential that temporarily potential setting of " 0 " data side must be higher than " 1 " data side.This situation is called as the situation of the output order of the electric charge that reverses.

Figure 17 is in comparator circuit (Fig. 5), the time diagram during counter-rotating electric charge output order.As shown in figure 17, the current potential of bit line BL-L (dotted line) is greater than near the current potential (for example, with reference to the 20ns) of bit line BL-R.Thereupon, become Vthg-L＜Vthg-R, Vmn-L＞Vmn-R.But finally be: the current potential of bit line BL-R is greater than the current potential of bit line BL-L, i.e. Vmn-L＜Vmn-R.

Figure 18 is in circuit as shown in figure 12, the time diagram in output when order of counter-rotating electric charge.As shown in figure 18, the current potential of bit line BL-L (dotted line) is greater than near the current potential (for example, with reference to the 20ns) of bit line BL-R.Thereupon, become Vthg-L＜Vthg-R, and carry out and Vmn-L＞Vmn-R is corresponding reads (mistake judgement).

Figure 19 is in the circuit (Figure 14) at present embodiment, the time diagram during the output order of counter-rotating electric charge.As shown in figure 19, originally the current potential of bit line BL-L (dotted line) is greater than near the current potential (for example, 20ns) of bit line BL-R, though after the relation that corrects them, the judgement based on Vmn-L＜Vmn-R is still finally carried out in the rising of start node Vmn-L and Vmn-R.That is, improve wrong judgement.And as shown in figure 17, it is big that the potential difference (PD) of node Vmn-L and Vmn-R becomes.That is, reading tolerance limit improves.

The above-mentioned wrong improvement of judging is the effect of negative potential generation circuit 50-L, 50-R.That is, bit line BL-L, BL-R are changed to negative potential, thereby the current potential of node Vthg-L, Vthg-R is risen, and can limit the action of first, second p channel-type MISFET at the initial stage of reading by negative potential generation circuit 50-L, 50-R.That is, can postpone the moment of p channel-type MISFETT2-L and T2-R conducting.In other words, can shelter the action that (mask) reads first, second p channel-type MISFET at initial stage.

Therefore, though the output of the electric charge that temporarily reverses order, but till p channel-type MISFETT2-L and T2-R conducting, can correct their relation.

Therefore, after the current potential of " 1 " data side becomes the current potential that is higher than " 0 " data side, can conducting p channel-type MISFETT2-L, T2-R, and near the current potential that can begin node Vmn-L, Vmn-R rise (30ns with reference to Figure 19).

In addition, after the current potential of " 1 " data side becomes the current potential that is higher than " 0 " data side,, thereby can force to reduce the current potential of node Vthg-L, Vthg-R by rising signals Vup.Therefore, can more apace the current potential of first node Vmn-L or Section Point Vmn-R be risen to the current potential of circuit 30 actions.

And preferably capacitor C 8-L, the C8-R with negative potential generation circuit 50-L, 50-R is set at and the roughly the same electric capacity of ferroelectric capacitor that constitutes ferroelectric condenser.Roughly the same electric capacity for example is meant, is formed to design identical size by identical materials.According to such structure, eliminate the electric charge of (cancel) " 0 " data volume, and when bit line rises to positive potential, the counter-rotating of current potential of correction " 0 " data and the current potential of " 1 " data.

In addition, even in the circuit of above-mentioned Figure 12, for example carry out, adjust the operation of tank capacitance C5-L and C5-R etc., and the potential difference (PD) of try every possible means not produce at the initial stage of reading node Vthg-L, Vthg-R with box lunch, thereby can prevent wrong judgement, simultaneously, can obtain and effect illustrated in the 3rd embodiment.

Second effect of pull-up circuit

And, in the present embodiment, preferably also use pull-up circuit 41A-L, 41A-R for bit line BL-L, BL-R are changed to negative potential.

That is, in the present embodiment, have following situation: by bit line BL-L, BL-R, the electric charge that reads into node Vmn-R, Vmn-L tails off.For example, when the degradation of capacitor C 8-L, the C8-R of ferroelectric capacitor that constitutes storage unit and negative potential generation circuit does not wait simultaneously, become the state that bit line is changed to too much negative potential.

Figure 20 is in the circuit of deletion after drawing amplifier circuit from circuit as shown in figure 14, the time diagram the when current potential of bit line is changed to negative potential excessively.That is, in Figure 20, compare with Figure 16, bit line BL-L, BL-R become big to the variation of negative potential.In this case, as shown in figure 20, rising with the current potential of the corresponding node Vmn-R of " 1 " data diminishes, and then the potential difference (PD) of node Vmn-L and Vmn-R also diminishes.Therefore, causing reading tolerance limit diminishes.

Figure 21 is in circuit as shown in figure 14, the time diagram the when current potential of bit line is changed to negative potential too much.In this case, illustrated as top " effect of pull-up circuit " part, by pull-up circuit 41A-R, 41A-L, can make the current potential of first node Vmn-L and Section Point Vmn-R rise to the current potential of circuit 30 actions, and can realize reading the raising of tolerance limit.

The 6th embodiment

Figure 22 is the circuit diagram of formation of the sense amplifier circuit (sensing circuit) of present embodiment.Change pull-up circuit 41A-L, the 41A-R of Figure 14 (the 5th embodiment) and the pull-up circuit 41B that packs into.

That is, between bit line BL-L and BL-R and p channel-type MISFETP1-L, P1-R, be connected with p channel-type MISFETP4-L, P4-R respectively, on the grid of they (P4-L, P4-R), be connected with signal wire Vupb by capacitor C 9.In other words, be connected with p channel-type MISFETP4-L, P4-R respectively side by side with p channel-type MISFETT2-L, T2-R.Other formations are all identical with the 5th embodiment (Figure 14).And, at this,, also can use ferroelectric capacitor though use paraelectric capacitance as capacitor C 9.

Next, the action of reading to ferroelectric memory with above-mentioned sensor amplifier describes.The action of various signals etc. is all identical with the 5th embodiment (Figure 15, Figure 16).Therefore, at this, only control signal Vup is described to the action that the H level changes (control signal Vupb changes to the L level) later circuit 41B.

That is, during certain (for example, from the decline of signal Vblm begin through during behind the t2) after, if control signal Vup is set at the H level, then with control signal Vupb as the L level, p channel-type MISFETP4-L and P4-R become conducting state.Therefore, can improve as the first node Vmn-L of negative potential and the current potential of Section Point Vmn-R.Then, be in the threshold potential that the node Vmn-R of noble potential at first reaches p channel-type MISFETP1-L, P1-R, and by the p channel-type MISFET of the opposing party's side.

As mentioned above, also can bring into play the effect same in the present embodiment with the 5th embodiment.That is, owing to can suppress the current potential rising of the side among first node Vmn-L and the Section Point Vmn-R by the big countermeasure circuit 30 of electric charge, so can guarantee their potential difference (PD) significantly.Therefore, can improve and read tolerance limit.

And, by pull-up circuit 41B, the current potential of first node Vmn-L and Section Point Vmn-R can be risen to the current potential of circuit 30 actions.And, can reflect and the potential difference (PD) of bit line BL-L, BL-R simultaneously, can improve the current potential of first node Vmn-L and Section Point Vmn-R.Therefore, can realize further improving reading tolerance limit.In addition, even the bit line current potential is being changed to too much under the situation of negative potential, also can the current potential of first node Vmn-L and Section Point Vmn-R be risen to the current potential of circuit 30 actions by pull-up circuit.

(the 7th embodiment)

Also can change pull-up circuit 41A-L, the 41A-R of the 5th embodiment (Figure 14) and use the pull-up circuit (40,40A, 40B) of second embodiment～the 4th embodiment (Fig. 7, Figure 12, Figure 13).

Figure 23～Figure 25 is the circuit diagram of formation of the sense amplifier circuit (sensing circuit) of present embodiment.

First is suitable for example

As shown in figure 23, change pull-up circuit 41A-L, the 41A-R of the 5th embodiment (Figure 14) and the pull-up circuit (40) of second embodiment (Fig. 7) that pack into.

Particularly, between the 3rd node Vc-L and earthing potential, be connected with p channel-type MISFETP3-L, between the 4th node Vc-R and earthing potential, be connected with p channel-type MISFETP3-R.The grid of p channel-type MISFETP3-L and P3-R is connected in signal wire Vupb by capacitor C 7.And the back of the body grid of p channel-type MISFETP3-L and P3-R are connected in earthing potential.By connecting in this wise, can reduce leakage current to substrate.And, at this,, also can use ferroelectric capacitor though use paraelectric capacitance as capacitor C 7.

Second is suitable for example

As shown in figure 24, change pull-up circuit 41A-L, the 41A-R of the 5th embodiment (Figure 14) and the pull-up circuit (40A-L, 40A-R) of the 3rd embodiment (Figure 12) that pack into.

The 3rd is suitable for example

As shown in figure 25, change pull-up circuit 41A-L, the 41A-R of the 5th embodiment (Figure 14) and the pull-up circuit (40B-L, 40B-R) of the 4th embodiment (Figure 13) that pack into.

Being suitable for example～3rd above-mentioned first is suitable for example and (in the circuit of Figure 23～Figure 24), can makes the current potential (with reference to second embodiment～the 4th embodiment) that rises to circuit 30 actions as the current potential of the first node Vmn-L of negative potential and Section Point Vmn-R by pull-up circuit.

And then, even the bit line current potential is being changed to too much under the situation of negative potential, also can the current potential of first node Vmn-L and Section Point Vmn-R be risen to the current potential of circuit 30 actions by pull-up circuit.

In addition, in above-mentioned the 5th embodiment～the 7th embodiment,, also the present invention can be applicable to the ferroelectric memory of 1T1C though the ferroelectric memory of so-called 2T2C is illustrated.

And, also pull-up circuit illustrated in the 5th embodiment and the 6th embodiment (41A, 41B) can be applicable in the circuit of first embodiment (Fig. 2).And, also negative potential generation circuit 50 illustrated in the 5th embodiment can be applicable in the circuit of first embodiment (Fig. 2).

As mentioned above, according to purposes, the embodiment or the application examples that can illustrate the embodiment by foregoing invention are carried out suitable combination, perhaps change, improve the back and use, and the present invention is not limited to the description of above-mentioned embodiment.

Description of reference numerals

13-L, 13-R see-saw circuit

15-L, 15-R threshold potential (Vth) circuit for generating

17-L, 17-R negative potential circuit for generating

19-L, 19-R positive potential translation circuit

20 latch cicuits

The big countermeasure circuit of 30 electric charges

The little countermeasure circuit of 40 electric charges

40A-L, the little countermeasure circuit of 40A-R electric charge

40B-L, the little countermeasure circuit of 40B-R electric charge

41A-L, 41A-R pull-up circuit

50-L, 50-R negative potential circuit for generating

100 ferroelectric memories

110 memory cell arrays

120 word line traffic control sections

130 printed line control parts

140 bit line control parts

BL-L, BL-R bit line

C1-L, C1-R, C2-L, C2-R electric capacity

C5-L, C5-R tank capacitance

C7 electric capacity

C8-L, C8-R electric capacity

C9 electric capacity

INVL, INVR phase inverter

N1-L, N1-R, N2-L, N2-R n channel-type MISFET

P3-L, P3-R p channel-type MISFET

P4-L, P4-R p channel-type MISFET

The PL printed line

RL, PR resistance

T2-L, T2-R p channel-type MISFET

During t1, the t2

Vc-L, Vc-R node (node)

Vmn-L, Vmn-R node

The Vmngen control signal

Vsf-L, Vsf-R export (signal)

VswL, VswR switching transistor

VswmL, VswmR switching transistor

Vsw, Vswm control signal

Vthg-L, Vthg-R node

The Vthgen control signal

Vup, Vupb signal

The Vblm signal

The WL word line

Claims

1. ferroelectric memory comprises:

First electric charge transmits MISFET, is connected between first bit line and the first node;

Second electric charge transmits MISFET, is connected between second bit line and the Section Point;

First electric capacity is connected in described first node;

Second electric capacity is connected in described Section Point;

The one p channel-type MISFET is connected described first electric charge and transmits between MISFET and the described first node, and the grid of a described p channel-type MISFET is connected in described Section Point; And

The 2nd p channel-type MISFET is connected described second electric charge and transmits between MISFET and the described Section Point, and the grid of described the 2nd p channel-type MISFET is connected in described first node.

2. ferroelectric memory according to claim 1 is characterized in that,

Described first electric charge transmits MISFET and described second electric charge transmission MISFET is respectively p channel-type MISFET.

3. ferroelectric memory according to claim 1 and 2 is characterized in that,

Described ferroelectric memory also comprises first phase inverter and second phase inverter,

Described first phase inverter is connected described first bit line and described first electric charge transmits between the grid of MISFET, the input part of described first phase inverter is connected with described first bit line by the 3rd electric capacity, and the efferent of described first phase inverter is connected with the grid that described first electric charge transmits MISFET by the 4th electric capacity;

Described second phase inverter is connected second bit line and described second electric charge transmits between the grid of MISFET, the input part of described second phase inverter is connected with described second bit line by the 5th electric capacity, and the efferent of described second phase inverter is connected with the grid that described second electric charge transmits MISFET by the 6th electric capacity.

4. according to each described ferroelectric memory in the claim 1 to 3, it is characterized in that,

Described ferroelectric memory also comprises:

The 3rd p channel-type MISFET is connected as described first electric charge and transmits between the 3rd node and earthing potential of connected node of a MISFET and a described p channel-type MISFET; And

The 4th p channel-type MISFET is connected as described second electric charge and transmits between the 4th node and earthing potential of connected node of MISFET and described the 2nd p channel-type MISFET.

5. ferroelectric memory according to claim 4 is characterized in that,

Described the 3rd p channel-type MISFET and described the 4th p channel-type MISFET Be Controlled so that after reading of described ferroelectric memory moved beginning, and after during certain, become conducting state.

6. ferroelectric memory according to claim 3 is characterized in that,

Described ferroelectric memory also comprises:

The one n channel-type MISFET is connected between the efferent and earthing potential of described first phase inverter; And

The 2nd n channel-type MISFET is connected between the efferent and earthing potential of described second phase inverter.

7. ferroelectric memory according to claim 6 is characterized in that,

A described n channel-type MISFET and described the 2nd n channel-type MISFET Be Controlled so that after reading of described ferroelectric memory moved beginning, and after during certain, become conducting state.

8. ferroelectric memory according to claim 3 is characterized in that,

Described ferroelectric memory also comprises:

The 5th p channel-type MISFET is connected between the input part and power supply potential of described first phase inverter; And

The 6th p channel-type MISFET is connected between the efferent and power supply potential of described second phase inverter.

9. ferroelectric memory according to claim 8 is characterized in that,

Described the 5th p channel-type MISFET and described the 6th p channel-type MISFET Be Controlled so that after reading of described ferroelectric memory moved beginning, and after during certain, become conducting state.

10. according to each described ferroelectric memory in the claim 1 to 9, it is characterized in that,

Described first electric capacity, described second electric capacity are ferroelectric capacitors.

11. according to each described ferroelectric memory in the claim 1 to 9, it is characterized in that,

Described first electric capacity, described second electric capacity are gate capacitance.

12. according to each described ferroelectric memory in the claim 1 to 11, it is characterized in that,

On described first bit line and described second bit line, be connected with ferroelectric memory respectively.

13. according to each described ferroelectric memory in the claim 1 to 11, it is characterized in that,

On described first bit line, be connected with ferroelectric memory, be added with reference potential outside on described second bit line.

14. an electronic equipment is characterized in that, comprises each described ferroelectric memory in the claim 1 to 13.

15. a ferroelectric memory comprises:

The one p channel-type MISFET is connected between first node and the 3rd node, and the grid of a described p channel-type MISFET is connected in Section Point;

The 2nd p channel-type MISFET is connected between described Section Point and the 4th node, and the grid of described the 2nd p channel-type MISFET is connected in described first node;

First electric charge transmits MISFET, is connected between first bit line and described the 3rd node;

Second electric charge transmits MISFET, is connected between second bit line and described the 4th node;

First control circuit is connected described first bit line and described first electric charge and transmits between the first grid of MISFET, according to the current potential of described first bit line, and the current potential that control adds to described first grid;

Second control circuit is connected described second bit line and described second electric charge and transmits between the second grid of MISFET, according to the current potential of described second bit line, and the current potential that control adds to described second grid;

First electric capacity is connected in described first node;

Second electric capacity is connected in described Section Point;

The first negative potential generation circuit is connected in described first bit line; And

The second negative potential generation circuit is connected in described second bit line.

16. ferroelectric memory according to claim 15 is characterized in that,

17. according to claim 15 or 16 described ferroelectric memories, it is characterized in that,

Described first control circuit comprises first phase inverter, described first phase inverter is connected described first bit line and described first electric charge transmits between the grid of MISFET, the input part of described first phase inverter is connected with described first bit line by the 3rd electric capacity, the efferent of described first phase inverter is connected with the grid that described first electric charge transmits MISFET by the 4th electric capacity

Described second control circuit comprises second phase inverter, described second phase inverter is connected second bit line and described second electric charge transmits between the grid of MISFET, the input part of described second phase inverter is connected with described second bit line by the 5th electric capacity, and the efferent of described second phase inverter is connected with the grid that described second electric charge transmits MISFET by the 6th electric capacity.

18. according to each described ferroelectric memory in the claim 15 to 17, it is characterized in that,

The described first negative potential generation circuit comprises the 7th electric capacity, and described the 7th electric capacity is connected between described first bit line and first signal wire,

The described second negative potential generation circuit comprises the 8th electric capacity, and described the 8th electric capacity is connected between described second bit line and described first signal wire.

19. ferroelectric memory according to claim 18 is characterized in that, described the 7th electric capacity, described the 8th electric capacity are ferroelectric capacitors.

20. ferroelectric memory according to claim 18 is characterized in that, is connected with ferroelectric memory respectively on described first bit line or described second bit line,

Described the 7th electric capacity and described the 8th electric capacity are and the roughly the same electric capacity of ferroelectric capacitor that constitutes described ferroelectric memory.

21. ferroelectric memory according to claim 17 is characterized in that, described ferroelectric memory also comprises:

22. ferroelectric memory according to claim 21 is characterized in that, described ferroelectric memory also comprises:

The 3rd n channel-type MISFET is connected between the efferent and a described n channel-type MISFET of described first phase inverter, and its grid is connected in the input part of described first phase inverter; And

The 4th n channel-type MISFET is connected between the efferent and described the 2nd n channel-type MISFET of described second phase inverter, and its grid is connected in the input part of described second phase inverter.

23. according to claim 21 or 22 described ferroelectric memories, it is characterized in that,

A described n channel-type MISFET and described the 2nd n channel-type MISFET Be Controlled so that after the action of described first negative potential generation circuit and the described second negative potential generation circuit begins, and after during certain, become conducting state respectively.

24. according to each described ferroelectric memory in the claim 15 to 20, it is characterized in that,

Described ferroelectric memory also comprises:

Tricharged transmits MISFET, transmits MISFET with described first electric charge and is connected in parallel, and its grid is connected in the secondary signal line; And

The 4th electric charge transmits MISFET, transmits MISFET with described second electric charge and is connected in parallel, and its grid is connected in the secondary signal line.

25. according to each described ferroelectric memory in the claim 15 to 20, it is characterized in that,

Described ferroelectric memory also comprises:

The 3rd p channel-type MISFET is connected between described the 3rd node and the earthing potential, and its grid is connected in the secondary signal line; And

The 4th p channel-type MISFET is connected between described the 4th node and the earthing potential, and its grid is connected in the secondary signal line.

26. ferroelectric memory according to claim 17 is characterized in that,

Described ferroelectric memory also comprises:

The 5th p channel-type MISFET is connected between the input part and power supply potential of described first phase inverter, and its grid is connected in the secondary signal line; And

The 6th p channel-type MISFET is connected between the input part and power supply potential of described second phase inverter, and its grid is connected in the secondary signal line.

27. according to each described ferroelectric memory in the claim 24 to 26, it is characterized in that,

The current potential Be Controlled of described secondary signal line so that after the action of described first negative potential generation circuit and the described second negative potential generation circuit begins, and after during certain, changes.

28. according to each described ferroelectric memory in the claim 15 to 27, it is characterized in that,

Be connected with ferroelectric memory respectively on described first bit line and described second bit line.

29. according to each described ferroelectric memory in the claim 15 to 27, it is characterized in that,

30. an electronic equipment is characterized in that, comprises each described ferroelectric memory in the claim 15 to 29.